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[MIPS] Disassemble the 0xefefefef trap padding used by LLD
AbandonedPublic

Authored by arichardson on Jan 8 2018, 6:51 AM.

Details

Summary

Previously using llvm-objdump would just print a lot of 0xefefefef unknown
instructions. If we disassemble this as trap_ri it should be obvious that
it is a explicit trap padding rather than some instruction that is not
available because the wrong -triple was passed to llvm-objdump.

I am not sure if there trap_ri is the best mnemonic to use here, I just
decided to go for that since it will always cause a reserved instruction
trap.

Event Timeline

arichardson created this revision.Jan 8 2018, 6:51 AM

In fact, 0xef (111011b to be precise) is a valid start for the swc3 mips instruction. Take a look at LLVM test\MC\Disassembler\Mips\mips2\valid-mips2.txt. Right now I do not know why llvm-objdump does not show a correct instruction instead of "<unknown>". By the way GNU objdump shows "swc3 $15,-4113(ra)" for "efefefef".

ruiu added a subscriber: ruiu.Jan 8 2018, 2:42 PM

IIRC, 0xefefefef is chosen by Theo de Raadt.

grimar added a subscriber: grimar.Jan 9 2018, 3:11 AM

Right now I do not know why llvm-objdump does not show a correct instruction instead of "<unknown>". By the way GNU objdump shows "swc3 $15,-4113(ra)" for "efefefef".

It's not being disassembled as the disassembler sets the internal state to be mips32. The COP3 opcodes are only disassembled for MIPS-I and MIPS-II.

That opcode was repurposed in MIPSR6:

8: efefefef lwpc ra,0xffffbfc4

For micromips(r6):

10:	ef ef 	li16	$7, 111

Which is not particularly useful as trap instructions.

I'm a little uncertain as to what specific opcode we should use here. If we have a pure microMIPS or pure MIPS environment, we can use the corresponding 'sigrie' opcode from MIPSR6 to cause a reserved instruction trap. In revisions prior to revision 6, those instructions trap anyway.

In a mixed environment as we have a problem where we don't know what ISA mode we're operating in, so we'd have to alternate 'sigrie's as the microMIPSR6 'sigrie' corresponds to a valid MIPS64 no-op instruction and to ensure that the processor sees both if we've hit padding.

I've looked at the instruction tables and I believe that the MIPSR6 sigrie with the operand 1 is the best choice. Modulo a bug in upstream binutils, for microMIPS it disassembles to:

0:	04 17 	subu16	$3, $16, $17
2:	00 01  <unknown>
4:	04 17 	subu16	$3, $16, $17
6:	00 01  <unknown>

Which I believe is the simplest solution. That just requires a small change to lld, and providing an implementation of sigrie for MIPS in llvm.

Let's abandon this review because we need to implement the SIGRIE instruction support and use it for a trap padding in the LLD. I'm going to implement both parts of the plan.

arichardson abandoned this revision.Jul 4 2018, 11:00 AM

I'm going to implement both parts of the plan.

Thank you. (Please add a reference to this review in the new reviews so there's a link to find them.)

Support of SIGRIE instruction is implemented at rL346230. LLD related patch with new trap instruction is D54154.