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atanasyanatanasyan
committedNov 6, 2018
[mips] Support sigrie instruction
The `sigrie` instruction signals a Reserved Instruction Exception. This patch adds support for assembling / disassembling the instruction. Differential Revision: http://reviews.llvm.org/D53861 llvm-svn: 346230
·
llvmorg-21-initllvmorg-8.0.0-rc1
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9 files changed

+59
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9 files changed

+59
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‎llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td

+11
Original file line numberDiff line numberDiff line change
@@ -159,6 +159,7 @@ class SYNC_MMR6_ENC : POOL32A_SYNC_FM_MMR6;
159159
class SYNCI_MMR6_ENC : POOL32I_SYNCI_FM_MMR6, MMR6Arch<"synci">;
160160
class RDPGPR_MMR6_ENC : POOL32A_RDPGPR_FM_MMR6<0b1110000101>;
161161
class SDBBP_MMR6_ENC : SDBBP_FM_MM, MMR6Arch<"sdbbp">;
162+
class SIGRIE_MMR6_ENC : SIGRIE_FM_MM, MMR6Arch<"sigrie">;
162163
class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
163164
class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
164165
class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
@@ -1162,6 +1163,14 @@ class SDBBP_MMR6_DESC : MipsR6Inst {
11621163
InstrItinClass Itinerary = II_SDBBP;
11631164
}
11641165

1166+
class SIGRIE_MMR6_DESC : MipsR6Inst {
1167+
dag OutOperandList = (outs);
1168+
dag InOperandList = (ins uimm16:$code_);
1169+
string AsmString = !strconcat("sigrie", "\t$code_");
1170+
list<dag> Pattern = [];
1171+
InstrItinClass Itinerary = II_SIGRIE;
1172+
}
1173+
11651174
class LWM16_MMR6_DESC
11661175
: MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
11671176
!strconcat("lwm16", "\t$rt, $addr"), [],
@@ -1427,6 +1436,7 @@ def SYNCI_MMR6 : StdMMR6Rel, SYNCI_MMR6_DESC, SYNCI_MMR6_ENC, ISA_MICROMIPS32R6;
14271436
def RDPGPR_MMR6 : R6MMR6Rel, RDPGPR_MMR6_DESC, RDPGPR_MMR6_ENC,
14281437
ISA_MICROMIPS32R6;
14291438
def SDBBP_MMR6 : R6MMR6Rel, SDBBP_MMR6_DESC, SDBBP_MMR6_ENC, ISA_MICROMIPS32R6;
1439+
def SIGRIE_MMR6 : R6MMR6Rel, SIGRIE_MMR6_DESC, SIGRIE_MMR6_ENC, ISA_MICROMIPS32R6;
14301440
def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
14311441
def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
14321442
let DecoderMethod = "DecodeMemMMImm16" in {
@@ -1635,6 +1645,7 @@ def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
16351645
}
16361646
def : MipsInstAlias<"sync", (SYNC_MMR6 0), 1>, ISA_MICROMIPS32R6;
16371647
def : MipsInstAlias<"sdbbp", (SDBBP_MMR6 0), 1>, ISA_MICROMIPS32R6;
1648+
def : MipsInstAlias<"sigrie", (SIGRIE_MMR6 0), 1>, ISA_MICROMIPS32R6;
16381649
def : MipsInstAlias<"rdhwr $rt, $rs",
16391650
(RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>,
16401651
ISA_MICROMIPS32R6;

‎llvm/lib/Target/Mips/MicroMipsInstrFormats.td

+11
Original file line numberDiff line numberDiff line change
@@ -933,6 +933,17 @@ class SDBBP_FM_MM : MMArch {
933933
let Inst{5-0} = 0x3c;
934934
}
935935

936+
class SIGRIE_FM_MM : MMArch {
937+
bits<16> code_;
938+
939+
bits<32> Inst;
940+
941+
let Inst{31-26} = 0x0;
942+
let Inst{25-22} = 0x0;
943+
let Inst{21-6} = code_;
944+
let Inst{5-0} = 0b111111;
945+
}
946+
936947
class RDHWR_FM_MM : MMArch {
937948
bits<5> rt;
938949
bits<5> rd;

‎llvm/lib/Target/Mips/Mips32r6InstrFormats.td

+10
Original file line numberDiff line numberDiff line change
@@ -87,6 +87,7 @@ def OPCODE5_BC1NEZ : OPCODE5<0b01101>;
8787
def OPCODE5_BC2EQZ : OPCODE5<0b01001>;
8888
def OPCODE5_BC2NEZ : OPCODE5<0b01101>;
8989
def OPCODE5_BGEZAL : OPCODE5<0b10001>;
90+
def OPCODE5_SIGRIE : OPCODE5<0b10111>;
9091
// The next four constants are unnamed in the spec. These names are taken from
9192
// the OPGROUP names they are used with.
9293
def OPCODE5_LDC2 : OPCODE5<0b01110>;
@@ -602,3 +603,12 @@ class SPECIAL3_GINV<bits<2> ginv> : MipsR6Inst {
602603
let Inst{7-6} = ginv;
603604
let Inst{5-0} = 0b111101;
604605
}
606+
607+
class SIGRIE_FM : MipsR6Inst {
608+
bits<16> code_;
609+
610+
let Inst{31-26} = OPGROUP_REGIMM.Value;
611+
let Inst{25-21} = 0;
612+
let Inst{20-16} = OPCODE5_SIGRIE.Value;
613+
let Inst{15-0} = code_;
614+
}

‎llvm/lib/Target/Mips/Mips32r6InstrInfo.td

+12
Original file line numberDiff line numberDiff line change
@@ -200,6 +200,8 @@ class CRC32CW_ENC : SPECIAL3_2R_SZ_CRC<2,1>;
200200
class GINVI_ENC : SPECIAL3_GINV<0>;
201201
class GINVT_ENC : SPECIAL3_GINV<2>;
202202

203+
class SIGRIE_ENC : SIGRIE_FM;
204+
203205
//===----------------------------------------------------------------------===//
204206
//
205207
// Instruction Multiclasses
@@ -846,6 +848,14 @@ class GINVI_DESC : GINV_DESC_BASE<"ginvi", GPR32Opnd, II_GINVI> {
846848
}
847849
class GINVT_DESC : GINV_DESC_BASE<"ginvt", GPR32Opnd, II_GINVT>;
848850

851+
class SIGRIE_DESC {
852+
dag OutOperandList = (outs);
853+
dag InOperandList = (ins uimm16:$code_);
854+
string AsmString = "sigrie\t$code_";
855+
list<dag> Pattern = [];
856+
InstrItinClass Itinerary = II_SIGRIE;
857+
}
858+
849859
//===----------------------------------------------------------------------===//
850860
//
851861
// Instruction Definitions
@@ -961,6 +971,7 @@ let AdditionalPredicates = [NotInMicroMips] in {
961971
def SEL_S : R6MMR6Rel, SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT;
962972
def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
963973
def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
974+
def SIGRIE : SIGRIE_ENC, SIGRIE_DESC, ISA_MIPS32R6;
964975
}
965976

966977
let AdditionalPredicates = [NotInMicroMips] in {
@@ -988,6 +999,7 @@ def : MipsInstAlias<"evp", (EVP ZERO), 0>, ISA_MIPS32R6;
988999

9891000
let AdditionalPredicates = [NotInMicroMips] in {
9901001
def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6;
1002+
def : MipsInstAlias<"sigrie", (SIGRIE 0)>, ISA_MIPS32R6;
9911003
def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6, GPR_32;
9921004
}
9931005

‎llvm/lib/Target/Mips/MipsSchedule.td

+2
Original file line numberDiff line numberDiff line change
@@ -154,6 +154,7 @@ def II_DERET : InstrItinClass;
154154
def II_ERETNC : InstrItinClass;
155155
def II_EHB : InstrItinClass;
156156
def II_SDBBP : InstrItinClass;
157+
def II_SIGRIE : InstrItinClass;
157158
def II_SSNOP : InstrItinClass;
158159
def II_SYSCALL : InstrItinClass;
159160
def II_PAUSE : InstrItinClass;
@@ -546,6 +547,7 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
546547
InstrItinData<II_ERETNC , [InstrStage<1, [ALU]>]>,
547548
InstrItinData<II_EHB , [InstrStage<1, [ALU]>]>,
548549
InstrItinData<II_SDBBP , [InstrStage<1, [ALU]>]>,
550+
InstrItinData<II_SIGRIE , [InstrStage<1, [ALU]>]>,
549551
InstrItinData<II_SSNOP , [InstrStage<1, [ALU]>]>,
550552
InstrItinData<II_SYSCALL , [InstrStage<1, [ALU]>]>,
551553
InstrItinData<II_PAUSE , [InstrStage<1, [ALU]>]>,

‎llvm/lib/Target/Mips/MipsScheduleGeneric.td

+1-1
Original file line numberDiff line numberDiff line change
@@ -179,7 +179,7 @@ def GenericWriteTrap : SchedWriteRes<[GenericIssueCTISTD]>;
179179
def : ItinRW<[GenericWriteTrap], [II_BREAK, II_SYSCALL, II_TEQ, II_TEQI,
180180
II_TGE, II_TGEI, II_TGEIU, II_TGEU, II_TNE,
181181
II_TNEI, II_TLT, II_TLTI, II_TLTU, II_TTLTIU,
182-
II_TRAP, II_SDBBP]>;
182+
II_TRAP, II_SDBBP, II_SIGRIE]>;
183183

184184
// COP0 Pipeline
185185
// =============

‎llvm/test/MC/Mips/micromips32r6/valid.s

+4
Original file line numberDiff line numberDiff line change
@@ -169,6 +169,10 @@
169169
rdpgpr $3, $9 # CHECK: $3, $9 # encoding: [0x00,0x69,0xe1,0x7c]
170170
sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0xdb,0x7c]
171171
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x22,0xdb,0x7c]
172+
sigrie # CHECK: sigrie # encoding: [0x00,0x00,0x00,0x3f]
173+
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SIGRIE_MM
174+
sigrie 257 # CHECK: sigrie 257 # encoding: [0x00,0x00,0x40,0x7f]
175+
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SIGRIE_MM
172176
xor $3, $4, $5 # CHECK: xor $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x10]
173177
xori $3, $4, 1234 # CHECK: xori $3, $4, 1234 # encoding: [0x70,0x64,0x04,0xd2]
174178
sw $5, 4($6) # CHECK: sw $5, 4($6) # encoding: [0xf8,0xa6,0x00,0x04]

‎llvm/test/MC/Mips/mips32r6/valid.s

+4
Original file line numberDiff line numberDiff line change
@@ -281,6 +281,10 @@ a:
281281
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e]
282282
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
283283
# CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
284+
sigrie # CHECK: sigrie # encoding: [0x04,0x17,0x00,0x00]
285+
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SIGRIE
286+
sigrie 257 # CHECK: sigrie 257 # encoding: [0x04,0x17,0x01,0x01]
287+
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SIGRIE
284288
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
285289
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
286290
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]

‎llvm/test/MC/Mips/mips64r6/valid.s

+4
Original file line numberDiff line numberDiff line change
@@ -242,6 +242,10 @@ a:
242242
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e]
243243
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
244244
# CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
245+
sigrie # CHECK: sigrie # encoding: [0x04,0x17,0x00,0x00]
246+
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SIGRIE
247+
sigrie 257 # CHECK: sigrie 257 # encoding: [0x04,0x17,0x01,0x01]
248+
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SIGRIE
245249
sdc2 $20,629($s2) # CHECK: sdc2 $20, 629($18) # encoding: [0x49,0xf4,0x92,0x75]
246250
sel.d $f0,$f1,$f2 # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10]
247251
sel.s $f0,$f1,$f2 # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10]

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