[MachineCombiner] Improve debug output (NFC)

[avt77]

Summary

The suggested debug logging really improves the possibilty to check the job made by Machine Combiner.

[pdouglas]

lib/CodeGen/MachineCombiner.cpp

370

Typo: "DOES NOT improves" should be "DOES NOT improve"

[avt77]

The typo was fixed.

[RKSimon]

Adding extra MC reviewers

[fhahn]

Thanks. I've left some minor comments. Could you add the debug output created for an example? That would be helpful to get a better picture on the new format.

Also adding Gerolf as reviewer.

lib/CodeGen/MachineCombiner.cpp

19

What is this needed for?

140

I think we should wrap that in DEBUG.

436

I think we should wrap that in DEBUG.

499

I think mentioning that for the current matched pattern, those are the instructions going to be removed and inserted instead would be clearer.

500

const pointer?

505

const pointer?

571

Usually we do not use this->.

[fhahn]

nit: Something like [MachineCombiner] Improve debug output (NFC) as title seems slightly more compact

[avt77]

I fixed the comments raised by fhahn except the one: I can't show the new output format just now because we don't have real Machine Combiner Patterns tests at the moment. When I commit D40602 I'll be able to prepare such tests.

[RKSimon]

lib/CodeGen/MachineCombiner.cpp

140

Is STI used in this function? I couldn't see it.

581

If we're storing MF do we need to keep MRI and OptSize ?

[Gerolf]

lib/CodeGen/MachineCombiner.cpp

437

+ 1

Also, why recompute STI?

481

Duplicate info to what is displayed in the loops below?

499

The loops should be wrapped in DEBUG. Since this is a lot of info that is potentially logged I suggest to offer an option to enable this dump.

572

What motivates the changes in this function?

[avt77]

lib/CodeGen/MachineCombiner.cpp

437

It seems it's better to use *STI initialized in runOnFuction - I'll change it.

481

No, here we have only one possible instr to remove (the message should be changed). Below we could have a set of instrs to remove.

499

OK, I'll create such an option.

572

I'd like to store MF here to be able to calculate STI reference later but it seems I should store *STI here instead of that and use this pointer instead of reference..

[avt77]

Following requirements I got rid of class attribute MF and replaced it with STI. In addition I added special hidden switch to allow dump of substituted instructions.

[RKSimon]

lib/CodeGen/MachineCombiner.cpp

43

to match the other maybe make this "machine-combiner-dump-subst-intrs"

[avt77]

The name of the new switch was changed.

[RKSimon]

@fhahn @Gerolf Any more comments?

[fhahn]

Debug output with this patch for test/CodeGen/AArch64/machine-combiner.mir. I think it's an overall improvement , I just have a few more comments. I think it also would be worth explicitly stating that we applied a substitution.

Machine InstCombiner: inc_update_iterator_test
Combining MBB
Combining MBB
 Possible instr to replace
	 sched: [1:0.50]: %6:gpr32 = ADDWrr %3, killed %5Computing MinInstr trace through %bb.1
  pred for %bb.0: null
  pred for %bb.1: %bb.0
  succ for %bb.1: null

Depths for %bb.0:
      0 Instructions
0	%3:gpr32 = COPY %w2
0	%2:gpr32 = COPY %w1
0	%1:gpr32 = COPY %w0
0	%0:fpr64 = COPY %d0
0	%4:gpr32 = SUBSWrr %1:gpr32, %2:gpr32, implicit-def %nzcv
1	Bcc 13, %bb.2, implicit %nzcv
0	B %bb.1

Depths for %bb.1:
      3 Instructions
     2c @ A57UnitB (2 ops x6)
     1c @ A57UnitI (1 ops x3)
0	%5:gpr32 = MADDWrrr %1:gpr32, %2:gpr32, %wzr
3	%6:gpr32 = ADDWrr %3:gpr32, killed %5:gpr32
4	%7:fpr64 = SCVTFUWDri killed %6:gpr32
14	%8:fpr64 = FMULDrr %7:fpr64, %7:fpr64
19	%9:fpr64 = FADDDrr %0:fpr64, killed %8:fpr64
24	%d0 = COPY %9:fpr64
24	RET_ReallyLR implicit %d0
Heights for %bb.1:
      6 Instructions
     1c @ A57UnitB (1 ops x6)
     1c @ A57UnitI (1 ops x3)
     1c @ A57UnitL (1 ops x6)
     1c @ A57UnitM (1 ops x6)
     2c @ A57UnitV (3 ops x3)
24	0	RET_ReallyLR implicit %d0
24	0	%d0 = COPY %9:fpr64
24	5	%9:fpr64 = FADDDrr %0:fpr64, killed %8:fpr64
24	10	%8:fpr64 = FMULDrr %7:fpr64, %7:fpr64
24	20	%7:fpr64 = SCVTFUWDri killed %6:gpr32
24	21	%6:gpr32 = ADDWrr %3:gpr32, killed %5:gpr32
24	24	%5:gpr32 = MADDWrrr %1:gpr32, %2:gpr32, %wzr
%bb.1 Live-ins: %0@5 %3@21 %1@24 %2@24 WZR@24
Critical path: 24
  Dependence data for %6:gpr32 = ADDWrr %3:gpr32, killed %5:gpr32
	NewRootDepth: 1	RootDepth: 3
	NewRootLatency: 3	RootLatency: 4
	RootSlack: 0 SlackIsAccurate=1
	NewRootDepth + NewRootLatency = 4
	RootDepth + RootLatency + RootSlack = 7
	  It IMPROVES PathLen because
		NewCycleCount = 4, OldCycleCount = 7
		Resource length before replacement: 5 and after: 4
		  As result it IMPROVES/PRESERVES Resource Length
Invalidate %bb.1 MinInstr height.
Invalidate %bb.1 MinInstr depth.
 Possible instr to replace
	 sched: [5:0.50]: %9:fpr64 = FADDDrr %0, killed %8Computing MinInstr trace through %bb.1
  pred for %bb.1: %bb.0
  succ for %bb.1: null

Depths for %bb.1:
      3 Instructions
     2c @ A57UnitB (2 ops x6)
     1c @ A57UnitI (1 ops x3)
0	%6:gpr32 = MADDWrrr %1:gpr32, %2:gpr32, %3:gpr32
3	%7:fpr64 = SCVTFUWDri killed %6:gpr32
13	%8:fpr64 = FMULDrr %7:fpr64, %7:fpr64
18	%9:fpr64 = FADDDrr %0:fpr64, killed %8:fpr64
23	%d0 = COPY %9:fpr64
23	RET_ReallyLR implicit %d0
Heights for %bb.1:
      6 Instructions
     1c @ A57UnitB (1 ops x6)
     1c @ A57UnitI (1 ops x3)
     1c @ A57UnitL (1 ops x6)
     1c @ A57UnitM (1 ops x6)
     2c @ A57UnitV (3 ops x3)
23	0	RET_ReallyLR implicit %d0
23	0	%d0 = COPY %9:fpr64
23	5	%9:fpr64 = FADDDrr %0:fpr64, killed %8:fpr64
23	10	%8:fpr64 = FMULDrr %7:fpr64, %7:fpr64
23	20	%7:fpr64 = SCVTFUWDri killed %6:gpr32
23	23	%6:gpr32 = MADDWrrr %1:gpr32, %2:gpr32, %3:gpr32
%bb.1 Live-ins: %0@5 %1@23 %2@23 %3@23
Critical path: 23
  Dependence data for %9:fpr64 = FADDDrr %0:fpr64, killed %8:fpr64
	NewRootDepth: 13	RootDepth: 18
	NewRootLatency: 9	RootLatency: 10
	RootSlack: 0 SlackIsAccurate=1
	NewRootDepth + NewRootLatency = 22
	RootDepth + RootLatency + RootSlack = 28
	  It IMPROVES PathLen because
		NewCycleCount = 22, OldCycleCount = 28
		Resource length before replacement: 5 and after: 4
		  As result it IMPROVES/PRESERVES Resource Length
Invalidate %bb.1 MinInstr height.
Invalidate %bb.1 MinInstr depth.
Combining MBB

lib/CodeGen/MachineCombiner.cpp

437

Why did you drop this debug message? It seems helpful to know which instructions the machine combiner already visited. Although I can also see why one could argue why dropping it is ok, as we have the reference in which basic block we are at through the debug message at the beginning of the function

481

I think " Possible instr to replace" is not quite accurate. At this point we found > 0 patterns that could replace a pattern with MI as root.

482

What additional information does the SchedInfoStr add here?

483

I think we need a \n after print().

lib/CodeGen/MachineInstr.cpp

1216 ↗

(On Diff #129597)

The changes to MachineInstr.cpp seem unrelated to improving the debug output for the MachineCombiner?

[avt77]

lib/CodeGen/MachineCombiner.cpp

481

OK, "Possible patterns to replace the instr:\n" ? And in this case we need loop here, right?

482

We are able to compare lattency:throughput of original instr with replaced instrs.

lib/CodeGen/MachineInstr.cpp

1216 ↗

(On Diff #129597)

We call MachineInstr::print from MachineCombiner and here we try to improve the output if we don't have valid TII pointer (I saw such situations if the given istr was not included in any MachineFunction yet).

[avt77]

lib/CodeGen/MachineCombiner.cpp

437

Because we have such print below - see 479.

483

Why? print adds \n: do you like to see an empty string here?

[avt77]

I removed incorrect output about possibly removed instr: instead I added an output about Patterns used in combiner.

[avt77]

Ping.

[avt77]

fhahn, do you have any questions here?

[fhahn]

Thanks, and sorry for taking so long to come back to this. I think it looks good, there is just the missing newline issue. After that's resolved I would be happy to sign off on the machine combiner changes, but I would prefer if we move the lib/CodeGen/MachineInstr.cpp to a separate patch.

lib/CodeGen/MachineCombiner.cpp

500

I do not think we reference the pattern ID anywhere else, so I am not sure how it would be helpful here. Also, should Pattern be lowercase?

503

I think you need \n after the print calls in your patch . I get the following output (see the machine instrs all on the same line):

	For the Pattern (21) these instructions could be removed
		 sched: [5:0.50]: %8:fpr64 = FMULDrr %7, %7		 sched: [5:0.50]: %9:fpr64 = FADDDrr %0, killed %8	These instructions could replace the removed ones
		 sched: [9:0.50]: %9 = UNKNOWN %7, %7, %0Computing MinInstr trace through %bb.1

[avt77]

1. The issue with "\n" was fixed.
2. About pattern ID in output: in theory there could be several patterns for one Root and every pattern could have several alternative sequences, right? I think in this case the pattern ID will help to distinguish all these removed/substituted sequences from each other. Am I right or it's better to remove the IDs?

[fhahn]

About pattern ID in output: in theory there could be several patterns for one Root and every pattern could have several alternative sequences, right? I think in this case the pattern ID will help to distinguish all these removed/substituted sequences from each other. Am I right or it's better to remove the IDs?

Right thanks!

MachineCombiner part LGTM now. I still would prefer if you submit it without the change in lib/CodeGen/MachineInstr.cpp and do that in a separate change.

[avt77]

MachineCombiner part LGTM now. I still would prefer if you submit it without the change in lib/CodeGen/MachineInstr.cpp and do that in a separate change.

OK, I'll do it as a separate patch.

[RKSimon]

In D41278#1008470, @avt77 wrote:

MachineCombiner part LGTM now. I still would prefer if you submit it without the change in lib/CodeGen/MachineInstr.cpp and do that in a separate change.

OK, I'll do it as a separate patch.

AFAICT the MachineCombiner.cpp part landed at rL325217 - @fhahn are you happy for the MachineInstr.cpp diff just to be committed or do you want @avt77 to raise another phab?

[avt77]

I was going to commit it as a part of D40602 because the isue raised there. Is it OK?

[RKSimon]

Commit it by itself, no need to wait for another review, as long as its a separate commit its fine to tag it with 'Differential Revision: https://reviews.llvm.org/D41278' (like you should have done for rL325217 as well).

lib/CodeGen/MachineCombiner.cpp

 // instructions do not lengthen the critical path or the resource depth.
 //===----------------------------------------------------------------------===//
 
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineLoopInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/MachineTraceMetrics.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/CodeGen/TargetSchedule.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "machine-combiner"
 
 STATISTIC(NumInstCombined, "Number of machineinst combined");
 
 static cl::opt<unsigned>
 inc_threshold("machine-combiner-inc-threshold", cl::Hidden,
               cl::desc("Incremental depth computation will be used for basic "
                        "blocks with more instructions."), cl::init(500));
 
 namespace {
 class MachineCombiner : public MachineFunctionPass {
+  MachineFunction *MF;
   const TargetInstrInfo *TII;
   const TargetRegisterInfo *TRI;
   MCSchedModel SchedModel;
   MachineRegisterInfo *MRI;
   MachineLoopInfo *MLI; // Current MachineLoopInfo
   MachineTraceMetrics *Traces;
   MachineTraceMetrics::Ensemble *MinInstr;
 

 unsigned
 MachineCombiner::getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
                           DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
                           MachineTraceMetrics::Trace BlockTrace) {
   SmallVector<unsigned, 16> InstrDepth;
   assert(TSchedModel.hasInstrSchedModelOrItineraries() &&
          "Missing machine model\n");
 
+  const TargetSubtargetInfo &STI = MF->getSubtarget();
+
   // For each instruction in the new sequence compute the depth based on the
   // operands. Use the trace information when possible. For new operands which
   // are tracked in the InstrIdxForVirtReg map depth is looked up in InstrDepth
+  DEBUG(dbgs() << "  Could be replaced with\n");
   for (auto *InstrPtr : InsInstrs) { // for each Use
     unsigned IDepth = 0;
-    DEBUG(dbgs() << "NEW INSTR ";
-          InstrPtr->print(dbgs(), TII);
-          dbgs() << "\n";);
+    DEBUG(dbgs() << "\t" << STI.getSchedInfoStr(*InstrPtr) << ": ";
+          InstrPtr->print(dbgs(), false, false, TII););
     for (const MachineOperand &MO : InstrPtr->operands()) {
       // Check for virtual register operand.
       if (!(MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())))
         continue;
       if (!MO.isUse())
         continue;
       unsigned DepthOp = 0;
       unsigned LatencyOp = 0;
bool MachineCombiner::improvesCriticalPathLen(
   // NewRoot is the last instruction in the \p InsInstrs vector.
   unsigned NewRootIdx = InsInstrs.size() - 1;
   MachineInstr *NewRoot = InsInstrs[NewRootIdx];
 
   // Get depth and latency of NewRoot and Root.
   unsigned NewRootDepth = getDepth(InsInstrs, InstrIdxForVirtReg, BlockTrace);
   unsigned RootDepth = BlockTrace.getInstrCycles(*Root).Depth;
 
-  DEBUG(dbgs() << "DEPENDENCE DATA FOR " << *Root << "\n";
-        dbgs() << " NewRootDepth: " << NewRootDepth << "\n";
-        dbgs() << " RootDepth: " << RootDepth << "\n");
+  DEBUG(dbgs() << "  Dependence data for " << *Root << "\tNewRootDepth: "
+               << NewRootDepth << "\tRootDepth: " << RootDepth);
 
   // For a transform such as reassociation, the cost equation is
   // conservatively calculated so that we must improve the depth (data
   // dependency cycles) in the critical path to proceed with the transform.
   // Being conservative also protects against inaccuracies in the underlying
   // machine trace metrics and CPU models.
-  if (getCombinerObjective(Pattern) == CombinerObjective::MustReduceDepth)
+  if (getCombinerObjective(Pattern) == CombinerObjective::MustReduceDepth) {
+    DEBUG(dbgs() << "\tIt MustReduceDepth ");
+    DEBUG(NewRootDepth < RootDepth ? dbgs() << "\t  and it does it\n"
+                                   : dbgs() << "\t  but it does NOT do it\n");
     return NewRootDepth < RootDepth;
+  }
 
   // A more flexible cost calculation for the critical path includes the slack
   // of the original code sequence. This may allow the transform to proceed
   // even if the instruction depths (data dependency cycles) become worse.
 
   // Account for the latency of the inserted and deleted instructions by
   // adding up their latencies. This assumes that the inserted and deleted
   // instructions are dependent instruction chains, which might not hold
   // in all cases.
   unsigned NewRootLatency = 0;
   for (unsigned i = 0; i < InsInstrs.size() - 1; i++)
     NewRootLatency += TSchedModel.computeInstrLatency(InsInstrs[i]);
   NewRootLatency += getLatency(Root, NewRoot, BlockTrace);
 
   unsigned RootLatency = 0;
   for (auto I : DelInstrs)
     RootLatency += TSchedModel.computeInstrLatency(I);
 
   unsigned RootSlack = BlockTrace.getInstrSlack(*Root);
   unsigned NewCycleCount = NewRootDepth + NewRootLatency;
-  unsigned OldCycleCount = RootDepth + RootLatency +
-                           (SlackIsAccurate ? RootSlack : 0);
-  DEBUG(dbgs() << " NewRootLatency: " << NewRootLatency << "\n";
-        dbgs() << " RootLatency: " << RootLatency << "\n";
-        dbgs() << " RootSlack: " << RootSlack << " SlackIsAccurate="
-               << SlackIsAccurate << "\n";
-        dbgs() << " NewRootDepth + NewRootLatency = "
-               << NewCycleCount << "\n";
-        dbgs() << " RootDepth + RootLatency + RootSlack = "
-               << OldCycleCount << "\n";
-        );
+  unsigned OldCycleCount =
+      RootDepth + RootLatency + (SlackIsAccurate ? RootSlack : 0);
+  DEBUG(dbgs() << "\n\tNewRootLatency: " << NewRootLatency << "\tRootLatency: "
+               << RootLatency << "\n\tRootSlack: " << RootSlack
+               << " SlackIsAccurate=" << SlackIsAccurate
+               << "\n\tNewRootDepth + NewRootLatency = " << NewCycleCount
+               << "\n\tRootDepth + RootLatency + RootSlack = "
+               << OldCycleCount;);
+  DEBUG(NewCycleCount <= OldCycleCount
+            ? dbgs() << "\n\t  It IMPROVES PathLen because"
+            : dbgs() << "\n\t  It DOES NOT improve PathLen because");
+  DEBUG(dbgs() << "\n\t\tNewCycleCount = " << NewCycleCount <<
+        ", OldCycleCount = " << OldCycleCount << "\n");
 
   return NewCycleCount <= OldCycleCount;
 }
 
 /// helper routine to convert instructions into SC
 void MachineCombiner::instr2instrSC(
     SmallVectorImpl<MachineInstr *> &Instrs,
     SmallVectorImpl<const MCSchedClassDesc *> &InstrsSC) {
bool MachineCombiner::preservesResourceLen(
 
   ArrayRef<const MCSchedClassDesc *> MSCInsArr = makeArrayRef(InsInstrsSC);
   ArrayRef<const MCSchedClassDesc *> MSCDelArr = makeArrayRef(DelInstrsSC);
 
   // Compute new resource length.
   unsigned ResLenAfterCombine =
       BlockTrace.getResourceLength(MBBarr, MSCInsArr, MSCDelArr);
 
-  DEBUG(dbgs() << "RESOURCE DATA: \n";
-        dbgs() << " resource len before: " << ResLenBeforeCombine
-               << " after: " << ResLenAfterCombine << "\n";);
+  DEBUG(dbgs() << "\t\tResource length before replacement: "
+               << ResLenBeforeCombine << " and after: " << ResLenAfterCombine
+               << "\n";);
+  DEBUG(
+      ResLenAfterCombine <= ResLenBeforeCombine
+          ? dbgs() << "\t\t  As result it IMPROVES/PRESERVES Resource Length\n"
+          : dbgs() << "\t\t  As result it DOES NOT improve/preserve Resource "
+                      "Length\n");
 
   return ResLenAfterCombine <= ResLenBeforeCombine;
 }
 
 /// \returns true when new instruction sequence should be generated
 /// independent if it lengthens critical path or not
 bool MachineCombiner::doSubstitute(unsigned NewSize, unsigned OldSize) {
   if (OptSize && (NewSize < OldSize))

 /// The prototype of such a pattern is MUl + ADD -> MADD. Performs instruction
 /// combining based on machine trace metrics. Only combine a sequence of
 /// instructions  when this neither lengthens the critical path nor increases
 /// resource pressure. When optimizing for codesize always combine when the new
 /// sequence is shorter.
 bool MachineCombiner::combineInstructions(MachineBasicBlock *MBB) {
   bool Changed = false;
   DEBUG(dbgs() << "Combining MBB " << MBB->getName() << "\n");
+  const TargetSubtargetInfo &STI = MF->getSubtarget();
 
   bool IncrementalUpdate = false;
   auto BlockIter = MBB->begin();
   decltype(BlockIter) LastUpdate;
   // Check if the block is in a loop.
   const MachineLoop *ML = MLI->getLoopFor(MBB);
   if (!MinInstr)
     MinInstr = Traces->getEnsemble(MachineTraceMetrics::TS_MinInstrCount);
 
   SparseSet<LiveRegUnit> RegUnits;
   RegUnits.setUniverse(TRI->getNumRegUnits());
 
   while (BlockIter != MBB->end()) {
     auto &MI = *BlockIter++;
-
-    DEBUG(dbgs() << "INSTR "; MI.dump(); dbgs() << "\n";);
     SmallVector<MachineCombinerPattern, 16> Patterns;
+
     // The motivating example is:
     //
     //     MUL  Other        MUL_op1 MUL_op2  Other
     //      \    /               \      |    /
     //      ADD/SUB      =>        MADD/MSUB
     //      (=Root)                (=NewRoot)
 
     // The DAGCombine code always replaced MUL + ADD/SUB by MADD. While this is
while (BlockIter != MBB->end()) {
     // The algorithm does not try to evaluate all patterns and pick the best.
     // This is only an artificial restriction though. In practice there is
     // mostly one pattern, and getMachineCombinerPatterns() can order patterns
     // based on an internal cost heuristic.
 
     if (!TII->getMachineCombinerPatterns(MI, Patterns))
       continue;
 
+    DEBUG(dbgs() << " Possible instr(s) to replace\n");
+    DEBUG(dbgs() << "\t" << STI.getSchedInfoStr(MI) << ": ";
+          MI.print(dbgs(), false, false, TII););
+
     for (auto P : Patterns) {
       SmallVector<MachineInstr *, 16> InsInstrs;
       SmallVector<MachineInstr *, 16> DelInstrs;
       DenseMap<unsigned, unsigned> InstrIdxForVirtReg;
       TII->genAlternativeCodeSequence(MI, P, InsInstrs, DelInstrs,
                                       InstrIdxForVirtReg);
       unsigned NewInstCount = InsInstrs.size();
       unsigned OldInstCount = DelInstrs.size();
       // Found pattern, but did not generate alternative sequence.
       // This can happen e.g. when an immediate could not be materialized
       // in a single instruction.
       if (!NewInstCount)
         continue;
 
+      DEBUG(dbgs() << "\tDelInstrs\n");
+      for (auto *InstrPtr : DelInstrs) {
+        DEBUG(dbgs() << "\t\t" << STI.getSchedInfoStr(*InstrPtr) << ": ";
+              InstrPtr->print(dbgs(), false, false, TII););
+      }
+      DEBUG(dbgs() << "\tInsInstrs\n");
+      for (auto *InstrPtr : InsInstrs) {
+        DEBUG(dbgs() << "\t\t" << STI.getSchedInfoStr(*InstrPtr) << ": ";
+              InstrPtr->print(dbgs(), false, false, TII););
+      }
+
       bool SubstituteAlways = false;
       if (ML && TII->isThroughputPattern(P))
         SubstituteAlways = true;
 
       if (IncrementalUpdate) {
         // Update depths since the last incremental update.
         MinInstr->updateDepths(LastUpdate, BlockIter, RegUnits);
         LastUpdate = BlockIter;
bool MachineCombiner::combineInstructions(MachineBasicBlock *MBB) {
   }
 
   if (Changed && IncrementalUpdate)
     Traces->invalidate(MBB);
   return Changed;
 }
 
 bool MachineCombiner::runOnMachineFunction(MachineFunction &MF) {
+  this->MF = &MF;
   const TargetSubtargetInfo &STI = MF.getSubtarget();
   TII = STI.getInstrInfo();
   TRI = STI.getRegisterInfo();
   SchedModel = STI.getSchedModel();
   TSchedModel.init(SchedModel, &STI, TII);
   MRI = &MF.getRegInfo();
   MLI = &getAnalysis<MachineLoopInfo>();
   Traces = &getAnalysis<MachineTraceMetrics>();
   MinInstr = nullptr;
   OptSize = MF.getFunction()->optForSize();
 
   DEBUG(dbgs() << getPassName() << ": " << MF.getName() << '\n');
   if (!TII->useMachineCombiner()) {
     DEBUG(dbgs() << "  Skipping pass: Target does not support machine combiner\n");
     return false;
   }
 
   bool Changed = false;
 
   // Try to combine instructions.
   for (auto &MBB : MF)
     Changed |= combineInstructions(&MBB);
 
   return Changed;
 }