[CodeGen] Unify MBB reference format in both MIR and debug output

[thegameg]

Summary

As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'.

The MIR printer prints the IR name of a MBB only for block definitions.

• find . \( -name "*.cpp" -o -name "*.h" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g'
• find . \( -name "*.cpp" -o -name "*.h" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g'
• find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g'
• grep -nr 'BB#' and fix

This patch des not include tests because it exceeds the 8MB limit (even without context).

[MatzeB]

One thing I always found odd with the MIR format is that all the MBB references repeated the IR name of the basic block. Even though it would be perfectly fine to only print the IR reference once where the block is defined and not for every reference.

How about changing printMBBReference() to never print the .name suffix and change the MI parser to optionally accept it to accomodate old .mir files, but new .mir files would not print it anymore in MBB references?

lib/CodeGen/BranchFolding.cpp

616–617

Use printMBBReference()? The same applies to various other debug printers below.

[MatzeB]

Thanks, LGTM.

lib/CodeGen/MachineScheduler.cpp

101

I think you can leave the MBB# here to make it more clear that the argument is a number.

include/llvm/CodeGen/MachineBasicBlock.h

 #include "llvm/ADT/iterator_range.h"
 #include "llvm/ADT/simple_ilist.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineInstrBundleIterator.h"
 #include "llvm/IR/DebugLoc.h"
 #include "llvm/MC/LaneBitmask.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/Support/BranchProbability.h"
+#include "llvm/Support/Printable.h"
 #include <cassert>
 #include <cstdint>
 #include <functional>
 #include <iterator>
 #include <string>
 #include <vector>
 
 namespace llvm {
private:
   /// Remove Pred as a predecessor of this MachineBasicBlock. Don't do this
   /// unless you know what you're doing, because it doesn't update Pred's
   /// successors list. Use Pred->removeSuccessor instead.
   void removePredecessor(MachineBasicBlock *Pred);
 };
 
 raw_ostream& operator<<(raw_ostream &OS, const MachineBasicBlock &MBB);
 
+/// Prints a machine basic block reference.
+///
+/// The format is:
+///   %bb.5           - a machine basic block without a named IR basic block.
+///   %bb.5.name      - a machine basic block with a named IR basic block.
+///
+/// Usage: OS << printMBBReference(MBB) << '\n';
+Printable printMBBReference(const MachineBasicBlock &MBB);
+
 // This is useful when building IndexedMaps keyed on basic block pointers.
 struct MBB2NumberFunctor {
   using argument_type = const MachineBasicBlock *;
   unsigned operator()(const MachineBasicBlock *MBB) const {
     return MBB->getNumber();
   }
 };
 

lib/CodeGen/AsmPrinter/AsmPrinter.cpp

if (isVerbose()) {
     emitBasicBlockLoopComments(MBB, LI, *this);
   }
 
   // Print the main label for the block.
   if (MBB.pred_empty() ||
       (isBlockOnlyReachableByFallthrough(&MBB) && !MBB.isEHFuncletEntry())) {
     if (isVerbose()) {
       // NOTE: Want this comment at start of line, don't emit with AddComment.
-      OutStreamer->emitRawComment(" BB#" + Twine(MBB.getNumber()) + ":", false);
+      OutStreamer->emitRawComment(" %bb." + Twine(MBB.getNumber()) + ":", false);
     }
   } else {
     OutStreamer->EmitLabel(MBB.getSymbol());
   }
 }
 
 void AsmPrinter::EmitBasicBlockEnd(const MachineBasicBlock &MBB) {
   MCCodePaddingContext Context;

lib/CodeGen/BranchFolding.cpp

if (!FuncletMembership.empty()) {
     assert(Funclet2 != FuncletMembership.end());
     if (Funclet1->second != Funclet2->second)
       return false;
   }
 
   CommonTailLen = ComputeCommonTailLength(MBB1, MBB2, I1, I2);
   if (CommonTailLen == 0)
     return false;
-  DEBUG(dbgs() << "Common tail length of BB#" << MBB1->getNumber()
-               << " and BB#" << MBB2->getNumber() << " is " << CommonTailLen
+  DEBUG(dbgs() << "Common tail length of %bb." << MBB1->getNumber()
+               << " and %bb." << MBB2->getNumber() << " is " << CommonTailLen
                << '\n');
 
   // It's almost always profitable to merge any number of non-terminator
   // instructions with the block that falls through into the common successor.
   // This is true only for a single successor. For multiple successors, we are
   // trading a conditional branch for an unconditional one.
   // TODO: Re-visit successor size for non-layout tail merging.
   if ((MBB1 == PredBB || MBB2 == PredBB) &&
if (t <= TimeEstimate) {
       commonTailIndex = i;
     }
   }
 
   MachineBasicBlock::iterator BBI =
     SameTails[commonTailIndex].getTailStartPos();
   MachineBasicBlock *MBB = SameTails[commonTailIndex].getBlock();
 
-  DEBUG(dbgs() << "\nSplitting BB#" << MBB->getNumber() << ", size "
+  DEBUG(dbgs() << "\nSplitting %bb." << MBB->getNumber() << ", size "
                << maxCommonTailLength);
 
   // If the split block unconditionally falls-thru to SuccBB, it will be
   // merged. In control flow terms it should then take SuccBB's name. e.g. If
   // SuccBB is an inner loop, the common tail is still part of the inner loop.
   const BasicBlock *BB = (SuccBB && MBB->succ_size() == 1) ?
     SuccBB->getBasicBlock() : MBB->getBasicBlock();
   MachineBasicBlock *newMBB = SplitMBBAt(*MBB, BBI, BB);

 // there are at least this many instructions in common.
 bool BranchFolder::TryTailMergeBlocks(MachineBasicBlock *SuccBB,
                                       MachineBasicBlock *PredBB,
                                       unsigned MinCommonTailLength) {
   bool MadeChange = false;
 
   DEBUG(dbgs() << "\nTryTailMergeBlocks: ";
         for (unsigned i = 0, e = MergePotentials.size(); i != e; ++i)
-          dbgs() << "BB#" << MergePotentials[i].getBlock()->getNumber()
+          dbgs() << "%bb." << MergePotentials[i].getBlock()->getNumber()
                  << (i == e-1 ? "" : ", ");
         dbgs() << "\n";
         if (SuccBB) {
-          dbgs() << "  with successor BB#" << SuccBB->getNumber() << '\n';
+          dbgs() << "  with successor %bb." << SuccBB->getNumber() << '\n';
           if (PredBB)
-            dbgs() << "  which has fall-through from BB#"
+            dbgs() << "  which has fall-through from %bb."
                    << PredBB->getNumber() << "\n";
         }
         dbgs() << "Looking for common tails of at least "
                << MinCommonTailLength << " instruction"
                << (MinCommonTailLength == 1 ? "" : "s") << '\n';
        );
 
   // Sort by hash value so that blocks with identical end sequences sort
while (MergePotentials.size() > 1) {
     setCommonTailEdgeWeights(*MBB);
 
     // Merge debug locations, MMOs and undef flags across identical instructions
     // for common tail.
     mergeCommonTails(commonTailIndex);
 
     // MBB is common tail.  Adjust all other BB's to jump to this one.
     // Traversal must be forwards so erases work.
-    DEBUG(dbgs() << "\nUsing common tail in BB#" << MBB->getNumber()
+    DEBUG(dbgs() << "\nUsing common tail in %bb." << MBB->getNumber()
                  << " for ");
     for (unsigned int i=0, e = SameTails.size(); i != e; ++i) {
       if (commonTailIndex == i)
         continue;
-      DEBUG(dbgs() << "BB#" << SameTails[i].getBlock()->getNumber()
+      DEBUG(dbgs() << "%bb." << SameTails[i].getBlock()->getNumber()
                    << (i == e-1 ? "" : ", "));
       // Hack the end off BB i, making it jump to BB commonTailIndex instead.
       replaceTailWithBranchTo(SameTails[i].getTailStartPos(), *MBB);
       // BB i is no longer a predecessor of SuccBB; remove it from the worklist.
       MergePotentials.erase(SameTails[i].getMPIter());
     }
     DEBUG(dbgs() << "\n");
     // We leave commonTailIndex in the worklist in case there are other blocks

lib/CodeGen/BranchRelaxation.cpp

 #endif
 }
 
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 /// print block size and offset information - debugging
 LLVM_DUMP_METHOD void BranchRelaxation::dumpBBs() {
   for (auto &MBB : *MF) {
     const BasicBlockInfo &BBI = BlockInfo[MBB.getNumber()];
-    dbgs() << format("BB#%u\toffset=%08x\t", MBB.getNumber(), BBI.Offset)
+    dbgs() << format("%bb.%u\toffset=%08x\t", MBB.getNumber(), BBI.Offset)
            << format("size=%#x\n", BBI.Size);
   }
 }
 #endif
 
 /// scanFunction - Do the initial scan of the function, building up
 /// information about each block.
 void BranchRelaxation::scanFunction() {
bool BranchRelaxation::isBlockInRange(
   const MachineInstr &MI, const MachineBasicBlock &DestBB) const {
   int64_t BrOffset = getInstrOffset(MI);
   int64_t DestOffset = BlockInfo[DestBB.getNumber()].Offset;
 
   if (TII->isBranchOffsetInRange(MI.getOpcode(), DestOffset - BrOffset))
     return true;
 
   DEBUG(
-    dbgs() << "Out of range branch to destination BB#" << DestBB.getNumber()
-           << " from BB#" << MI.getParent()->getNumber()
+    dbgs() << "Out of range branch to destination %bb." << DestBB.getNumber()
+           << " from %bb." << MI.getParent()->getNumber()
            << " to " << DestOffset
            << " offset " << DestOffset - BrOffset
            << '\t' << MI
   );
 
   return false;
 }
 
if (FBB && isBlockInRange(MI, *FBB)) {
     if (TRI->trackLivenessAfterRegAlloc(*MF))
       computeAndAddLiveIns(LiveRegs, NewBB);
   }
 
   // We now have an appropriate fall-through block in place (either naturally or
   // just created), so we can invert the condition.
   MachineBasicBlock &NextBB = *std::next(MachineFunction::iterator(MBB));
 
-  DEBUG(dbgs() << "  Insert B to BB#" << TBB->getNumber()
-               << ", invert condition and change dest. to BB#"
+  DEBUG(dbgs() << "  Insert B to %bb." << TBB->getNumber()
+               << ", invert condition and change dest. to %bb."
                << NextBB.getNumber() << '\n');
 
   unsigned &MBBSize = BlockInfo[MBB->getNumber()].Size;
 
   // Insert a new conditional branch and a new unconditional branch.
   int RemovedSize = 0;
   TII->reverseBranchCondition(Cond);
   TII->removeBranch(*MBB, &RemovedSize);

lib/CodeGen/EarlyIfConversion.cpp

 /// the defining instructions are added to InsertAfter.
 ///
 /// Any clobbered regunits are added to ClobberedRegUnits.
 ///
 bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) {
   // Reject any live-in physregs. It's probably CPSR/EFLAGS, and very hard to
   // get right.
   if (!MBB->livein_empty()) {
-    DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has live-ins.\n");
+    DEBUG(dbgs() << "%bb." << MBB->getNumber() << " has live-ins.\n");
     return false;
   }
 
   unsigned InstrCount = 0;
 
   // Check all instructions, except the terminators. It is assumed that
   // terminators never have side effects or define any used register values.
   for (MachineBasicBlock::iterator I = MBB->begin(),
        E = MBB->getFirstTerminator(); I != E; ++I) {
     if (I->isDebugValue())
       continue;
 
     if (++InstrCount > BlockInstrLimit && !Stress) {
-      DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has more than "
+      DEBUG(dbgs() << "%bb." << MBB->getNumber() << " has more than "
                    << BlockInstrLimit << " instructions.\n");
       return false;
     }
 
     // There shouldn't normally be any phis in a single-predecessor block.
     if (I->isPHI()) {
       DEBUG(dbgs() << "Can't hoist: " << *I);
       return false;
for (const MachineOperand &MO : I->operands()) {
           ClobberedRegUnits.set(*Units);
 
       if (!MO.readsReg() || !TargetRegisterInfo::isVirtualRegister(Reg))
         continue;
       MachineInstr *DefMI = MRI->getVRegDef(Reg);
       if (!DefMI || DefMI->getParent() != Head)
         continue;
       if (InsertAfter.insert(DefMI).second)
-        DEBUG(dbgs() << "BB#" << MBB->getNumber() << " depends on " << *DefMI);
+        DEBUG(dbgs() << "%bb." << MBB->getNumber() << " depends on " << *DefMI);
       if (DefMI->isTerminator()) {
         DEBUG(dbgs() << "Can't insert instructions below terminator.\n");
         return false;
       }
     }
   }
   return true;
 }
bool SSAIfConv::canConvertIf(MachineBasicBlock *MBB) {
   Tail = Succ0->succ_begin()[0];
 
   // This is not a triangle.
   if (Tail != Succ1) {
     // Check for a diamond. We won't deal with any critical edges.
     if (Succ1->pred_size() != 1 || Succ1->succ_size() != 1 ||
         Succ1->succ_begin()[0] != Tail)
       return false;
-    DEBUG(dbgs() << "\nDiamond: BB#" << Head->getNumber()
-                 << " -> BB#" << Succ0->getNumber()
-                 << "/BB#" << Succ1->getNumber()
-                 << " -> BB#" << Tail->getNumber() << '\n');
+    DEBUG(dbgs() << "\nDiamond: %bb." << Head->getNumber()
+                 << " -> %bb." << Succ0->getNumber()
+                 << "/%bb." << Succ1->getNumber()
+                 << " -> %bb." << Tail->getNumber() << '\n');
 
     // Live-in physregs are tricky to get right when speculating code.
     if (!Tail->livein_empty()) {
       DEBUG(dbgs() << "Tail has live-ins.\n");
       return false;
     }
   } else {
-    DEBUG(dbgs() << "\nTriangle: BB#" << Head->getNumber()
-                 << " -> BB#" << Succ0->getNumber()
-                 << " -> BB#" << Tail->getNumber() << '\n');
+    DEBUG(dbgs() << "\nTriangle: %bb." << Head->getNumber()
+                 << " -> %bb." << Succ0->getNumber()
+                 << " -> %bb." << Tail->getNumber() << '\n');
   }
 
   // This is a triangle or a diamond.
   // If Tail doesn't have any phis, there must be side effects.
   if (Tail->empty() || !Tail->front().isPHI()) {
     DEBUG(dbgs() << "No phis in tail.\n");
     return false;
   }
void SSAIfConv::convertIf(SmallVectorImpl<MachineBasicBlock*> &RemovedBlocks) {
   if (FBB != Tail) {
     RemovedBlocks.push_back(FBB);
     FBB->eraseFromParent();
   }
 
   assert(Head->succ_empty() && "Additional head successors?");
   if (!ExtraPreds && Head->isLayoutSuccessor(Tail)) {
     // Splice Tail onto the end of Head.
-    DEBUG(dbgs() << "Joining tail BB#" << Tail->getNumber()
-                 << " into head BB#" << Head->getNumber() << '\n');
+    DEBUG(dbgs() << "Joining tail %bb." << Tail->getNumber()
+                 << " into head %bb." << Head->getNumber() << '\n');
     Head->splice(Head->end(), Tail,
                      Tail->begin(), Tail->end());
     Head->transferSuccessorsAndUpdatePHIs(Tail);
     RemovedBlocks.push_back(Tail);
     Tail->eraseFromParent();
   } else {
     // We need a branch to Tail, let code placement work it out later.
     DEBUG(dbgs() << "Converting to unconditional branch.\n");

lib/CodeGen/EdgeBundles.cpp

 raw_ostream &WriteGraph<>(raw_ostream &O, const EdgeBundles &G,
                           bool ShortNames,
                           const Twine &Title) {
   const MachineFunction *MF = G.getMachineFunction();
 
   O << "digraph {\n";
   for (const auto &MBB : *MF) {
     unsigned BB = MBB.getNumber();
-    O << "\t\"BB#" << BB << "\" [ shape=box ]\n"
-      << '\t' << G.getBundle(BB, false) << " -> \"BB#" << BB << "\"\n"
-      << "\t\"BB#" << BB << "\" -> " << G.getBundle(BB, true) << '\n';
+    O << "\t\"%bb." << BB << "\" [ shape=box ]\n"
+      << '\t' << G.getBundle(BB, false) << " -> \"%bb." << BB << "\"\n"
+      << "\t\"%bb." << BB << "\" -> " << G.getBundle(BB, true) << '\n';
     for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(),
            SE = MBB.succ_end(); SI != SE; ++SI)
-      O << "\t\"BB#" << BB << "\" -> \"BB#" << (*SI)->getNumber()
+      O << "\t\"%bb." << BB << "\" -> \"%bb." << (*SI)->getNumber()
         << "\" [ color=lightgray ]\n";
   }
   O << "}\n";
   return O;
 }
 
 } // end namespace llvm
 
 /// view - Visualize the annotated bipartite CFG with Graphviz.
 void EdgeBundles::view() const {
   ViewGraph(*this, "EdgeBundles");
 }

lib/CodeGen/ExecutionDepsFix.cpp

if (MBB->pred_empty()) {
     for (const auto &LI : MBB->liveins()) {
       for (int rx : regIndices(LI.PhysReg)) {
         // Treat function live-ins as if they were defined just before the first
         // instruction.  Usually, function arguments are set up immediately
         // before the call.
         LiveRegs[rx].Def = -1;
       }
     }
-    DEBUG(dbgs() << "BB#" << MBB->getNumber() << ": entry\n");
+    DEBUG(dbgs() << "%bb." << MBB->getNumber() << ": entry\n");
     return;
   }
 
   // Try to coalesce live-out registers from predecessors.
   for (MachineBasicBlock::const_pred_iterator pi = MBB->pred_begin(),
        pe = MBB->pred_end(); pi != pe; ++pi) {
     auto fi = MBBInfos.find(*pi);
     assert(fi != MBBInfos.end() &&
for (unsigned rx = 0; rx != NumRegs; ++rx) {
       // Currently open, merge in predecessor.
       if (!pdv->isCollapsed())
         merge(LiveRegs[rx].Value, pdv);
       else
         force(rx, pdv->getFirstDomain());
     }
   }
   DEBUG(
-      dbgs() << "BB#" << MBB->getNumber()
+      dbgs() << "%bb." << MBB->getNumber()
              << (!isBlockDone(MBB) ? ": incomplete\n" : ": all preds known\n"));
 }
 
 void ExecutionDepsFix::leaveBasicBlock(MachineBasicBlock *MBB) {
   assert(LiveRegs && "Must enter basic block first.");
   LiveReg *OldOutRegs = MBBInfos[MBB].OutRegs;
   // Save register clearances at end of MBB - used by enterBasicBlock().
   MBBInfos[MBB].OutRegs = LiveRegs;

lib/CodeGen/IfConversion.cpp

while (!Tokens.empty()) {
       switch (Kind) {
       default: llvm_unreachable("Unexpected!");
       case ICSimple:
       case ICSimpleFalse: {
         bool isFalse = Kind == ICSimpleFalse;
         if ((isFalse && DisableSimpleF) || (!isFalse && DisableSimple)) break;
         DEBUG(dbgs() << "Ifcvt (Simple" << (Kind == ICSimpleFalse ?
                                             " false" : "")
-                     << "): BB#" << BBI.BB->getNumber() << " ("
+                     << "): %bb." << BBI.BB->getNumber() << " ("
                      << ((Kind == ICSimpleFalse)
                          ? BBI.FalseBB->getNumber()
                          : BBI.TrueBB->getNumber()) << ") ");
         RetVal = IfConvertSimple(BBI, Kind);
         DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n");
         if (RetVal) {
           if (isFalse) ++NumSimpleFalse;
           else         ++NumSimple;
while (!Tokens.empty()) {
         if (DisableTriangleR && !isFalse && isRev) break;
         if (DisableTriangleF && isFalse && !isRev) break;
         if (DisableTriangleFR && isFalse && isRev) break;
         DEBUG(dbgs() << "Ifcvt (Triangle");
         if (isFalse)
           DEBUG(dbgs() << " false");
         if (isRev)
           DEBUG(dbgs() << " rev");
-        DEBUG(dbgs() << "): BB#" << BBI.BB->getNumber() << " (T:"
+        DEBUG(dbgs() << "): %bb." << BBI.BB->getNumber() << " (T:"
                      << BBI.TrueBB->getNumber() << ",F:"
                      << BBI.FalseBB->getNumber() << ") ");
         RetVal = IfConvertTriangle(BBI, Kind);
         DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n");
         if (RetVal) {
           if (isFalse) {
             if (isRev) ++NumTriangleFRev;
             else       ++NumTriangleFalse;
           } else {
             if (isRev) ++NumTriangleRev;
             else       ++NumTriangle;
           }
         }
         break;
       }
       case ICDiamond:
         if (DisableDiamond) break;
-        DEBUG(dbgs() << "Ifcvt (Diamond): BB#" << BBI.BB->getNumber() << " (T:"
+        DEBUG(dbgs() << "Ifcvt (Diamond): %bb." << BBI.BB->getNumber() << " (T:"
                      << BBI.TrueBB->getNumber() << ",F:"
                      << BBI.FalseBB->getNumber() << ") ");
         RetVal = IfConvertDiamond(BBI, Kind, NumDups, NumDups2,
                                   Token->TClobbersPred,
                                   Token->FClobbersPred);
         DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n");
         if (RetVal) ++NumDiamonds;
         break;
       case ICForkedDiamond:
         if (DisableForkedDiamond) break;
-        DEBUG(dbgs() << "Ifcvt (Forked Diamond): BB#"
+        DEBUG(dbgs() << "Ifcvt (Forked Diamond): %bb."
                      << BBI.BB->getNumber() << " (T:"
                      << BBI.TrueBB->getNumber() << ",F:"
                      << BBI.FalseBB->getNumber() << ") ");
         RetVal = IfConvertForkedDiamond(BBI, Kind, NumDups, NumDups2,
                                       Token->TClobbersPred,
                                       Token->FClobbersPred);
         DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n");
         if (RetVal) ++NumForkedDiamonds;

lib/CodeGen/LiveDebugVariables.cpp

for (LocMap::const_iterator I = locInts.begin(); I.valid();) {
     // first instruction in the range).
     if (trimmedDefs.count(Start))
       Start = Start.getPrevIndex();
 
     DEBUG(dbgs() << "\t[" << Start << ';' << Stop << "):" << Loc.locNo());
     MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start)->getIterator();
     SlotIndex MBBEnd = LIS.getMBBEndIdx(&*MBB);
 
-    DEBUG(dbgs() << " BB#" << MBB->getNumber() << '-' << MBBEnd);
+    DEBUG(dbgs() << ' ' << printMBBReference(*MBB) << '-' << MBBEnd);
     insertDebugValue(&*MBB, Start, Stop, Loc, Spilled, LIS, TII, TRI);
     // This interval may span multiple basic blocks.
     // Insert a DBG_VALUE into each one.
     while (Stop > MBBEnd) {
       // Move to the next block.
       Start = MBBEnd;
       if (++MBB == MFEnd)
         break;
       MBBEnd = LIS.getMBBEndIdx(&*MBB);
-      DEBUG(dbgs() << " BB#" << MBB->getNumber() << '-' << MBBEnd);
+      DEBUG(dbgs() << ' ' << printMBBReference(*MBB) << '-' << MBBEnd);
       insertDebugValue(&*MBB, Start, Stop, Loc, Spilled, LIS, TII, TRI);
     }
     DEBUG(dbgs() << '\n');
     if (MBB == MFEnd)
       break;
 
     ++I;
   }

lib/CodeGen/LiveIntervalAnalysis.cpp

void LiveIntervals::computeLiveInRegUnits() {
   // Check all basic blocks for live-ins.
   for (const MachineBasicBlock &MBB : *MF) {
     // We only care about ABI blocks: Entry + landing pads.
     if ((&MBB != &MF->front() && !MBB.isEHPad()) || MBB.livein_empty())
       continue;
 
     // Create phi-defs at Begin for all live-in registers.
     SlotIndex Begin = Indexes->getMBBStartIdx(&MBB);
-    DEBUG(dbgs() << Begin << "\tBB#" << MBB.getNumber());
+    DEBUG(dbgs() << Begin << "\t%bb." << MBB.getNumber());
     for (const auto &LI : MBB.liveins()) {
       for (MCRegUnitIterator Units(LI.PhysReg, TRI); Units.isValid(); ++Units) {
         unsigned Unit = *Units;
         LiveRange *LR = RegUnitRanges[Unit];
         if (!LR) {
           // Use segment set to speed-up initial computation of the live range.
           LR = RegUnitRanges[Unit] = new LiveRange(UseSegmentSetForPhysRegs);
           NewRanges.push_back(Unit);

lib/CodeGen/LiveRangeCalc.cpp

if (MBB->pred_empty()) {
       report_fatal_error("Use not jointly dominated by defs.");
     }
 
     if (TargetRegisterInfo::isPhysicalRegister(PhysReg) &&
         !MBB->isLiveIn(PhysReg)) {
       MBB->getParent()->verify();
       const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
       errs() << "The register " << printReg(PhysReg, TRI)
-             << " needs to be live in to BB#" << MBB->getNumber()
+             << " needs to be live in to " << printMBBReference(*MBB)
              << ", but is missing from the live-in list.\n";
       report_fatal_error("Invalid global physical register");
     }
 #endif
     FoundUndef |= MBB->pred_empty();
 
     for (MachineBasicBlock *Pred : MBB->predecessors()) {
        // Is this a known live-out block?

lib/CodeGen/MIRPrinter.cpp

MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
             const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
         StackObjectOperandMapping(StackObjectOperandMapping) {}
 
   void print(const MachineBasicBlock &MBB);
 
   void print(const MachineInstr &MI);
-  void printMBBReference(const MachineBasicBlock &MBB);
   void printIRBlockReference(const BasicBlock &BB);
   void printIRValueReference(const Value &V);
   void printStackObjectReference(int FrameIndex);
   void printOffset(int64_t Offset);
   void printTargetFlags(const MachineOperand &Op);
   void print(const MachineInstr &MI, unsigned OpIdx,
              const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies,
              LLT TypeToPrint, bool IsDef = false);
void MIRPrinter::convert(ModuleSlotTracker &MST,
   YamlMFI.HasCalls = MFI.hasCalls();
   YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()
     ? MFI.getMaxCallFrameSize() : ~0u;
   YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
   YamlMFI.HasVAStart = MFI.hasVAStart();
   YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
   if (MFI.getSavePoint()) {
     raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
-    MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
-        .printMBBReference(*MFI.getSavePoint());
+    MFI.getSavePoint()->printAsOperand(StrOS, /*PrintType=*/false);
   }
   if (MFI.getRestorePoint()) {
     raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
-    MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
-        .printMBBReference(*MFI.getRestorePoint());
+    MFI.getRestorePoint()->printAsOperand(StrOS, /*PrintType=*/false);
   }
 }
 
 void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF,
                                      const MachineFunction &MF,
                                      ModuleSlotTracker &MST) {
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
void MIRPrinter::convert(ModuleSlotTracker &MST,
   YamlJTI.Kind = JTI.getEntryKind();
   unsigned ID = 0;
   for (const auto &Table : JTI.getJumpTables()) {
     std::string Str;
     yaml::MachineJumpTable::Entry Entry;
     Entry.ID = ID++;
     for (const auto *MBB : Table.MBBs) {
       raw_string_ostream StrOS(Str);
-      MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
-          .printMBBReference(*MBB);
+      MBB->printAsOperand(StrOS, /*PrintType=*/false);
       Entry.Blocks.push_back(StrOS.str());
       Str.clear();
     }
     YamlJTI.Entries.push_back(Entry);
   }
 }
 
 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
void MIPrinter::print(const MachineBasicBlock &MBB) {
   // without the successor list, it would guess the code would
   // fallthrough.
   if ((!MBB.succ_empty() && !SimplifyMIR) || !canPredictProbs ||
       !canPredictSuccessors(MBB)) {
     OS.indent(2) << "successors: ";
     for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
       if (I != MBB.succ_begin())
         OS << ", ";
-      printMBBReference(**I);
+      (*I)->printAsOperand(OS, /*PrintType=*/false);
       if (!SimplifyMIR || !canPredictProbs)
         OS << '('
            << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
            << ')';
     }
     OS << "\n";
     HasLineAttributes = true;
   }
for (const auto *Op : MI.memoperands()) {
       if (NeedComma)
         OS << ", ";
       print(Context, *TII, *Op);
       NeedComma = true;
     }
   }
 }
 
-void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
-  OS << "%bb." << MBB.getNumber();
-  if (const auto *BB = MBB.getBasicBlock()) {
-    if (BB->hasName())
-      OS << '.' << BB->getName();
-  }
-}
-
 static void printIRSlotNumber(raw_ostream &OS, int Slot) {
   if (Slot == -1)
     OS << "<badref>";
   else
     OS << Slot;
 }
 
 void MIPrinter::printIRBlockReference(const BasicBlock &BB) {
case MachineOperand::MO_Immediate:
     break;
   case MachineOperand::MO_CImmediate:
     Op.getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
     break;
   case MachineOperand::MO_FPImmediate:
     Op.getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
     break;
   case MachineOperand::MO_MachineBasicBlock:
-    printMBBReference(*Op.getMBB());
+    Op.getMBB()->printAsOperand(OS, /*PrintType=*/false);
     break;
   case MachineOperand::MO_FrameIndex:
     printStackObjectReference(Op.getIndex());
     break;
   case MachineOperand::MO_ConstantPoolIndex:
     OS << "%const." << Op.getIndex();
     printOffset(Op.getOffset());
     break;

lib/CodeGen/MachineBasicBlock.cpp

 }
 
 
 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineBasicBlock &MBB) {
   MBB.print(OS);
   return OS;
 }
 
+Printable llvm::printMBBReference(const MachineBasicBlock &MBB) {
+  return Printable([&MBB](raw_ostream &OS) { return MBB.printAsOperand(OS); });
+}
+
 /// When an MBB is added to an MF, we need to update the parent pointer of the
 /// MBB, the MBB numbering, and any instructions in the MBB to be on the right
 /// operand list for registers.
 ///
 /// MBBs start out as #-1. When a MBB is added to a MachineFunction, it
 /// gets the next available unique MBB number. If it is removed from a
 /// MachineFunction, it goes back to being #-1.
 void ilist_callback_traits<MachineBasicBlock>::addNodeToList(
if (!MF) {
     OS << "Can't print out MachineBasicBlock because parent MachineFunction"
        << " is null\n";
     return;
   }
 
   if (Indexes)
     OS << Indexes->getMBBStartIdx(this) << '\t';
 
-  OS << "BB#" << getNumber() << ": ";
+  OS << "%bb." << getNumber() << ": ";
 
   const char *Comma = "";
   if (const BasicBlock *LBB = getBasicBlock()) {
     OS << Comma << "derived from LLVM BB ";
     LBB->printAsOperand(OS, /*PrintType=*/false, MST);
     Comma = ", ";
   }
   if (isEHPad()) { OS << Comma << "EH LANDING PAD"; Comma = ", "; }
if (!livein_empty()) {
     }
     OS << '\n';
   }
   // Print the preds of this block according to the CFG.
   if (!pred_empty()) {
     if (Indexes) OS << '\t';
     OS << "    Predecessors according to CFG:";
     for (const_pred_iterator PI = pred_begin(), E = pred_end(); PI != E; ++PI)
-      OS << " BB#" << (*PI)->getNumber();
+      OS << " %bb." << (*PI)->getNumber();
     OS << '\n';
   }
 
   for (auto &I : instrs()) {
     if (Indexes) {
       if (Indexes->hasIndex(I))
         OS << Indexes->getInstructionIndex(I);
       OS << '\t';
     }
     OS << '\t';
     if (I.isInsideBundle())
       OS << "  * ";
     I.print(OS, MST);
   }
 
   // Print the successors of this block according to the CFG.
   if (!succ_empty()) {
     if (Indexes) OS << '\t';
     OS << "    Successors according to CFG:";
     for (const_succ_iterator SI = succ_begin(), E = succ_end(); SI != E; ++SI) {
-      OS << " BB#" << (*SI)->getNumber();
+      OS << " %bb." << (*SI)->getNumber();
       if (!Probs.empty())
         OS << '(' << *getProbabilityIterator(SI) << ')';
     }
     OS << '\n';
   }
   if (IrrLoopHeaderWeight) {
     if (Indexes) OS << '\t';
     OS << "    Irreducible loop header weight: "
        << IrrLoopHeaderWeight.getValue();
     OS << '\n';
   }
 }
 
 void MachineBasicBlock::printAsOperand(raw_ostream &OS,
                                        bool /*PrintType*/) const {
-  OS << "BB#" << getNumber();
+  OS << "%bb." << getNumber();
+  if (const auto *BB = getBasicBlock()) {
+    if (BB->hasName())
+      OS << '.' << BB->getName();
+  }
 }
 
 void MachineBasicBlock::removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) {
   LiveInVector::iterator I = find_if(
       LiveIns, [Reg](const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
   if (I == LiveIns.end())
     return;
 
if (!canSplitCriticalEdge(Succ))
     return nullptr;
 
   MachineFunction *MF = getParent();
   DebugLoc DL;  // FIXME: this is nowhere
 
   MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock();
   MF->insert(std::next(MachineFunction::iterator(this)), NMBB);
   DEBUG(dbgs() << "Splitting critical edge:"
-        " BB#" << getNumber()
-        << " -- BB#" << NMBB->getNumber()
-        << " -- BB#" << Succ->getNumber() << '\n');
+        " %bb." << getNumber()
+        << " -- %bb." << NMBB->getNumber()
+        << " -- %bb." << Succ->getNumber() << '\n');
 
   LiveIntervals *LIS = P.getAnalysisIfAvailable<LiveIntervals>();
   SlotIndexes *Indexes = P.getAnalysisIfAvailable<SlotIndexes>();
   if (LIS)
     LIS->insertMBBInMaps(NMBB);
   else if (Indexes)
     Indexes->insertMBBInMaps(NMBB);
 
if (TII->analyzeBranch(*const_cast<MachineBasicBlock *>(this), TBB, FBB, Cond,
                          /*AllowModify*/ false))
     return false;
 
   // Avoid bugpoint weirdness: A block may end with a conditional branch but
   // jumps to the same MBB is either case. We have duplicate CFG edges in that
   // case that we can't handle. Since this never happens in properly optimized
   // code, just skip those edges.
   if (TBB && TBB == FBB) {
-    DEBUG(dbgs() << "Won't split critical edge after degenerate BB#"
+    DEBUG(dbgs() << "Won't split critical edge after degenerate %bb."
                  << getNumber() << '\n');
     return false;
   }
   return true;
 }
 
 /// Prepare MI to be removed from its bundle. This fixes bundle flags on MI's
 /// neighboring instructions so the bundle won't be broken by removing MI.

lib/CodeGen/MachineBlockPlacement.cpp

 
 #ifndef NDEBUG
 /// \brief Helper to print the name of a MBB.
 ///
 /// Only used by debug logging.
 static std::string getBlockName(const MachineBasicBlock *BB) {
   std::string Result;
   raw_string_ostream OS(Result);
-  OS << "BB#" << BB->getNumber();
+  OS << "%bb." << BB->getNumber();
   OS << " ('" << BB->getName() << "')";
   OS.flush();
   return Result;
 }
 #endif
 
 /// \brief Mark a chain's successors as having one fewer preds.
 ///

lib/CodeGen/MachineBranchProbabilityInfo.cpp

MachineBranchProbabilityInfo::getHotSucc(MachineBasicBlock *MBB) const {
   return nullptr;
 }
 
 raw_ostream &MachineBranchProbabilityInfo::printEdgeProbability(
     raw_ostream &OS, const MachineBasicBlock *Src,
     const MachineBasicBlock *Dst) const {
 
   const BranchProbability Prob = getEdgeProbability(Src, Dst);
-  OS << "edge MBB#" << Src->getNumber() << " -> MBB#" << Dst->getNumber()
+  OS << "edge %bb." << Src->getNumber() << " -> %bb." << Dst->getNumber()
      << " probability is " << Prob
      << (isEdgeHot(Src, Dst) ? " [HOT edge]\n" : "\n");
 
   return OS;
 }

lib/CodeGen/MachineFunction.cpp

struct DOTGraphTraits<const MachineFunction*> : public DefaultDOTGraphTraits {
 
     std::string getNodeLabel(const MachineBasicBlock *Node,
                              const MachineFunction *Graph) {
       std::string OutStr;
       {
         raw_string_ostream OSS(OutStr);
 
         if (isSimple()) {
-          OSS << "BB#" << Node->getNumber();
+          OSS << "%bb." << Node->getNumber();
           if (const BasicBlock *BB = Node->getBasicBlock())
             OSS << ": " << BB->getName();
         } else
           Node->print(OSS);
       }
 
       if (OutStr[0] == '\n') OutStr.erase(OutStr.begin());
 

 void MachineJumpTableInfo::print(raw_ostream &OS) const {
   if (JumpTables.empty()) return;
 
   OS << "Jump Tables:\n";
 
   for (unsigned i = 0, e = JumpTables.size(); i != e; ++i) {
     OS << "  jt#" << i << ": ";
     for (unsigned j = 0, f = JumpTables[i].MBBs.size(); j != f; ++j)
-      OS << " BB#" << JumpTables[i].MBBs[j]->getNumber();
+      OS << " %bb." << JumpTables[i].MBBs[j]->getNumber();
   }
 
   OS << '\n';
 }
 
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 LLVM_DUMP_METHOD void MachineJumpTableInfo::dump() const { print(dbgs()); }
 #endif

lib/CodeGen/MachineLICM.cpp

 
 /// When an instruction is found to only use loop invariant operands that is
 /// safe to hoist, this instruction is called to do the dirty work.
 void MachineLICM::HoistPostRA(MachineInstr *MI, unsigned Def) {
   MachineBasicBlock *Preheader = getCurPreheader();
 
   // Now move the instructions to the predecessor, inserting it before any
   // terminator instructions.
-  DEBUG(dbgs() << "Hoisting to BB#" << Preheader->getNumber() << " from BB#"
+  DEBUG(dbgs() << "Hoisting to %bb." << Preheader->getNumber() << " from %bb."
                << MI->getParent()->getNumber() << ": " << *MI);
 
   // Splice the instruction to the preheader.
   MachineBasicBlock *MBB = MI->getParent();
   Preheader->splice(Preheader->getFirstTerminator(), MBB, MI);
 
   // Add register to livein list to all the BBs in the current loop since a
   // loop invariant must be kept live throughout the whole loop. This is
for (MachineBasicBlock *CurrentLoopExitingBlock : CurrentLoopExitingBlocks)
       }
   }
 
   SpeculationState = SpeculateFalse;
   return true;
 }
 
 void MachineLICM::EnterScope(MachineBasicBlock *MBB) {
-  DEBUG(dbgs() << "Entering BB#" << MBB->getNumber() << '\n');
+  DEBUG(dbgs() << "Entering %bb." << MBB->getNumber() << '\n');
 
   // Remember livein register pressure.
   BackTrace.push_back(RegPressure);
 }
 
 void MachineLICM::ExitScope(MachineBasicBlock *MBB) {
-  DEBUG(dbgs() << "Exiting BB#" << MBB->getNumber() << '\n');
+  DEBUG(dbgs() << "Exiting %bb." << MBB->getNumber() << '\n');
   BackTrace.pop_back();
 }
 
 /// Destroy scope for the MBB that corresponds to the given dominator tree node
 /// if its a leaf or all of its children are done. Walk up the dominator tree to
 /// destroy ancestors which are now done.
 void MachineLICM::ExitScopeIfDone(MachineDomTreeNode *Node,
                 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren,
if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) {
     if (!MI) return false;
   }
 
   // Now move the instructions to the predecessor, inserting it before any
   // terminator instructions.
   DEBUG({
       dbgs() << "Hoisting " << *MI;
       if (MI->getParent()->getBasicBlock())
-        dbgs() << " from BB#" << MI->getParent()->getNumber();
+        dbgs() << " from %bb." << MI->getParent()->getNumber();
       if (Preheader->getBasicBlock())
-        dbgs() << " to BB#" << Preheader->getNumber();
+        dbgs() << " to %bb." << Preheader->getNumber();
       dbgs() << "\n";
     });
 
   // If this is the first instruction being hoisted to the preheader,
   // initialize the CSE map with potential common expressions.
   if (FirstInLoop) {
     InitCSEMap(Preheader);
     FirstInLoop = false;

lib/CodeGen/MachineOperand.cpp

if (getFPImm()->getType()->isFloatTy()) {
                                  /*Upper=*/true);
       OS << format_hex_no_prefix(API.getLoBits(64).getZExtValue(), 16,
                                  /*Upper=*/true);
     } else {
       OS << getFPImm()->getValueAPF().convertToDouble();
     }
     break;
   case MachineOperand::MO_MachineBasicBlock:
-    OS << "<BB#" << getMBB()->getNumber() << ">";
+    OS << printMBBReference(*getMBB());
     break;
   case MachineOperand::MO_FrameIndex:
     OS << "<fi#" << getIndex() << '>';
     break;
   case MachineOperand::MO_ConstantPoolIndex:
     OS << "<cp#" << getIndex();
     if (getOffset())
       OS << "+" << getOffset();

lib/CodeGen/MachineScheduler.cpp

static cl::opt<unsigned> ViewMISchedCutoff("view-misched-cutoff", cl::Hidden,
   cl::desc("Hide nodes with more predecessor/successor than cutoff"));
 
 static cl::opt<unsigned> MISchedCutoff("misched-cutoff", cl::Hidden,
   cl::desc("Stop scheduling after N instructions"), cl::init(~0U));
 
 static cl::opt<std::string> SchedOnlyFunc("misched-only-func", cl::Hidden,
   cl::desc("Only schedule this function"));
 static cl::opt<unsigned> SchedOnlyBlock("misched-only-block", cl::Hidden,
-  cl::desc("Only schedule this MBB#"));
+  cl::desc("Only schedule this %bb."));
 #else
 static bool ViewMISchedDAGs = false;
 #endif // NDEBUG
 
 /// Avoid quadratic complexity in unusually large basic blocks by limiting the
 /// size of the ready lists.
 static cl::opt<unsigned> ReadyListLimit("misched-limit", cl::Hidden,
   cl::desc("Limit ready list to N instructions"), cl::init(256));
for (MBBRegionsVector::iterator R = MBBRegions.begin();
       if (I == RegionEnd || I == std::prev(RegionEnd)) {
         // Close the current region. Bundle the terminator if needed.
         // This invalidates 'RegionEnd' and 'I'.
         Scheduler.exitRegion();
         continue;
       }
       DEBUG(dbgs() << "********** MI Scheduling **********\n");
       DEBUG(dbgs() << MF->getName()
-            << ":BB#" << MBB->getNumber() << " " << MBB->getName()
+            << ":%bb." << MBB->getNumber() << " " << MBB->getName()
             << "\n  From: " << *I << "    To: ";
             if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
             else dbgs() << "End";
             dbgs() << " RegionInstrs: " << NumRegionInstrs << '\n');
       if (DumpCriticalPathLength) {
         errs() << MF->getName();
-        errs() << ":BB# " << MBB->getNumber();
+        errs() << ":%bb. " << MBB->getNumber();
         errs() << " " << MBB->getName() << " \n";
       }
 
       // Schedule a region: possibly reorder instructions.
       // This invalidates the original region iterators.
       Scheduler.schedule();
 
       // Close the current region.
while (true) {
     updateQueues(SU, IsTopNode);
   }
   assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.");
 
   placeDebugValues();
 
   DEBUG({
       unsigned BBNum = begin()->getParent()->getNumber();
-      dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n";
+      dbgs() << "*** Final schedule for %bb." << BBNum << " ***\n";
       dumpSchedule();
       dbgs() << '\n';
     });
 }
 
 /// Apply each ScheduleDAGMutation step in order.
 void ScheduleDAGMI::postprocessDAG() {
   for (auto &m : Mutations)
while (true) {
     updateQueues(SU, IsTopNode);
   }
   assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.");
 
   placeDebugValues();
 
   DEBUG({
       unsigned BBNum = begin()->getParent()->getNumber();
-      dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n";
+      dbgs() << "*** Final schedule for %bb." << BBNum << " ***\n";
       dumpSchedule();
       dbgs() << '\n';
     });
 }
 
 /// Build the DAG and setup three register pressure trackers.
 void ScheduleDAGMILive::buildDAGWithRegPressure() {
   if (!ShouldTrackPressure) {

lib/CodeGen/MachineSink.cpp

MachineSinking::AllUsesDominatedByBlock(unsigned Reg,
   // Ignore debug uses because debug info doesn't affect the code.
   if (MRI->use_nodbg_empty(Reg))
     return true;
 
   // BreakPHIEdge is true if all the uses are in the successor MBB being sunken
   // into and they are all PHI nodes. In this case, machine-sink must break
   // the critical edge first. e.g.
   //
-  // BB#1: derived from LLVM BB %bb4.preheader
-  //   Predecessors according to CFG: BB#0
+  // %bb.1: derived from LLVM BB %bb4.preheader
+  //   Predecessors according to CFG: %bb.0
   //     ...
   //     %reg16385<def> = DEC64_32r %reg16437, %EFLAGS<imp-def,dead>
   //     ...
-  //     JE_4 <BB#37>, %EFLAGS<imp-use>
-  //   Successors according to CFG: BB#37 BB#2
+  //     JE_4 %bb.37, %EFLAGS<imp-use>
+  //   Successors according to CFG: %bb.37 %bb.2
   //
-  // BB#2: derived from LLVM BB %bb.nph
-  //   Predecessors according to CFG: BB#0 BB#1
-  //     %reg16386<def> = PHI %reg16434, <BB#0>, %reg16385, <BB#1>
+  // %bb.2: derived from LLVM BB %bb.nph
+  //   Predecessors according to CFG: %bb.0 %bb.1
+  //     %reg16386<def> = PHI %reg16434, %bb.0, %reg16385, %bb.1
   BreakPHIEdge = true;
   for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
     MachineInstr *UseInst = MO.getParent();
     unsigned OpNo = &MO - &UseInst->getOperand(0);
     MachineBasicBlock *UseBlock = UseInst->getParent();
     if (!(UseBlock == MBB && UseInst->isPHI() &&
           UseInst->getOperand(OpNo+1).getMBB() == DefMBB)) {
       BreakPHIEdge = false;
while (true) {
     for (auto &MBB: MF)
       MadeChange |= ProcessBlock(MBB);
 
     // If we have anything we marked as toSplit, split it now.
     for (auto &Pair : ToSplit) {
       auto NewSucc = Pair.first->SplitCriticalEdge(Pair.second, *this);
       if (NewSucc != nullptr) {
         DEBUG(dbgs() << " *** Splitting critical edge:"
-              " BB#" << Pair.first->getNumber()
-              << " -- BB#" << NewSucc->getNumber()
-              << " -- BB#" << Pair.second->getNumber() << '\n');
+              " %bb." << Pair.first->getNumber()
+              << " -- %bb." << NewSucc->getNumber()
+              << " -- %bb." << Pair.second->getNumber() << '\n');
         MadeChange = true;
         ++NumSplit;
       } else
         DEBUG(dbgs() << " *** Not legal to break critical edge\n");
     }
     // If this iteration over the code changed anything, keep iterating.
     if (!MadeChange) break;
     EverMadeChange = true;
bool MachineSinking::PostponeSplitCriticalEdge(MachineInstr &MI,
   // Check for backedges of more "complex" loops.
   if (LI->getLoopFor(FromBB) == LI->getLoopFor(ToBB) &&
       LI->isLoopHeader(ToBB))
     return false;
 
   // It's not always legal to break critical edges and sink the computation
   // to the edge.
   //
-  // BB#1:
+  // %bb.1:
   // v1024
-  // Beq BB#3
+  // Beq %bb.3
   // <fallthrough>
-  // BB#2:
+  // %bb.2:
   // ... no uses of v1024
   // <fallthrough>
-  // BB#3:
+  // %bb.3:
   // ...
   //       = v1024
   //
-  // If BB#1 -> BB#3 edge is broken and computation of v1024 is inserted:
+  // If %bb.1 -> %bb.3 edge is broken and computation of v1024 is inserted:
   //
-  // BB#1:
+  // %bb.1:
   // ...
-  // Bne BB#2
-  // BB#4:
+  // Bne %bb.2
+  // %bb.4:
   // v1024 =
-  // B BB#3
-  // BB#2:
+  // B %bb.3
+  // %bb.2:
   // ... no uses of v1024
   // <fallthrough>
-  // BB#3:
+  // %bb.3:
   // ...
   //       = v1024
   //
-  // This is incorrect since v1024 is not computed along the BB#1->BB#2->BB#3
+  // This is incorrect since v1024 is not computed along the %bb.1->%bb.2->%bb.3
   // flow. We need to ensure the new basic block where the computation is
   // sunk to dominates all the uses.
   // It's only legal to break critical edge and sink the computation to the
   // new block if all the predecessors of "To", except for "From", are
   // not dominated by "From". Given SSA property, this means these
   // predecessors are dominated by "To".
   //
   // There is no need to do this check if all the uses are PHI nodes. PHI

lib/CodeGen/MachineTraceMetrics.cpp

MachineTraceMetrics::getEnsemble(MachineTraceMetrics::Strategy strategy) {
   // Allocate new Ensemble on demand.
   switch (strategy) {
   case TS_MinInstrCount: return (E = new MinInstrCountEnsemble(this));
   default: llvm_unreachable("Invalid trace strategy enum");
   }
 }
 
 void MachineTraceMetrics::invalidate(const MachineBasicBlock *MBB) {
-  DEBUG(dbgs() << "Invalidate traces through BB#" << MBB->getNumber() << '\n');
+  DEBUG(dbgs() << "Invalidate traces through %bb." << MBB->getNumber() << '\n');
   BlockInfo[MBB->getNumber()].invalidate();
   for (unsigned i = 0; i != TS_NumStrategies; ++i)
     if (Ensembles[i])
       Ensembles[i]->invalidate(MBB);
 }
 
 void MachineTraceMetrics::verifyAnalysis() const {
   if (!MF)
bool insertEdge(Optional<const MachineBasicBlock *> From,
     return LB.Visited.insert(To).second;
   }
 };
 
 } // end namespace llvm
 
 /// Compute the trace through MBB.
 void MachineTraceMetrics::Ensemble::computeTrace(const MachineBasicBlock *MBB) {
-  DEBUG(dbgs() << "Computing " << getName() << " trace through BB#"
+  DEBUG(dbgs() << "Computing " << getName() << " trace through %bb."
                << MBB->getNumber() << '\n');
   // Set up loop bounds for the backwards post-order traversal.
   LoopBounds Bounds(BlockInfo, MTM.Loops);
 
   // Run an upwards post-order search for the trace start.
   Bounds.Downward = false;
   Bounds.Visited.clear();
   for (auto I : inverse_post_order_ext(MBB, Bounds)) {
-    DEBUG(dbgs() << "  pred for BB#" << I->getNumber() << ": ");
+    DEBUG(dbgs() << "  pred for %bb." << I->getNumber() << ": ");
     TraceBlockInfo &TBI = BlockInfo[I->getNumber()];
     // All the predecessors have been visited, pick the preferred one.
     TBI.Pred = pickTracePred(I);
     DEBUG({
       if (TBI.Pred)
-        dbgs() << "BB#" << TBI.Pred->getNumber() << '\n';
+        dbgs() << "%bb." << TBI.Pred->getNumber() << '\n';
       else
         dbgs() << "null\n";
     });
     // The trace leading to I is now known, compute the depth resources.
     computeDepthResources(I);
   }
 
   // Run a downwards post-order search for the trace end.
   Bounds.Downward = true;
   Bounds.Visited.clear();
   for (auto I : post_order_ext(MBB, Bounds)) {
-    DEBUG(dbgs() << "  succ for BB#" << I->getNumber() << ": ");
+    DEBUG(dbgs() << "  succ for %bb." << I->getNumber() << ": ");
     TraceBlockInfo &TBI = BlockInfo[I->getNumber()];
     // All the successors have been visited, pick the preferred one.
     TBI.Succ = pickTraceSucc(I);
     DEBUG({
       if (TBI.Succ)
-        dbgs() << "BB#" << TBI.Succ->getNumber() << '\n';
+        dbgs() << "%bb." << TBI.Succ->getNumber() << '\n';
       else
         dbgs() << "null\n";
     });
     // The trace leaving I is now known, compute the height resources.
     computeHeightResources(I);
   }
 }
 
 /// Invalidate traces through BadMBB.
 void
 MachineTraceMetrics::Ensemble::invalidate(const MachineBasicBlock *BadMBB) {
   SmallVector<const MachineBasicBlock*, 16> WorkList;
   TraceBlockInfo &BadTBI = BlockInfo[BadMBB->getNumber()];
 
   // Invalidate height resources of blocks above MBB.
   if (BadTBI.hasValidHeight()) {
     BadTBI.invalidateHeight();
     WorkList.push_back(BadMBB);
     do {
       const MachineBasicBlock *MBB = WorkList.pop_back_val();
-      DEBUG(dbgs() << "Invalidate BB#" << MBB->getNumber() << ' ' << getName()
+      DEBUG(dbgs() << "Invalidate %bb." << MBB->getNumber() << ' ' << getName()
             << " height.\n");
       // Find any MBB predecessors that have MBB as their preferred successor.
       // They are the only ones that need to be invalidated.
       for (const MachineBasicBlock *Pred : MBB->predecessors()) {
         TraceBlockInfo &TBI = BlockInfo[Pred->getNumber()];
         if (!TBI.hasValidHeight())
           continue;
         if (TBI.Succ == MBB) {
           TBI.invalidateHeight();
           WorkList.push_back(Pred);
           continue;
         }
         // Verify that TBI.Succ is actually a *I successor.
         assert((!TBI.Succ || Pred->isSuccessor(TBI.Succ)) && "CFG changed");
       }
     } while (!WorkList.empty());
   }
 
   // Invalidate depth resources of blocks below MBB.
   if (BadTBI.hasValidDepth()) {
     BadTBI.invalidateDepth();
     WorkList.push_back(BadMBB);
     do {
       const MachineBasicBlock *MBB = WorkList.pop_back_val();
-      DEBUG(dbgs() << "Invalidate BB#" << MBB->getNumber() << ' ' << getName()
+      DEBUG(dbgs() << "Invalidate %bb." << MBB->getNumber() << ' ' << getName()
             << " depth.\n");
       // Find any MBB successors that have MBB as their preferred predecessor.
       // They are the only ones that need to be invalidated.
       for (const MachineBasicBlock *Succ : MBB->successors()) {
         TraceBlockInfo &TBI = BlockInfo[Succ->getNumber()];
         if (!TBI.hasValidDepth())
           continue;
         if (TBI.Pred == MBB) {
computeInstrDepths(const MachineBasicBlock *MBB) {
   // the trace. This is quite rare in SSA form, typically created by CSE
   // hoisting a compare.
   SparseSet<LiveRegUnit> RegUnits;
   RegUnits.setUniverse(MTM.TRI->getNumRegUnits());
 
   // Go through trace blocks in top-down order, stopping after the center block.
   while (!Stack.empty()) {
     MBB = Stack.pop_back_val();
-    DEBUG(dbgs() << "\nDepths for BB#" << MBB->getNumber() << ":\n");
+    DEBUG(dbgs() << "\nDepths for %bb." << MBB->getNumber() << ":\n");
     TraceBlockInfo &TBI = BlockInfo[MBB->getNumber()];
     TBI.HasValidInstrDepths = true;
     TBI.CriticalPath = 0;
 
     // Print out resource depths here as well.
     DEBUG({
       dbgs() << format("%7u Instructions\n", TBI.InstrDepth);
       ArrayRef<unsigned> PRDepths = getProcResourceDepths(MBB->getNumber());
for (LiveInReg &LI : TBI.LiveIns) {
       }
     }
   }
 
   // Go through the trace blocks in bottom-up order.
   SmallVector<DataDep, 8> Deps;
   for (;!Stack.empty(); Stack.pop_back()) {
     MBB = Stack.back();
-    DEBUG(dbgs() << "Heights for BB#" << MBB->getNumber() << ":\n");
+    DEBUG(dbgs() << "Heights for %bb." << MBB->getNumber() << ":\n");
     TraceBlockInfo &TBI = BlockInfo[MBB->getNumber()];
     TBI.HasValidInstrHeights = true;
     TBI.CriticalPath = 0;
 
     DEBUG({
       dbgs() << format("%7u Instructions\n", TBI.InstrHeight);
       ArrayRef<unsigned> PRHeights = getProcResourceHeights(MBB->getNumber());
       for (unsigned K = 0; K != PRHeights.size(); ++K)
for (MachineBasicBlock::const_iterator BI = MBB->end(), BB = MBB->begin();
       }
       // Update critical path length.
       TBI.CriticalPath = std::max(TBI.CriticalPath, Cycle + MICycles.Depth);
       DEBUG(dbgs() << TBI.CriticalPath << '\t' << Cycle << '\t' << MI);
     }
 
     // Update virtual live-in heights. They were added by addLiveIns() with a 0
     // height because the final height isn't known until now.
-    DEBUG(dbgs() << "BB#" << MBB->getNumber() <<  " Live-ins:");
+    DEBUG(dbgs() << "%bb." << MBB->getNumber() <<  " Live-ins:");
     for (LiveInReg &LIR : TBI.LiveIns) {
       const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg);
       LIR.Height = Heights.lookup(DefMI);
       DEBUG(dbgs() << ' ' << printReg(LIR.Reg) << '@' << LIR.Height);
     }
 
     // Transfer the live regunits to the live-in list.
     for (SparseSet<LiveRegUnit>::const_iterator
bool MachineTraceMetrics::Trace::isDepInTrace(const MachineInstr &DefMI,
   const TraceBlockInfo &TBI = TE.BlockInfo[UseMI.getParent()->getNumber()];
 
   return DepTBI.isUsefulDominator(TBI);
 }
 
 void MachineTraceMetrics::Ensemble::print(raw_ostream &OS) const {
   OS << getName() << " ensemble:\n";
   for (unsigned i = 0, e = BlockInfo.size(); i != e; ++i) {
-    OS << "  BB#" << i << '\t';
+    OS << "  %bb." << i << '\t';
     BlockInfo[i].print(OS);
     OS << '\n';
   }
 }
 
 void MachineTraceMetrics::TraceBlockInfo::print(raw_ostream &OS) const {
   if (hasValidDepth()) {
     OS << "depth=" << InstrDepth;
     if (Pred)
-      OS << " pred=BB#" << Pred->getNumber();
+      OS << " pred=%bb." << Pred->getNumber();
     else
       OS << " pred=null";
-    OS << " head=BB#" << Head;
+    OS << " head=%bb." << Head;
     if (HasValidInstrDepths)
       OS << " +instrs";
   } else
     OS << "depth invalid";
   OS << ", ";
   if (hasValidHeight()) {
     OS << "height=" << InstrHeight;
     if (Succ)
-      OS << " succ=BB#" << Succ->getNumber();
+      OS << " succ=%bb." << Succ->getNumber();
     else
       OS << " succ=null";
-    OS << " tail=BB#" << Tail;
+    OS << " tail=%bb." << Tail;
     if (HasValidInstrHeights)
       OS << " +instrs";
   } else
     OS << "height invalid";
   if (HasValidInstrDepths && HasValidInstrHeights)
     OS << ", crit=" << CriticalPath;
 }
 
 void MachineTraceMetrics::Trace::print(raw_ostream &OS) const {
   unsigned MBBNum = &TBI - &TE.BlockInfo[0];
 
-  OS << TE.getName() << " trace BB#" << TBI.Head << " --> BB#" << MBBNum
-     << " --> BB#" << TBI.Tail << ':';
+  OS << TE.getName() << " trace %bb." << TBI.Head << " --> %bb." << MBBNum
+     << " --> %bb." << TBI.Tail << ':';
   if (TBI.hasValidHeight() && TBI.hasValidDepth())
     OS << ' ' << getInstrCount() << " instrs.";
   if (TBI.HasValidInstrDepths && TBI.HasValidInstrHeights)
     OS << ' ' << TBI.CriticalPath << " cycles.";
 
   const MachineTraceMetrics::TraceBlockInfo *Block = &TBI;
-  OS << "\nBB#" << MBBNum;
+  OS << "\n%bb." << MBBNum;
   while (Block->hasValidDepth() && Block->Pred) {
     unsigned Num = Block->Pred->getNumber();
-    OS << " <- BB#" << Num;
+    OS << " <- %bb." << Num;
     Block = &TE.BlockInfo[Num];
   }
 
   Block = &TBI;
   OS << "\n    ";
   while (Block->hasValidHeight() && Block->Succ) {
     unsigned Num = Block->Succ->getNumber();
-    OS << " -> BB#" << Num;
+    OS << " -> %bb." << Num;
     Block = &TE.BlockInfo[Num];
   }
   OS << '\n';
 }

lib/CodeGen/MachineVerifier.cpp

void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
   }
   errs() << "*** Bad machine code: " << msg << " ***\n"
       << "- function:    " << MF->getName() << "\n";
 }
 
 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
   assert(MBB);
   report(msg, MBB->getParent());
-  errs() << "- basic block: BB#" << MBB->getNumber()
+  errs() << "- basic block: %bb." << MBB->getNumber()
       << ' ' << MBB->getName()
       << " (" << (const void*)MBB << ')';
   if (Indexes)
     errs() << " [" << Indexes->getMBBStartIdx(MBB)
         << ';' <<  Indexes->getMBBEndIdx(MBB) << ')';
   errs() << '\n';
 }
 
MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
   for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
        E = MBB->succ_end(); I != E; ++I) {
     if ((*I)->isEHPad())
       LandingPadSuccs.insert(*I);
     if (!FunctionBlocks.count(*I))
       report("MBB has successor that isn't part of the function.", MBB);
     if (!MBBInfoMap[*I].Preds.count(MBB)) {
       report("Inconsistent CFG", MBB);
-      errs() << "MBB is not in the predecessor list of the successor BB#"
+      errs() << "MBB is not in the predecessor list of the successor %bb."
           << (*I)->getNumber() << ".\n";
     }
   }
 
   // Check the predecessor list.
   for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
        E = MBB->pred_end(); I != E; ++I) {
     if (!FunctionBlocks.count(*I))
       report("MBB has predecessor that isn't part of the function.", MBB);
     if (!MBBInfoMap[*I].Succs.count(MBB)) {
       report("Inconsistent CFG", MBB);
-      errs() << "MBB is not in the successor list of the predecessor BB#"
+      errs() << "MBB is not in the successor list of the predecessor %bb."
           << (*I)->getNumber() << ".\n";
     }
   }
 
   const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
   const BasicBlock *BB = MBB->getBasicBlock();
   const Function *Fn = MF->getFunction();
   if (LandingPadSuccs.size() > 1 &&
for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2) {
                &BBI.getOperand(i), i);
     }
 
     // Did we see all predecessors?
     for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
            PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
       if (!seen.count(*PrI)) {
         report("Missing PHI operand", &BBI);
-        errs() << "BB#" << (*PrI)->getNumber()
+        errs() << "%bb." << (*PrI)->getNumber()
             << " is a predecessor according to the CFG.\n";
       }
     }
   }
 }
 
 void MachineVerifier::visitMachineFunctionAfter() {
   calcRegsPassed();
for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
       // All predecessors must have a live-out value. However for a phi
       // instruction with subregister intervals
       // only one of the subregisters (not necessarily the current one) needs to
       // be defined.
       if (!PVNI && (LaneMask.none() || !IsPHI) ) {
         report("Register not marked live out of predecessor", *PI);
         report_context(LR, Reg, LaneMask);
         report_context(*VNI);
-        errs() << " live into BB#" << MFI->getNumber()
+        errs() << " live into %bb." << MFI->getNumber()
                << '@' << LiveInts->getMBBStartIdx(&*MFI) << ", not live before "
                << PEnd << '\n';
         continue;
       }
 
       // Only PHI-defs can take different predecessor values.
       if (!IsPHI && PVNI != VNI) {
         report("Different value live out of predecessor", *PI);
         report_context(LR, Reg, LaneMask);
-        errs() << "Valno #" << PVNI->id << " live out of BB#"
+        errs() << "Valno #" << PVNI->id << " live out of %bb."
                << (*PI)->getNumber() << '@' << PEnd << "\nValno #" << VNI->id
-               << " live into BB#" << MFI->getNumber() << '@'
+               << " live into %bb." << MFI->getNumber() << '@'
                << LiveInts->getMBBStartIdx(&*MFI) << '\n';
       }
     }
     if (&*MFI == EndMBB)
       break;
     ++MFI;
   }
 }
for (df_ext_iterator<const MachineFunction *,
     // Make sure the exit state of any predecessor is consistent with the entry
     // state.
     for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
          E = MBB->pred_end(); I != E; ++I) {
       if (Reachable.count(*I) &&
           (SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue ||
            SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
         report("The exit stack state of a predecessor is inconsistent.", MBB);
-        errs() << "Predecessor BB#" << (*I)->getNumber() << " has exit state ("
+        errs() << "Predecessor %bb." << (*I)->getNumber() << " has exit state ("
             << SPState[(*I)->getNumber()].ExitValue << ", "
             << SPState[(*I)->getNumber()].ExitIsSetup
-            << "), while BB#" << MBB->getNumber() << " has entry state ("
+            << "), while %bb." << MBB->getNumber() << " has entry state ("
             << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
       }
     }
 
     // Make sure the entry state of any successor is consistent with the exit
     // state.
     for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
          E = MBB->succ_end(); I != E; ++I) {
       if (Reachable.count(*I) &&
           (SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue ||
            SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
         report("The entry stack state of a successor is inconsistent.", MBB);
-        errs() << "Successor BB#" << (*I)->getNumber() << " has entry state ("
+        errs() << "Successor %bb." << (*I)->getNumber() << " has entry state ("
             << SPState[(*I)->getNumber()].EntryValue << ", "
             << SPState[(*I)->getNumber()].EntryIsSetup
-            << "), while BB#" << MBB->getNumber() << " has exit state ("
+            << "), while %bb." << MBB->getNumber() << " has exit state ("
             << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
       }
     }
 
     // Make sure a basic block with return ends with zero stack adjustment.
     if (!MBB->empty() && MBB->back().isReturn()) {
       if (BBState.ExitIsSetup)
         report("A return block ends with a FrameSetup.", MBB);
       if (BBState.ExitValue)
         report("A return block ends with a nonzero stack adjustment.", MBB);
     }
   }
 }

lib/CodeGen/PHIElimination.cpp

for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
       // use. That means the copy we will insert in PreMBB won't be a kill, and
       // there is a risk it may not be coalesced away.
       //
       // If the copy would be a kill, there is no need to split the edge.
       bool ShouldSplit = isLiveOutPastPHIs(Reg, PreMBB);
       if (!ShouldSplit && !NoPhiElimLiveOutEarlyExit)
         continue;
       if (ShouldSplit) {
-        DEBUG(dbgs() << printReg(Reg) << " live-out before critical edge BB#"
-                     << PreMBB->getNumber() << " -> BB#" << MBB.getNumber()
+        DEBUG(dbgs() << printReg(Reg) << " live-out before critical edge %bb."
+                     << PreMBB->getNumber() << " -> %bb." << MBB.getNumber()
                      << ": " << *BBI);
       }
 
       // If Reg is not live-in to MBB, it means it must be live-in to some
       // other PreMBB successor, and we can avoid the interference by splitting
       // the edge.
       //
       // If Reg *is* live-in to MBB, the interference is inevitable and a copy

lib/CodeGen/PostRASchedulerList.cpp

bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
   for (auto &MBB : Fn) {
 #ifndef NDEBUG
     // If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
     if (DebugDiv > 0) {
       static int bbcnt = 0;
       if (bbcnt++ % DebugDiv != DebugMod)
         continue;
       dbgs() << "*** DEBUG scheduling " << Fn.getName()
-             << ":BB#" << MBB.getNumber() << " ***\n";
+             << ":%bb." << MBB.getNumber() << " ***\n";
     }
 #endif
 
     // Initialize register live-range state for scheduling in this block.
     Scheduler.startBlock(&MBB);
 
     // Schedule each sequence of instructions not interrupted by a label
     // or anything else that effectively needs to shut down scheduling.

lib/CodeGen/ProcessImplicitDefs.cpp

for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end();
     for (MachineBasicBlock::instr_iterator MBBI = MFI->instr_begin(),
          MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI)
       if (MBBI->isImplicitDef())
         WorkList.insert(&*MBBI);
 
     if (WorkList.empty())
       continue;
 
-    DEBUG(dbgs() << "BB#" << MFI->getNumber() << " has " << WorkList.size()
+    DEBUG(dbgs() << "%bb." << MFI->getNumber() << " has " << WorkList.size()
                  << " implicit defs.\n");
     Changed = true;
 
     // Drain the WorkList to recursively process any new implicit defs.
     do processImplicitDef(WorkList.pop_back_val());
     while (!WorkList.empty());
   }
   return Changed;
 }

lib/CodeGen/RegAllocGreedy.cpp

if (BI.LiveOut) {
         IntvOut = Cand.IntvIdx;
         Cand.Intf.moveToBlock(Number);
         IntfOut = Cand.Intf.last();
       }
     }
 
     // Create separate intervals for isolated blocks with multiple uses.
     if (!IntvIn && !IntvOut) {
-      DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " isolated.\n");
+      DEBUG(dbgs() << "%bb." << BI.MBB->getNumber() << " isolated.\n");
       if (SA->shouldSplitSingleBlock(BI, SingleInstrs))
         SE->splitSingleBlock(BI);
       continue;
     }
 
     if (IntvIn && IntvOut)
       SE->splitLiveThroughBlock(Number, IntvIn, IntfIn, IntvOut, IntfOut);
     else if (IntvIn)

lib/CodeGen/RegisterCoalescer.cpp

bool RegisterCoalescer::removePartialRedundancy(const CoalescerPair &CP,
   //
   // If CopyLeftBB is not nullptr, ensure CopyLeftBB has a single succ so
   // MBB is hotter than CopyLeftBB.
   if (CopyLeftBB && CopyLeftBB->succ_size() > 1)
     return false;
 
   // Now ok to move copy.
   if (CopyLeftBB) {
-    DEBUG(dbgs() << "\tremovePartialRedundancy: Move the copy to BB#"
+    DEBUG(dbgs() << "\tremovePartialRedundancy: Move the copy to %bb."
                  << CopyLeftBB->getNumber() << '\t' << CopyMI);
 
     // Insert new copy to CopyLeftBB.
     auto InsPos = CopyLeftBB->getFirstTerminator();
     MachineInstr *NewCopyMI = BuildMI(*CopyLeftBB, InsPos, CopyMI.getDebugLoc(),
                                       TII->get(TargetOpcode::COPY), IntB.reg)
                                   .addReg(IntA.reg);
     SlotIndex NewCopyIdx =
         LIS->InsertMachineInstrInMaps(*NewCopyMI).getRegSlot();
     IntB.createDeadDef(NewCopyIdx, LIS->getVNInfoAllocator());
     for (LiveInterval::SubRange &SR : IntB.subranges())
       SR.createDeadDef(NewCopyIdx, LIS->getVNInfoAllocator());
 
     // If the newly created Instruction has an address of an instruction that was
     // deleted before (object recycled by the allocator) it needs to be removed from
     // the deleted list.
     ErasedInstrs.erase(NewCopyMI);
   } else {
-    DEBUG(dbgs() << "\tremovePartialRedundancy: Remove the copy from BB#"
+    DEBUG(dbgs() << "\tremovePartialRedundancy: Remove the copy from %bb."
                  << MBB.getNumber() << '\t' << CopyMI);
   }
 
   // Remove CopyMI.
   // Note: This is fine to remove the copy before updating the live-ranges.
   // While updating the live-ranges, we only look at slot indices and
   // never go back to the instruction.
   // Mark instructions as deleted.
JoinVals::analyzeValue(unsigned ValNo, JoinVals &Other) {
   // IMPLICIT_DEF instructions behind, and there is nothing wrong with it
   // technically.
   //
   // When it happens, treat that IMPLICIT_DEF as a normal value, and don't try
   // to erase the IMPLICIT_DEF instruction.
   if (OtherV.ErasableImplicitDef && DefMI &&
       DefMI->getParent() != Indexes->getMBBFromIndex(V.OtherVNI->def)) {
     DEBUG(dbgs() << "IMPLICIT_DEF defined at " << V.OtherVNI->def
-                 << " extends into BB#" << DefMI->getParent()->getNumber()
+                 << " extends into %bb." << DefMI->getParent()->getNumber()
                  << ", keeping it.\n");
     OtherV.ErasableImplicitDef = false;
   }
 
   // Allow overlapping PHI values. Any real interference would show up in a
   // predecessor, the PHI itself can't introduce any conflicts.
   if (VNI->isPHIDef())
     return CR_Replace;

lib/CodeGen/ScheduleDAGInstrs.cpp

for (MachineOperand &MO : MI.operands()) {
     bool IsKill = LiveRegs.available(MRI, Reg);
     MO.setIsKill(IsKill);
     if (addToLiveRegs)
       LiveRegs.addReg(Reg);
   }
 }
 
 void ScheduleDAGInstrs::fixupKills(MachineBasicBlock &MBB) {
-  DEBUG(dbgs() << "Fixup kills for BB#" << MBB.getNumber() << '\n');
+  DEBUG(dbgs() << "Fixup kills for %bb." << MBB.getNumber() << '\n');
 
   LiveRegs.init(*TRI);
   LiveRegs.addLiveOuts(MBB);
 
   // Examine block from end to start...
   for (MachineInstr &MI : make_range(MBB.rbegin(), MBB.rend())) {
     if (MI.isDebugValue())
       continue;

lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

if (VT == MVT::Untyped) {
     RegClass = TLI->getRepRegClassFor(VT)->getID();
     Cost = TLI->getRepRegClassCostFor(VT);
   }
 }
 
 /// Schedule - Schedule the DAG using list scheduling.
 void ScheduleDAGRRList::Schedule() {
   DEBUG(dbgs()
-        << "********** List Scheduling BB#" << BB->getNumber()
+        << "********** List Scheduling %bb." << BB->getNumber()
         << " '" << BB->getName() << "' **********\n");
 
   CurCycle = 0;
   IssueCount = 0;
   MinAvailableCycle =
       DisableSchedCycles ? 0 : std::numeric_limits<unsigned>::max();
   NumLiveRegs = 0;
   // Allocate slots for each physical register, plus one for a special register

lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp

private:
   void scheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
   void listScheduleTopDown();
 };
 }  // end anonymous namespace
 
 /// Schedule - Schedule the DAG using list scheduling.
 void ScheduleDAGVLIW::Schedule() {
   DEBUG(dbgs()
-        << "********** List Scheduling BB#" << BB->getNumber()
+        << "********** List Scheduling %bb." << BB->getNumber()
         << " '" << BB->getName() << "' **********\n");
 
   // Build the scheduling graph.
   BuildSchedGraph(AA);
 
   AvailableQueue->initNodes(SUnits);
 
   listScheduleTopDown();

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
       ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
       ViewSUnitDAGs)
 #endif
   {
     BlockNumber = FuncInfo->MBB->getNumber();
     BlockName =
         (MF->getName() + ":" + FuncInfo->MBB->getBasicBlock()->getName()).str();
   }
-  DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
+  DEBUG(dbgs() << "Initial selection DAG: %bb." << BlockNumber
         << " '" << BlockName << "'\n"; CurDAG->dump());
 
   if (ViewDAGCombine1 && MatchFilterBB)
     CurDAG->viewGraph("dag-combine1 input for " + BlockName);
 
   // Run the DAG combiner in pre-legalize mode.
   {
     NamedRegionTimer T("combine1", "DAG Combining 1", GroupName,
                        GroupDescription, TimePassesIsEnabled);
     CurDAG->Combine(BeforeLegalizeTypes, AA, OptLevel);
   }
 
-  DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
+  DEBUG(dbgs() << "Optimized lowered selection DAG: %bb." << BlockNumber
         << " '" << BlockName << "'\n"; CurDAG->dump());
 
   // Second step, hack on the DAG until it only uses operations and types that
   // the target supports.
   if (ViewLegalizeTypesDAGs && MatchFilterBB)
     CurDAG->viewGraph("legalize-types input for " + BlockName);
 
   bool Changed;
   {
     NamedRegionTimer T("legalize_types", "Type Legalization", GroupName,
                        GroupDescription, TimePassesIsEnabled);
     Changed = CurDAG->LegalizeTypes();
   }
 
-  DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
+  DEBUG(dbgs() << "Type-legalized selection DAG: %bb." << BlockNumber
         << " '" << BlockName << "'\n"; CurDAG->dump());
 
   // Only allow creation of legal node types.
   CurDAG->NewNodesMustHaveLegalTypes = true;
 
   if (Changed) {
     if (ViewDAGCombineLT && MatchFilterBB)
       CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
 
     // Run the DAG combiner in post-type-legalize mode.
     {
       NamedRegionTimer T("combine_lt", "DAG Combining after legalize types",
                          GroupName, GroupDescription, TimePassesIsEnabled);
       CurDAG->Combine(AfterLegalizeTypes, AA, OptLevel);
     }
 
-    DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
+    DEBUG(dbgs() << "Optimized type-legalized selection DAG: %bb." << BlockNumber
           << " '" << BlockName << "'\n"; CurDAG->dump());
   }
 
   {
     NamedRegionTimer T("legalize_vec", "Vector Legalization", GroupName,
                        GroupDescription, TimePassesIsEnabled);
     Changed = CurDAG->LegalizeVectors();
   }
 
   if (Changed) {
-    DEBUG(dbgs() << "Vector-legalized selection DAG: BB#" << BlockNumber
+    DEBUG(dbgs() << "Vector-legalized selection DAG: %bb." << BlockNumber
           << " '" << BlockName << "'\n"; CurDAG->dump());
 
     {
       NamedRegionTimer T("legalize_types2", "Type Legalization 2", GroupName,
                          GroupDescription, TimePassesIsEnabled);
       CurDAG->LegalizeTypes();
     }
 
-    DEBUG(dbgs() << "Vector/type-legalized selection DAG: BB#" << BlockNumber
+    DEBUG(dbgs() << "Vector/type-legalized selection DAG: %bb." << BlockNumber
           << " '" << BlockName << "'\n"; CurDAG->dump());
 
     if (ViewDAGCombineLT && MatchFilterBB)
       CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
 
     // Run the DAG combiner in post-type-legalize mode.
     {
       NamedRegionTimer T("combine_lv", "DAG Combining after legalize vectors",
                          GroupName, GroupDescription, TimePassesIsEnabled);
       CurDAG->Combine(AfterLegalizeVectorOps, AA, OptLevel);
     }
 
-    DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
+    DEBUG(dbgs() << "Optimized vector-legalized selection DAG: %bb."
           << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
   }
 
   if (ViewLegalizeDAGs && MatchFilterBB)
     CurDAG->viewGraph("legalize input for " + BlockName);
 
   {
     NamedRegionTimer T("legalize", "DAG Legalization", GroupName,
                        GroupDescription, TimePassesIsEnabled);
     CurDAG->Legalize();
   }
 
-  DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
+  DEBUG(dbgs() << "Legalized selection DAG: %bb." << BlockNumber
         << " '" << BlockName << "'\n"; CurDAG->dump());
 
   if (ViewDAGCombine2 && MatchFilterBB)
     CurDAG->viewGraph("dag-combine2 input for " + BlockName);
 
   // Run the DAG combiner in post-legalize mode.
   {
     NamedRegionTimer T("combine2", "DAG Combining 2", GroupName,
                        GroupDescription, TimePassesIsEnabled);
     CurDAG->Combine(AfterLegalizeDAG, AA, OptLevel);
   }
 
-  DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
+  DEBUG(dbgs() << "Optimized legalized selection DAG: %bb." << BlockNumber
         << " '" << BlockName << "'\n"; CurDAG->dump());
 
   if (OptLevel != CodeGenOpt::None)
     ComputeLiveOutVRegInfo();
 
   if (ViewISelDAGs && MatchFilterBB)
     CurDAG->viewGraph("isel input for " + BlockName);
 
   // Third, instruction select all of the operations to machine code, adding the
   // code to the MachineBasicBlock.
   {
     NamedRegionTimer T("isel", "Instruction Selection", GroupName,
                        GroupDescription, TimePassesIsEnabled);
     DoInstructionSelection();
   }
 
-  DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
+  DEBUG(dbgs() << "Selected selection DAG: %bb." << BlockNumber
         << " '" << BlockName << "'\n"; CurDAG->dump());
 
   if (ViewSchedDAGs && MatchFilterBB)
     CurDAG->viewGraph("scheduler input for " + BlockName);
 
   // Schedule machine code.
   ScheduleDAGSDNodes *Scheduler = CreateScheduler();
   {
void NodeDeleted(SDNode *N, SDNode *E) override {
     if (ISelPosition == SelectionDAG::allnodes_iterator(N))
       ++ISelPosition;
   }
 };
 
 } // end anonymous namespace
 
 void SelectionDAGISel::DoInstructionSelection() {
-  DEBUG(dbgs() << "===== Instruction selection begins: BB#"
+  DEBUG(dbgs() << "===== Instruction selection begins: %bb."
         << FuncInfo->MBB->getNumber()
         << " '" << FuncInfo->MBB->getName() << "'\n");
 
   PreprocessISelDAG();
 
   // Select target instructions for the DAG.
   {
     // Number all nodes with a topological order and set DAGSize.

lib/CodeGen/SlotIndexes.cpp

for (IndexList::const_iterator itr = indexList.begin();
     if (itr->getInstr()) {
       dbgs() << *itr->getInstr();
     } else {
       dbgs() << "\n";
     }
   }
 
   for (unsigned i = 0, e = MBBRanges.size(); i != e; ++i)
-    dbgs() << "BB#" << i << "\t[" << MBBRanges[i].first << ';'
+    dbgs() << "%bb." << i << "\t[" << MBBRanges[i].first << ';'
            << MBBRanges[i].second << ")\n";
 }
 #endif
 
 // Print a SlotIndex to a raw_ostream.
 void SlotIndex::print(raw_ostream &os) const {
   if (isValid())
     os << listEntry()->getIndex() << "Berd"[getSlot()];

lib/CodeGen/SplitKit.cpp

VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(),
                               std::next(MachineBasicBlock::iterator(MI)));
   return VNI->def;
 }
 
 SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
   assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
   SlotIndex End = LIS.getMBBEndIdx(&MBB);
   SlotIndex Last = End.getPrevSlot();
-  DEBUG(dbgs() << "    enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
+  DEBUG(dbgs() << "    enterIntvAtEnd %bb." << MBB.getNumber() << ", " << Last);
   VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last);
   if (!ParentVNI) {
     DEBUG(dbgs() << ": not live\n");
     return End;
   }
   DEBUG(dbgs() << ": valno " << ParentVNI->id);
   VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
                               SA.getLastSplitPointIter(&MBB));
SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
   assert(MI && "No instruction at index");
   VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
   return VNI->def;
 }
 
 SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
   assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
   SlotIndex Start = LIS.getMBBStartIdx(&MBB);
-  DEBUG(dbgs() << "    leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
+  DEBUG(dbgs() << "    leaveIntvAtTop %bb." << MBB.getNumber() << ", " << Start);
 
   VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
   if (!ParentVNI) {
     DEBUG(dbgs() << ": not live\n");
     return Start;
   }
 
   VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
SplitEditor::findShallowDominator(MachineBasicBlock *MBB,
   unsigned BestDepth = std::numeric_limits<unsigned>::max();
 
   while (true) {
     const MachineLoop *Loop = Loops.getLoopFor(MBB);
 
     // MBB isn't in a loop, it doesn't get any better.  All dominators have a
     // higher frequency by definition.
     if (!Loop) {
-      DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
+      DEBUG(dbgs() << "Def in %bb." << DefMBB->getNumber() << " dominates %bb."
                    << MBB->getNumber() << " at depth 0\n");
       return MBB;
     }
 
     // We'll never be able to exit the DefLoop.
     if (Loop == DefLoop) {
-      DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
+      DEBUG(dbgs() << "Def in %bb." << DefMBB->getNumber() << " dominates %bb."
                    << MBB->getNumber() << " in the same loop\n");
       return MBB;
     }
 
     // Least busy dominator seen so far.
     unsigned Depth = Loop->getLoopDepth();
     if (Depth < BestDepth) {
       BestMBB = MBB;
       BestDepth = Depth;
-      DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
+      DEBUG(dbgs() << "Def in %bb." << DefMBB->getNumber() << " dominates %bb."
                    << MBB->getNumber() << " at depth " << Depth << '\n');
     }
 
     // Leave loop by going to the immediate dominator of the loop header.
     // This is a bigger stride than simply walking up the dominator tree.
     MachineDomTreeNode *IDom = MDT[Loop->getHeader()]->getIDom();
 
     // Too far up the dominator tree?
if (!Dom.first) {
       else if (Near != Dom.first)
         // None dominate. Hoist to common dominator, need new def.
         Dom = DomPair(Near, SlotIndex());
       Costs[ParentVNI->id] += MBFI.getBlockFreq(ValMBB);
     }
 
     DEBUG(dbgs() << "Multi-mapped complement " << VNI->id << '@' << VNI->def
                  << " for parent " << ParentVNI->id << '@' << ParentVNI->def
-                 << " hoist to BB#" << Dom.first->getNumber() << ' '
+                 << " hoist to %bb." << Dom.first->getNumber() << ' '
                  << Dom.second << '\n');
   }
 
   // Insert the hoisted copies.
   for (unsigned i = 0, e = Parent->getNumValNums(); i != e; ++i) {
     DomPair &Dom = NearestDom[i];
     if (!Dom.first || Dom.second.isValid())
       continue;
do {
       MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start)->getIterator();
       SlotIndex BlockStart, BlockEnd;
       std::tie(BlockStart, BlockEnd) = LIS.getSlotIndexes()->getMBBRange(&*MBB);
 
       // The first block may be live-in, or it may have its own def.
       if (Start != BlockStart) {
         VNInfo *VNI = LI.extendInBlock(BlockStart, std::min(BlockEnd, End));
         assert(VNI && "Missing def for complex mapped value");
-        DEBUG(dbgs() << ':' << VNI->id << "*BB#" << MBB->getNumber());
+        DEBUG(dbgs() << ':' << VNI->id << "*%bb." << MBB->getNumber());
         // MBB has its own def. Is it also live-out?
         if (BlockEnd <= End)
           LRC.setLiveOutValue(&*MBB, VNI);
 
         // Skip to the next block for live-in.
         ++MBB;
         BlockStart = BlockEnd;
       }
 
       // Handle the live-in blocks covered by [Start;End).
       assert(Start <= BlockStart && "Expected live-in block");
       while (BlockStart < End) {
-        DEBUG(dbgs() << ">BB#" << MBB->getNumber());
+        DEBUG(dbgs() << ">%bb." << MBB->getNumber());
         BlockEnd = LIS.getMBBEndIdx(&*MBB);
         if (BlockStart == ParentVNI->def) {
           // This block has the def of a parent PHI, so it isn't live-in.
           assert(ParentVNI->isPHIDef() && "Non-phi defined at block start?");
           VNInfo *VNI = LI.extendInBlock(BlockStart, std::min(BlockEnd, End));
           assert(VNI && "Missing def for complex mapped parent PHI");
           if (End >= BlockEnd)
             LRC.setLiveOutValue(&*MBB, VNI); // Live-out as well.
for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
     SlotIndex Idx = LIS.getInstructionIndex(*MI);
     if (MO.isDef() || MO.isUndef())
       Idx = Idx.getRegSlot(MO.isEarlyClobber());
 
     // Rewrite to the mapped register at Idx.
     unsigned RegIdx = RegAssign.lookup(Idx);
     LiveInterval &LI = LIS.getInterval(Edit->get(RegIdx));
     MO.setReg(LI.reg);
-    DEBUG(dbgs() << "  rewr BB#" << MI->getParent()->getNumber() << '\t'
+    DEBUG(dbgs() << "  rewr %bb." << MI->getParent()->getNumber() << '\t'
                  << Idx << ':' << RegIdx << '\t' << *MI);
 
     // Extend liveness to Idx if the instruction reads reg.
     if (!ExtendRanges || MO.isUndef())
       continue;
 
     // Skip instructions that don't read Reg.
     if (MO.isDef()) {

 // are on the stack.
 
 void SplitEditor::splitLiveThroughBlock(unsigned MBBNum,
                                         unsigned IntvIn, SlotIndex LeaveBefore,
                                         unsigned IntvOut, SlotIndex EnterAfter){
   SlotIndex Start, Stop;
   std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(MBBNum);
 
-  DEBUG(dbgs() << "BB#" << MBBNum << " [" << Start << ';' << Stop
+  DEBUG(dbgs() << "%bb." << MBBNum << " [" << Start << ';' << Stop
                << ") intf " << LeaveBefore << '-' << EnterAfter
                << ", live-through " << IntvIn << " -> " << IntvOut);
 
   assert((IntvIn || IntvOut) && "Use splitSingleBlock for isolated blocks");
 
   assert((!LeaveBefore || LeaveBefore < Stop) && "Interference after block");
   assert((!IntvIn || !LeaveBefore || LeaveBefore > Start) && "Impossible intf");
   assert((!EnterAfter || EnterAfter >= Start) && "Interference before block");
void SplitEditor::splitLiveThroughBlock(unsigned MBBNum,
   assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
 }
 
 void SplitEditor::splitRegInBlock(const SplitAnalysis::BlockInfo &BI,
                                   unsigned IntvIn, SlotIndex LeaveBefore) {
   SlotIndex Start, Stop;
   std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
 
-  DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
+  DEBUG(dbgs() << "%bb." << BI.MBB->getNumber() << " [" << Start << ';' << Stop
                << "), uses " << BI.FirstInstr << '-' << BI.LastInstr
                << ", reg-in " << IntvIn << ", leave before " << LeaveBefore
                << (BI.LiveOut ? ", stack-out" : ", killed in block"));
 
   assert(IntvIn && "Must have register in");
   assert(BI.LiveIn && "Must be live-in");
   assert((!LeaveBefore || LeaveBefore > Start) && "Bad interference");
 
void SplitEditor::splitRegInBlock(const SplitAnalysis::BlockInfo &BI,
   assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
 }
 
 void SplitEditor::splitRegOutBlock(const SplitAnalysis::BlockInfo &BI,
                                    unsigned IntvOut, SlotIndex EnterAfter) {
   SlotIndex Start, Stop;
   std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
 
-  DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
+  DEBUG(dbgs() << "%bb." << BI.MBB->getNumber() << " [" << Start << ';' << Stop
                << "), uses " << BI.FirstInstr << '-' << BI.LastInstr
                << ", reg-out " << IntvOut << ", enter after " << EnterAfter
                << (BI.LiveIn ? ", stack-in" : ", defined in block"));
 
   SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
 
   assert(IntvOut && "Must have register out");
   assert(BI.LiveOut && "Must be live-out");

lib/CodeGen/StackColoring.cpp

for (MachineInstr &MI : *MBB) {
           int Slot = slots[0];
           if (BlockInfo.Begin.test(Slot)) {
             BlockInfo.Begin.reset(Slot);
           }
           BlockInfo.End.set(Slot);
         } else {
           for (auto Slot : slots) {
             DEBUG(dbgs() << "Found a use of slot #" << Slot);
-            DEBUG(dbgs() << " at BB#" << MBB->getNumber() << " index ");
+            DEBUG(dbgs() << " at %bb." << MBB->getNumber() << " index ");
             DEBUG(Indexes->getInstructionIndex(MI).print(dbgs()));
             const AllocaInst *Allocation = MFI->getObjectAllocation(Slot);
             if (Allocation) {
               DEBUG(dbgs() << " with allocation: "<< Allocation->getName());
             }
             DEBUG(dbgs() << "\n");
             if (BlockInfo.End.test(Slot)) {
               BlockInfo.End.reset(Slot);

lib/CodeGen/TailDuplicator.cpp

while (MI != MBB->end()) {
         for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) {
           MachineBasicBlock *PHIBB = MI->getOperand(i + 1).getMBB();
           if (PHIBB == PredBB) {
             Found = true;
             break;
           }
         }
         if (!Found) {
-          dbgs() << "Malformed PHI in BB#" << MBB->getNumber() << ": " << *MI;
-          dbgs() << "  missing input from predecessor BB#"
+          dbgs() << "Malformed PHI in %bb." << MBB->getNumber() << ": " << *MI;
+          dbgs() << "  missing input from predecessor %bb."
                  << PredBB->getNumber() << '\n';
           llvm_unreachable(nullptr);
         }
       }
 
       for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) {
         MachineBasicBlock *PHIBB = MI->getOperand(i + 1).getMBB();
         if (CheckExtra && !Preds.count(PHIBB)) {
-          dbgs() << "Warning: malformed PHI in BB#" << MBB->getNumber() << ": "
+          dbgs() << "Warning: malformed PHI in %bb." << MBB->getNumber() << ": "
                  << *MI;
-          dbgs() << "  extra input from predecessor BB#" << PHIBB->getNumber()
+          dbgs() << "  extra input from predecessor %bb." << PHIBB->getNumber()
                  << '\n';
           llvm_unreachable(nullptr);
         }
         if (PHIBB->getNumber() < 0) {
-          dbgs() << "Malformed PHI in BB#" << MBB->getNumber() << ": " << *MI;
-          dbgs() << "  non-existing BB#" << PHIBB->getNumber() << '\n';
+          dbgs() << "Malformed PHI in %bb." << MBB->getNumber() << ": " << *MI;
+          dbgs() << "  non-existing %bb." << PHIBB->getNumber() << '\n';
           llvm_unreachable(nullptr);
         }
       }
       ++MI;
     }
   }
 }
 

 /// \p TDBBs             A vector to keep track of all blocks tail-duplicated
 ///                      into.
 /// \p Copies            A vector of copy instructions inserted. Used later to
 ///                      walk all the inserted copies and remove redundant ones.
 bool TailDuplicator::tailDuplicate(bool IsSimple, MachineBasicBlock *TailBB,
                                    MachineBasicBlock *ForcedLayoutPred,
                                    SmallVectorImpl<MachineBasicBlock *> &TDBBs,
                                    SmallVectorImpl<MachineInstr *> &Copies) {
-  DEBUG(dbgs() << "\n*** Tail-duplicating BB#" << TailBB->getNumber() << '\n');
+  DEBUG(dbgs() << "\n*** Tail-duplicating %bb." << TailBB->getNumber() << '\n');
 
   DenseSet<unsigned> UsedByPhi;
   getRegsUsedByPHIs(*TailBB, &UsedByPhi);
 
   if (IsSimple)
     return duplicateSimpleBB(TailBB, TDBBs, UsedByPhi, Copies);
 
   // Iterate through all the unique predecessors and tail-duplicate this

lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp

MachineBasicBlock *AMDGPUMachineCFGStructurizer::createIfBlock(
   IfBB->addSuccessor(MergeBB);
   IfBB->addSuccessor(CodeBBStart);
 
   DEBUG(dbgs() << "Created If block: " << IfBB->getNumber() << "\n");
   // Ensure that the MergeBB is a successor of the CodeEndBB.
   if (!CodeBBEnd->isSuccessor(MergeBB))
     CodeBBEnd->addSuccessor(MergeBB);
 
-  DEBUG(dbgs() << "Moved MBB#" << CodeBBStart->getNumber() << " through MBB#"
-               << CodeBBEnd->getNumber() << "\n");
+  DEBUG(dbgs() << "Moved " << printMBBReference(*CodeBBStart) << " through "
+               << printMBBReference(*CodeBBEnd) << "\n");
 
   // If we have a single predecessor we can find a reasonable debug location
   MachineBasicBlock *SinglePred =
       CodeBBStart->pred_size() == 1 ? *(CodeBBStart->pred_begin()) : nullptr;
   const DebugLoc &DL = SinglePred
                     ? SinglePred->findDebugLoc(SinglePred->getFirstTerminator())
                     : DebugLoc();
 

lib/Target/SystemZ/SystemZMachineScheduler.cpp

if (I->isPosition() || I->isDebugValue())
       continue;
     HazardRec->emitInstruction(&*I);
   }
 }
 
 void SystemZPostRASchedStrategy::enterMBB(MachineBasicBlock *NextMBB) {
   assert ((SchedStates.find(NextMBB) == SchedStates.end()) &&
           "Entering MBB twice?");
-  DEBUG (dbgs() << "+++ Entering MBB#" << NextMBB->getNumber());
+  DEBUG(dbgs() << "+++ Entering " << printMBBReference(*NextMBB));
 
   MBB = NextMBB;
   /// Create a HazardRec for MBB, save it in SchedStates and set HazardRec to
   /// point to it.
   HazardRec = SchedStates[MBB] = new SystemZHazardRecognizer(TII, &SchedModel);
   DEBUG (const MachineLoop *Loop = MLI->getLoopFor(MBB);
          if(Loop && Loop->getHeader() == MBB)
            dbgs() << " (Loop header)";
          dbgs() << ":\n";);
 
   // Try to take over the state from a single predecessor, if it has been
   // scheduled. If this is not possible, we are done.
   MachineBasicBlock *SinglePredMBB =
     getSingleSchedPred(MBB, MLI->getLoopFor(MBB));
   if (SinglePredMBB == nullptr ||
       SchedStates.find(SinglePredMBB) == SchedStates.end())
     return;
 
-  DEBUG (dbgs() << "+++ Continued scheduling from MBB#"
-         << SinglePredMBB->getNumber() << "\n";);
+  DEBUG(dbgs() << "+++ Continued scheduling from "
+               << printMBBReference(*SinglePredMBB) << "\n";);
 
   HazardRec->copyState(SchedStates[SinglePredMBB]);
 
   // Emit incoming terminator(s). Be optimistic and assume that branch
   // prediction will generally do "the right thing".
   for (MachineBasicBlock::iterator I = SinglePredMBB->getFirstTerminator();
        I != SinglePredMBB->end(); I++) {
     DEBUG (dbgs() << "+++ Emitting incoming branch: "; I->dump(););
     bool TakenBranch = (I->isBranch() &&
       (TII->getBranchInfo(*I).Target->isReg() || // Relative branch
        TII->getBranchInfo(*I).Target->getMBB() == MBB));
     HazardRec->emitInstruction(&*I, TakenBranch);
     if (TakenBranch)
       break;
   }
 }
 
 void SystemZPostRASchedStrategy::leaveMBB() {
-  DEBUG (dbgs() << "+++ Leaving MBB#" << MBB->getNumber() << "\n";);
+  DEBUG(dbgs() << "+++ Leaving " << printMBBReference(*MBB) << "\n";);
 
   // Advance to first terminator. The successor block will handle terminators
   // dependent on CFG layout (T/NT branch etc).
   advanceTo(MBB->getFirstTerminator());
 }
 
 SystemZPostRASchedStrategy::
 SystemZPostRASchedStrategy(const MachineSchedContext *C)

lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp

SmallVector<MachineBasicBlock *, 4> SuccWorklist(RewriteSuccs.begin(),
                                                    RewriteSuccs.end());
   while (!SuccWorklist.empty()) {
     MachineBasicBlock *MBB = SuccWorklist.pop_back_val();
     auto Pair = Indices.insert(std::make_pair(MBB, 0));
     if (!Pair.second)
       continue;
 
     unsigned Index = MIB.getInstr()->getNumExplicitOperands() - 1;
-    DEBUG(dbgs() << "MBB#" << MBB->getNumber() << " has index " << Index
-                 << "\n");
+    DEBUG(dbgs() << printMBBReference(*MBB) << " has index " << Index << "\n");
 
     Pair.first->second = Index;
     for (auto Pred : MBB->predecessors())
       RewriteSuccs.insert(Pred);
 
     MIB.addMBB(MBB);
     Dispatch->addSuccessor(MBB);