AMDGPU: Implement computeKnownBitsForTargetNode for mbcnt

[rampitec]

LGTM with spacing fixed.

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

4077

Space around "-"

[arsenm]

r318100

[foad]

This caused https://github.com/llvm/llvm-project/issues/55598

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

if (Opc == AMDGPUISD::MUL_I24) {
       Negative = (LHSNegative && RHSPositive) || (LHSPositive && RHSNegative);
     }
     if (Negative)
       Known.One.setHighBits(32 - MaxValBits);
     else
       Known.Zero.setHighBits(32 - MaxValBits);
     break;
   }
+  case ISD::INTRINSIC_WO_CHAIN: {
+    unsigned IID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+    switch (IID) {
+    case Intrinsic::amdgcn_mbcnt_lo:
+    case Intrinsic::amdgcn_mbcnt_hi: {
+      // These return at most the wavefront size - 1.
+      unsigned Size = Op.getValueType().getSizeInBits();
+      Known.Zero.setHighBits(Size- Subtarget->getWavefrontSizeLog2());
+      break;
+    }
+    default:
+      break;
+    }
+  }
   }
 }
 
 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
     SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
     unsigned Depth) const {
   switch (Op.getOpcode()) {
   case AMDGPUISD::BFE_I32: {

lib/Target/AMDGPU/AMDGPUSubtarget.h

public:
   Generation getGeneration() const {
     return Gen;
   }
 
   unsigned getWavefrontSize() const {
     return WavefrontSize;
   }
 
+  unsigned getWavefrontSizeLog2() const {
+    return Log2_32(WavefrontSize);
+  }
+
   int getLocalMemorySize() const {
     return LocalMemorySize;
   }
 
   int getLDSBankCount() const {
     return LDSBankCount;
   }
 

test/CodeGen/AMDGPU/llvm.amdgcn.mbcnt.ll

 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
 
 ; GCN-LABEL: {{^}}mbcnt_intrinsics:
 ; GCN: v_mbcnt_lo_u32_b32{{(_e64)*}} [[LO:v[0-9]+]], -1, 0
 ; SI: v_mbcnt_hi_u32_b32_e32 {{v[0-9]+}}, -1, [[LO]]
 ; VI: v_mbcnt_hi_u32_b32 {{v[0-9]+}}, -1, [[LO]]
 define amdgpu_ps void @mbcnt_intrinsics(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <32 x i8> addrspace(2)* inreg %arg2, i32 inreg %arg3) {
 main_body:
   %lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
   %hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo) #0
   %tmp = bitcast i32 %hi to float
   call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp, float %tmp, float %tmp, float %tmp, i1 true, i1 true) #1
   ret void
 }
 
+; GCN-LABEL: {{^}}mbcnt_lo_known_bits:
+; GCN: v_mbcnt_lo_u32_b32
+; GCN-NOT: and
+define i32 @mbcnt_lo_known_bits(i32 %x, i32 %y) #0 {
+  %lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 %x, i32 %y)
+  %mask = and i32 %lo, 63
+  ret i32 %mask
+}
+
+; GCN-LABEL: {{^}}mbcnt_hi_known_bits:
+; GCN: v_mbcnt_hi_u32_b32
+; GCN-NOT: and
+define i32 @mbcnt_hi_known_bits(i32 %x, i32 %y) #0 {
+  %hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 %x, i32 %y)
+  %mask = and i32 %hi, 63
+  ret i32 %mask
+}
+
 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0
 declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0
 declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1
 
 attributes #0 = { nounwind readnone }
 attributes #1 = { nounwind }