[MIPS][MicroMIPS] Extending size reduction pass with LWP and SWP

[milena.vujosevic.janicic]

Summary

The patch extends size reduction pass for MicroMIPS.
It introduces reduction of two instructions into one instruction:
Two SW instructions are transformed into one SWP instrucition.
Two LW instructions are transformed into one LWP instrucition.

[milena.vujosevic.janicic]

Any comments?

[milena.vujosevic.janicic]

Any comments?

[milena.vujosevic.janicic]

Any comments?

[milena.vujosevic.janicic]

Ping

[milena.vujosevic.janicic]

I would very much appreciate to get some comments.

[sdardis]

Can you also provide some tests than ensure that lwp/swp is not formed when the first register is ra? You'll need to use some mir based testing (i.e. compile an ll file and use -stop-before= and the list test will use -start-after=)

lib/Target/Mips/MicroMipsSizeReduction.cpp

86

You should not be using void * pointers. Instead, provide a typedef for the structure you're passing and use that instead.

116–128

Provide a forward declaration and typedef for this structure above 'struct ReduceEntry', as void * should not be used.

189

The parameter flag should have a more descriptive name.

441–445

Swap these two blocks in order and you can the set MI2 to NextMII immediately.

639–644

Unfortunately this is not the case that this pass is among the last to run before machine code is emitted. This pass runs before the delay slot filler+long branch+hazard scheduling. There are other general later passes which do some analysis for stackmaps and debug information and funclet layout and the like.

A particular problem here is that as the lwp/swp instructions either write/read their operands the delay slot filler will not be able to or will incorrect analyse that for the purposes of filling delay slots.

The second problem is that lwp and swp are unpredictable when placed in delay slots and the delay slot filler doesn't know that.

There are number of issues to be resolved here: correcting the definition of lwp and swp so that their definition reflects their actual operation; marking this instructions in some way as being unsuitable for being placed in delay slots.

684

Unnecessary change.

[milena.vujosevic.janicic]

All the comments are taken into account.

[milena.vujosevic.janicic]

Any comments?

[milena.vujosevic.janicic]

Ping

[milena.vujosevic.janicic]

Any comments?

[sdardis]

lib/Target/Mips/MicroMipsSizeReduction.cpp

330

instruciton -> instruction

394

Rather than passing an explicit end iterator, determine the end from the instruction iterator MII, this reduces the number of arguments to be passed.

test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.ll

2

Change the -march=mipsel to -mtriple=mipsel-unknown-linux-gnu and use update_llc_checks.py to generate the check lines.

Can you add another version of this test that is .mir based but with LW_MM and SW_MM, and mixes of LW & LW_MM, similarly for the stores?

[milena.vujosevic.janicic]

All the comments are taken into account.

[milena.vujosevic.janicic]

Any comments?

[milena.vujosevic.janicic]

Ping

[milena.vujosevic.janicic]

I would very much appreciate to get some comments.

[milena.vujosevic.janicic]

Ping

[milena.vujosevic.janicic]

Any comments?

[sdardis]

Hi Milena, sorry for the delay in getting back to this, I', currently on holiday but I will get back to looking at this sometime next week.

[milena.vujosevic.janicic]

Ping

[milena.vujosevic.janicic]

Any comments?

[milena.vujosevic.janicic]

Ping...

[milena.vujosevic.janicic]

Rebased against trunk.

[milena.vujosevic.janicic]

Ping!

[sdardis]

This looks ok. One the patch that I have made this dependant on lands, you should be able to get rid of the undefs on the registers, as they'll have the correct descriptions.

[milena.vujosevic.janicic]

Addressed changes introduced by
[mips] Fix the definitions of lwp, swp

[sdardis]

lib/Target/Mips/MicroMipsSizeReduction.cpp

465

Invert the test here. If Reg1 != Reg2 just return false immediately.

471

if (!(ConsecutiveForward || ConsecutiveBackward))

return false;

and remove the Reduce variable altogether.

test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.mir

6–8 ↗

(On Diff #149119)

This can be removed.

15 ↗

(On Diff #149119)

The attribute numbers can be removed.

20–21 ↗

(On Diff #149119)

This can be removed.

test/CodeGen/Mips/micromips-sizereduction/micromips-no-lwp-swp.mir

6–8 ↗

(On Diff #149119)

This can be removed.

15 ↗

(On Diff #149119)

The attribute numbers can be removed.

20–21 ↗

(On Diff #149119)

This can be removed.

[milena.vujosevic.janicic]

Suggested changes are addressed.

[sdardis]

lib/Target/Mips/MicroMipsSizeReduction.cpp

335

Shouldn't the closing parenthesis here be on the next line? Like the check below?

[sdardis]

LGTM.

lib/Target/Mips/MicroMipsSizeReduction.cpp

 //=== MicroMipsSizeReduction.cpp - MicroMips size reduction pass --------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///\file
 /// This pass is used to reduce the size of instructions where applicable.
 ///
 /// TODO: Implement microMIPS64 support.
-/// TODO: Implement support for reducing into lwp/swp instruction.
 //===----------------------------------------------------------------------===//
 #include "Mips.h"
 #include "MipsInstrInfo.h"
 #include "MipsSubtarget.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/Support/Debug.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "micromips-reduce-size"
 
-STATISTIC(NumReduced, "Number of 32-bit instructions reduced to 16-bit ones");
+STATISTIC(NumReduced, "Number of instructions reduced (32-bit to 16-bit ones, "
+                      "or two instructions into one");
 
 namespace {
 
 /// Order of operands to transfer
 // TODO: Will be extended when additional optimizations are added
 enum OperandTransfer {
   OT_NA,          ///< Not applicable
   OT_OperandsAll, ///< Transfer all operands
   OT_Operands02,  ///< Transfer operands 0 and 2
   OT_Operand2,    ///< Transfer just operand 2
   OT_OperandsXOR, ///< Transfer operands for XOR16
+  OT_OperandsXwp, ///< Transfer operands for LWP/SWP
 };
 
 /// Reduction type
 // TODO: Will be extended when additional optimizations are added
 enum ReduceType {
-  RT_OneInstr ///< Reduce one instruction into a smaller instruction
+  RT_TwoInstr, ///< Reduce two instructions into one instruction
+  RT_OneInstr  ///< Reduce one instruction into a smaller instruction
 };
 
 // Information about immediate field restrictions
 struct ImmField {
   ImmField() : ImmFieldOperand(-1), Shift(0), LBound(0), HBound(0) {}
   ImmField(uint8_t Shift, int16_t LBound, int16_t HBound,
            int8_t ImmFieldOperand)
       : ImmFieldOperand(ImmFieldOperand), Shift(Shift), LBound(LBound),
struct OpCodes {
   unsigned WideOpc;   ///< Wide opcode
   unsigned NarrowOpc; ///< Narrow opcode
 };
 
 /// ReduceTable - A static table with information on mapping from wide
 /// opcodes to narrow
 struct ReduceEntry {
 
-  enum ReduceType eRType; ///< Reduction type
-  bool (*ReduceFunction)(
-      MachineInstr *MI,
-      const ReduceEntry &Entry); ///< Pointer to reduce function
-  struct OpCodes Ops;            ///< All relevant OpCodes
-  struct OpInfo OpInf;           ///< Characteristics of operands
-  struct ImmField Imm;           ///< Characteristics of immediate field
+  enum ReduceType eRType;                ///< Reduction type
+  bool (*ReduceFunction)(void *FunArgs); ///< Pointer to reduce function
+  struct OpCodes Ops;                    ///< All relevant OpCodes
+  struct OpInfo OpInf;                   ///< Characteristics of operands
+  struct ImmField Imm;                   ///< Characteristics of immediate field
 
   ReduceEntry(enum ReduceType RType, struct OpCodes Op,
-              bool (*F)(MachineInstr *MI, const ReduceEntry &Entry),
-              struct OpInfo OpInf, struct ImmField Imm)
+              bool (*F)(void *FunArgs), struct OpInfo OpInf,
+              struct ImmField Imm)
       : eRType(RType), ReduceFunction(F), Ops(Op), OpInf(OpInf), Imm(Imm) {}
 
   unsigned NarrowOpc() const { return Ops.NarrowOpc; }
   unsigned WideOpc() const { return Ops.WideOpc; }
   int16_t LBound() const { return Imm.LBound; }
   int16_t HBound() const { return Imm.HBound; }
   uint8_t Shift() const { return Imm.Shift; }
   int8_t ImmField() const { return Imm.ImmFieldOperand; }
   enum OperandTransfer TransferOperands() const {
     return OpInf.TransferOperands;
   }
   enum ReduceType RType() const { return eRType; }
 
   // operator used by std::equal_range
   bool operator<(const unsigned int r) const { return (WideOpc() < r); }
 
   // operator used by std::equal_range
   friend bool operator<(const unsigned int r, const struct ReduceEntry &re) {
     return (r < re.WideOpc());
   }
 };
 
+// Function arguments for ReduceFunction
+struct ReduceEntryFunArgs {
+  MachineInstr *MI;         // Instruction
+  const ReduceEntry &Entry; // Entry field
+  MachineBasicBlock::instr_iterator
+      &NextMII; // Iterator to next instruction in block
+  const MachineBasicBlock::instr_iterator &E; // End iterator
+
+  ReduceEntryFunArgs(MachineInstr *argMI, const ReduceEntry &argEntry,
+                     MachineBasicBlock::instr_iterator &argNextMII,
+                     const MachineBasicBlock::instr_iterator &argE)
+      : MI(argMI), Entry(argEntry), NextMII(argNextMII), E(argE) {}
+};
+
+typedef llvm::SmallVector<ReduceEntry, 32> ReduceEntryVector;
+
 class MicroMipsSizeReduce : public MachineFunctionPass {
 public:
   static char ID;
   MicroMipsSizeReduce();
 
   static const MipsInstrInfo *MipsII;
   const MipsSubtarget *Subtarget;
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   llvm::StringRef getPassName() const override {
     return "microMIPS instruction size reduction pass";
   }
 
 private:
   /// Reduces width of instructions in the specified basic block.
   bool ReduceMBB(MachineBasicBlock &MBB);
 
   /// Attempts to reduce MI, returns true on success.
-  bool ReduceMI(const MachineBasicBlock::instr_iterator &MII);
+  bool ReduceMI(const MachineBasicBlock::instr_iterator &MII,
+                MachineBasicBlock::instr_iterator &NextMII,
+                const MachineBasicBlock::instr_iterator &E);
 
   // Attempts to reduce LW/SW instruction into LWSP/SWSP,
   // returns true on success.
-  static bool ReduceXWtoXWSP(MachineInstr *MI, const ReduceEntry &Entry);
+  static bool ReduceXWtoXWSP(void *FunArgs);
+
+  // Attempts to reduce two LW/SW instructions into LWP/SWP instruction,
+  // returns true on success.
+  static bool ReduceXWtoXWP(void *FunArgs);
 
   // Attempts to reduce LBU/LHU instruction into LBU16/LHU16,
   // returns true on success.
-  static bool ReduceLXUtoLXU16(MachineInstr *MI, const ReduceEntry &Entry);
+  static bool ReduceLXUtoLXU16(void *FunArgs);
 
   // Attempts to reduce SB/SH instruction into SB16/SH16,
   // returns true on success.
-  static bool ReduceSXtoSX16(MachineInstr *MI, const ReduceEntry &Entry);
+  static bool ReduceSXtoSX16(void *FunArgs);
 
   // Attempts to reduce arithmetic instructions, returns true on success.
-  static bool ReduceArithmeticInstructions(MachineInstr *MI,
-                                           const ReduceEntry &Entry);
+  static bool ReduceArithmeticInstructions(void *FunArgs);
 
   // Attempts to reduce ADDIU into ADDIUSP instruction,
   // returns true on success.
-  static bool ReduceADDIUToADDIUSP(MachineInstr *MI, const ReduceEntry &Entry);
+  static bool ReduceADDIUToADDIUSP(void *FunArgs);
 
   // Attempts to reduce ADDIU into ADDIUR1SP instruction,
   // returns true on success.
-  static bool ReduceADDIUToADDIUR1SP(MachineInstr *MI,
-                                     const ReduceEntry &Entry);
+  static bool ReduceADDIUToADDIUR1SP(void *FunArgs);
 
   // Attempts to reduce XOR into XOR16 instruction,
   // returns true on success.
-  static bool ReduceXORtoXOR16(MachineInstr *MI, const ReduceEntry &Entry);
+  static bool ReduceXORtoXOR16(void *FunArgs);
 
   // Changes opcode of an instruction.
-  static bool ReplaceInstruction(MachineInstr *MI, const ReduceEntry &Entry);
+  static bool ReplaceInstruction(MachineInstr *MI, const ReduceEntry &Entry,
+                                 MachineInstr *MI2 = nullptr,
+                                 bool flag = false);
 
   // Table with transformation rules for each instruction.
-  static llvm::SmallVector<ReduceEntry, 16> ReduceTable;
+  static ReduceEntryVector ReduceTable;
 };
 
 char MicroMipsSizeReduce::ID = 0;
 const MipsInstrInfo *MicroMipsSizeReduce::MipsII;
 
 // This table must be sorted by WideOpc as a main criterion and
 // ReduceType as a sub-criterion (when wide opcodes are the same).
-llvm::SmallVector<ReduceEntry, 16> MicroMipsSizeReduce::ReduceTable = {
+ReduceEntryVector MicroMipsSizeReduce::ReduceTable = {
 
     // ReduceType, OpCodes, ReduceFunction,
     // OpInfo(TransferOperands),
     // ImmField(Shift, LBound, HBound, ImmFieldPosition)
     {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUR1SP_MM),
      ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},
     {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUSP_MM), ReduceADDIUToADDIUSP,
      OpInfo(OT_Operand2), ImmField(0, 0, 0, 2)},
ReduceEntryVector MicroMipsSizeReduce::ReduceTable = {
     {RT_OneInstr, OpCodes(Mips::LBu_MM, Mips::LBU16_MM), ReduceLXUtoLXU16,
      OpInfo(OT_OperandsAll), ImmField(0, -1, 15, 2)},
     {RT_OneInstr, OpCodes(Mips::LEA_ADDiu, Mips::ADDIUR1SP_MM),
      ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},
     {RT_OneInstr, OpCodes(Mips::LHu, Mips::LHU16_MM), ReduceLXUtoLXU16,
      OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},
     {RT_OneInstr, OpCodes(Mips::LHu_MM, Mips::LHU16_MM), ReduceLXUtoLXU16,
      OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},
+    {RT_TwoInstr, OpCodes(Mips::LW, Mips::LWP_MM), ReduceXWtoXWP,
+     OpInfo(OT_OperandsXwp), ImmField(0, -2048, 2048, 2)},
     {RT_OneInstr, OpCodes(Mips::LW, Mips::LWSP_MM), ReduceXWtoXWSP,
      OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
+    {RT_TwoInstr, OpCodes(Mips::LW_MM, Mips::LWP_MM), ReduceXWtoXWP,
+     OpInfo(OT_OperandsXwp), ImmField(0, -2048, 2048, 2)},
     {RT_OneInstr, OpCodes(Mips::LW_MM, Mips::LWSP_MM), ReduceXWtoXWSP,
      OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
     {RT_OneInstr, OpCodes(Mips::SB, Mips::SB16_MM), ReduceSXtoSX16,
      OpInfo(OT_OperandsAll), ImmField(0, 0, 16, 2)},
     {RT_OneInstr, OpCodes(Mips::SB_MM, Mips::SB16_MM), ReduceSXtoSX16,
      OpInfo(OT_OperandsAll), ImmField(0, 0, 16, 2)},
     {RT_OneInstr, OpCodes(Mips::SH, Mips::SH16_MM), ReduceSXtoSX16,
      OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},
     {RT_OneInstr, OpCodes(Mips::SH_MM, Mips::SH16_MM), ReduceSXtoSX16,
      OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},
     {RT_OneInstr, OpCodes(Mips::SUBu, Mips::SUBU16_MM),
      ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),
      ImmField(0, 0, 0, -1)},
     {RT_OneInstr, OpCodes(Mips::SUBu_MM, Mips::SUBU16_MM),
      ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),
      ImmField(0, 0, 0, -1)},
+    {RT_TwoInstr, OpCodes(Mips::SW, Mips::SWP_MM), ReduceXWtoXWP,
+     OpInfo(OT_OperandsXwp), ImmField(0, -2048, 2048, 2)},
     {RT_OneInstr, OpCodes(Mips::SW, Mips::SWSP_MM), ReduceXWtoXWSP,
      OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
+    {RT_TwoInstr, OpCodes(Mips::SW_MM, Mips::SWP_MM), ReduceXWtoXWP,
+     OpInfo(OT_OperandsXwp), ImmField(0, -2048, 2048, 2)},
     {RT_OneInstr, OpCodes(Mips::SW_MM, Mips::SWSP_MM), ReduceXWtoXWSP,
      OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
     {RT_OneInstr, OpCodes(Mips::XOR, Mips::XOR16_MM), ReduceXORtoXOR16,
      OpInfo(OT_OperandsXOR), ImmField(0, 0, 0, -1)},
     {RT_OneInstr, OpCodes(Mips::XOR_MM, Mips::XOR16_MM), ReduceXORtoXOR16,
      OpInfo(OT_OperandsXOR), ImmField(0, 0, 0, -1)}};
 } // namespace
 
if (!GetImm(MI, Entry.ImmField(), offset))
     return false;
 
   if (!InRange(offset, Entry.Shift(), Entry.LBound(), Entry.HBound()))
     return false;
 
   return true;
 }
 
+// Returns true if MI can be reduced to lwp/swp instruciton
+static bool CheckXWPInstr(MachineInstr *MI, bool ReduceToLwp,
+                          const ReduceEntry &Entry) {
+
+  if (ReduceToLwp &&
+      !(MI->getOpcode() == Mips::LW || MI->getOpcode() == Mips::LW_MM))
+    return false;
+
+  if (!ReduceToLwp &&
+      !(MI->getOpcode() == Mips::SW || MI->getOpcode() == Mips::SW_MM))
+    return false;
+
+  unsigned reg = MI->getOperand(0).getReg();
+  if (reg == Mips::RA)
+    return false;
+
+  if (!ImmInRange(MI, Entry))
+    return false;
+
+  if (ReduceToLwp && (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()))
+    return false;
+
+  return true;
+}
+
+// Returns true if the registers Reg1 and Reg2 are consecutive
+static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) {
+  static SmallVector<unsigned, 31> Registers = {
+      Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
+      Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6,
+      Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
+      Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP,
+      Mips::SP, Mips::FP, Mips::RA};
+
+  for (uint8_t i = 0; i < Registers.size() - 1; i++) {
+    if (Registers[i] == Reg1) {
+      if (Registers[i + 1] == Reg2)
+        return true;
+      else
+        return false;
+    }
+  }
+  return false;
+}
+
+// Returns true if registers and offsets are consecutive
+static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) {
+
+  int64_t Offset1, Offset2;
+  if (!GetImm(MI1, 2, Offset1))
+    return false;
+  if (!GetImm(MI2, 2, Offset2))
+    return false;
+
+  unsigned Reg1 = MI1->getOperand(0).getReg();
+  unsigned Reg2 = MI2->getOperand(0).getReg();
+
+  return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2)));
+}
+
 MicroMipsSizeReduce::MicroMipsSizeReduce() : MachineFunctionPass(ID) {}
 
-bool MicroMipsSizeReduce::ReduceMI(
-    const MachineBasicBlock::instr_iterator &MII) {
+bool MicroMipsSizeReduce::ReduceMI(const MachineBasicBlock::instr_iterator &MII,
+                                   MachineBasicBlock::instr_iterator &NextMII,
+                                   const MachineBasicBlock::instr_iterator &E) {
 
   MachineInstr *MI = &*MII;
   unsigned Opcode = MI->getOpcode();
 
   // Search the table.
-  llvm::SmallVector<ReduceEntry, 16>::const_iterator Start =
-      std::begin(ReduceTable);
-  llvm::SmallVector<ReduceEntry, 16>::const_iterator End =
-      std::end(ReduceTable);
+  ReduceEntryVector::const_iterator Start = std::begin(ReduceTable);
+  ReduceEntryVector::const_iterator End = std::end(ReduceTable);
 
-  std::pair<llvm::SmallVector<ReduceEntry, 16>::const_iterator,
-            llvm::SmallVector<ReduceEntry, 16>::const_iterator>
+  std::pair<ReduceEntryVector::const_iterator,
+            ReduceEntryVector::const_iterator>
       Range = std::equal_range(Start, End, Opcode);
 
   if (Range.first == Range.second)
     return false;
 
-  for (llvm::SmallVector<ReduceEntry, 16>::const_iterator Entry = Range.first;
-       Entry != Range.second; ++Entry)
-    if (((*Entry).ReduceFunction)(&(*MII), *Entry))
+  for (ReduceEntryVector::const_iterator Entry = Range.first;
+       Entry != Range.second; ++Entry) {
+    struct ReduceEntryFunArgs FunArgs(&(*MII), *Entry, NextMII, E);
+    if (((*Entry).ReduceFunction)(&FunArgs))
       return true;
-
+  }
   return false;
 }
 
-bool MicroMipsSizeReduce::ReduceXWtoXWSP(MachineInstr *MI,
-                                         const ReduceEntry &Entry) {
+bool MicroMipsSizeReduce::ReduceXWtoXWSP(void *FunArgs) {
+
+  ReduceEntryFunArgs Arguments = *(ReduceEntryFunArgs *)FunArgs;
+  MachineInstr *MI = Arguments.MI;
+  const ReduceEntry &Entry = Arguments.Entry;
 
   if (!ImmInRange(MI, Entry))
     return false;
 
   if (!IsSP(MI->getOperand(1)))
     return false;
 
   return ReplaceInstruction(MI, Entry);
 }
 
-bool MicroMipsSizeReduce::ReduceArithmeticInstructions(
-    MachineInstr *MI, const ReduceEntry &Entry) {
+bool MicroMipsSizeReduce::ReduceXWtoXWP(void *FunArgs) {
+
+  ReduceEntryFunArgs Arguments = *(ReduceEntryFunArgs *)FunArgs;
+  const ReduceEntry &Entry = Arguments.Entry;
+  const MachineBasicBlock::instr_iterator &E = Arguments.E;
+  MachineBasicBlock::instr_iterator &NextMII = Arguments.NextMII;
+
+  MachineInstr *MI1 = Arguments.MI;
+  MachineInstr *MI2 = nullptr;
+
+  if (NextMII == E)
+    return false;
+
+  // ReduceToLwp = true/false - reduce to LWP/SWP instruction
+  bool ReduceToLwp =
+      (MI1->getOpcode() == Mips::LW) || (MI1->getOpcode() == Mips::LW_MM);
+
+  if (!CheckXWPInstr(MI1, ReduceToLwp, Entry))
+    return false;
+
+  MI2 = &*NextMII;
+  if (!CheckXWPInstr(MI2, ReduceToLwp, Entry))
+    return false;
+
+  bool Reduce = false;
+  bool ConsecutiveForward = false;
+  bool ConsecutiveBackward = false;
+
+  unsigned Reg1 = MI1->getOperand(1).getReg();
+  unsigned Reg2 = MI2->getOperand(1).getReg();
+
+  if (Reg1 == Reg2) {
+    ConsecutiveForward = ConsecutiveInstr(MI1, MI2);
+    ConsecutiveBackward = ConsecutiveInstr(MI2, MI1);
+    Reduce = ConsecutiveForward || ConsecutiveBackward;
+  }
+
+  if (!Reduce)
+    return false;
+
+  NextMII = std::next(NextMII);
+  return ReplaceInstruction(MI1, Entry, MI2, ConsecutiveForward);
+}
+
+bool MicroMipsSizeReduce::ReduceArithmeticInstructions(void *FunArgs) {
+
+  ReduceEntryFunArgs Arguments = *(ReduceEntryFunArgs *)FunArgs;
+  MachineInstr *MI = Arguments.MI;
+  const ReduceEntry &Entry = Arguments.Entry;
 
   if (!isMMThreeBitGPRegister(MI->getOperand(0)) ||
       !isMMThreeBitGPRegister(MI->getOperand(1)) ||
       !isMMThreeBitGPRegister(MI->getOperand(2)))
     return false;
 
   return ReplaceInstruction(MI, Entry);
 }
 
-bool MicroMipsSizeReduce::ReduceADDIUToADDIUR1SP(MachineInstr *MI,
-                                                 const ReduceEntry &Entry) {
+bool MicroMipsSizeReduce::ReduceADDIUToADDIUR1SP(void *FunArgs) {
+
+  ReduceEntryFunArgs Arguments = *(ReduceEntryFunArgs *)FunArgs;
+  MachineInstr *MI = Arguments.MI;
+  const ReduceEntry &Entry = Arguments.Entry;
 
   if (!ImmInRange(MI, Entry))
     return false;
 
   if (!isMMThreeBitGPRegister(MI->getOperand(0)) || !IsSP(MI->getOperand(1)))
     return false;
 
   return ReplaceInstruction(MI, Entry);
 }
 
-bool MicroMipsSizeReduce::ReduceADDIUToADDIUSP(MachineInstr *MI,
-                                               const ReduceEntry &Entry) {
+bool MicroMipsSizeReduce::ReduceADDIUToADDIUSP(void *FunArgs) {
+
+  ReduceEntryFunArgs Arguments = *(ReduceEntryFunArgs *)FunArgs;
+  MachineInstr *MI = Arguments.MI;
+  const ReduceEntry &Entry = Arguments.Entry;
 
   int64_t ImmValue;
   if (!GetImm(MI, Entry.ImmField(), ImmValue))
     return false;
 
   if (!AddiuspImmValue(ImmValue))
     return false;
 
   if (!IsSP(MI->getOperand(0)) || !IsSP(MI->getOperand(1)))
     return false;
 
   return ReplaceInstruction(MI, Entry);
 }
 
-bool MicroMipsSizeReduce::ReduceLXUtoLXU16(MachineInstr *MI,
-                                           const ReduceEntry &Entry) {
+bool MicroMipsSizeReduce::ReduceLXUtoLXU16(void *FunArgs) {
+
+  ReduceEntryFunArgs Arguments = *(ReduceEntryFunArgs *)FunArgs;
+  MachineInstr *MI = Arguments.MI;
+  const ReduceEntry &Entry = Arguments.Entry;
 
   if (!ImmInRange(MI, Entry))
     return false;
 
   if (!isMMThreeBitGPRegister(MI->getOperand(0)) ||
       !isMMThreeBitGPRegister(MI->getOperand(1)))
     return false;
 
   return ReplaceInstruction(MI, Entry);
 }
 
-bool MicroMipsSizeReduce::ReduceSXtoSX16(MachineInstr *MI,
-                                         const ReduceEntry &Entry) {
+bool MicroMipsSizeReduce::ReduceSXtoSX16(void *FunArgs) {
+
+  ReduceEntryFunArgs Arguments = *(ReduceEntryFunArgs *)FunArgs;
+  MachineInstr *MI = Arguments.MI;
+  const ReduceEntry &Entry = Arguments.Entry;
 
   if (!ImmInRange(MI, Entry))
     return false;
 
   if (!isMMSourceRegister(MI->getOperand(0)) ||
       !isMMThreeBitGPRegister(MI->getOperand(1)))
     return false;
 
   return ReplaceInstruction(MI, Entry);
 }
 
-bool MicroMipsSizeReduce::ReduceXORtoXOR16(MachineInstr *MI,
-                                           const ReduceEntry &Entry) {
+bool MicroMipsSizeReduce::ReduceXORtoXOR16(void *FunArgs) {
+  ReduceEntryFunArgs Arguments = *(ReduceEntryFunArgs *)FunArgs;
+  MachineInstr *MI = Arguments.MI;
+  const ReduceEntry &Entry = Arguments.Entry;
+
   if (!isMMThreeBitGPRegister(MI->getOperand(0)) ||
       !isMMThreeBitGPRegister(MI->getOperand(1)) ||
       !isMMThreeBitGPRegister(MI->getOperand(2)))
     return false;
 
   if (!(MI->getOperand(0).getReg() == MI->getOperand(2).getReg()) &&
       !(MI->getOperand(0).getReg() == MI->getOperand(1).getReg()))
     return false;
for (; MII != E; MII = NextMII) {
     NextMII = std::next(MII);
     MachineInstr *MI = &*MII;
 
     // Don't reduce bundled instructions or pseudo operations
     if (MI->isBundle() || MI->isTransient())
       continue;
 
     // Try to reduce 32-bit instruction into 16-bit instruction
-    Modified |= ReduceMI(MII);
+    Modified |= ReduceMI(MII, NextMII, E);
   }
 
   return Modified;
 }
 
 bool MicroMipsSizeReduce::ReplaceInstruction(MachineInstr *MI,
-                                             const ReduceEntry &Entry) {
+                                             const ReduceEntry &Entry,
+                                             MachineInstr *MI2, bool flag) {
 
   enum OperandTransfer OpTransfer = Entry.TransferOperands();
 
   DEBUG(dbgs() << "Converting 32-bit: " << *MI);
   ++NumReduced;
 
   if (OpTransfer == OT_OperandsAll) {
     MI->setDesc(MipsII->get(Entry.NarrowOpc()));
case OT_OperandsXOR: {
         MIB.add(MI->getOperand(2));
       } else {
         MIB.add(MI->getOperand(0));
         MIB.add(MI->getOperand(2));
         MIB.add(MI->getOperand(1));
       }
       break;
     }
+    case OT_OperandsXwp: {
+      if (flag) {
+        MIB.add(MI->getOperand(0));
+        // FIXME: This should be MIB.add(MI2->getOperand(0));
+        // However, TabGen counts regpair as one output operand,
+        // and that introduces machine verfier error for lwp instruction.
+        // Setting the second register as undef, bypasses this error.
+        // This should not introduce bugs as this pass is run
+        // immediately before machine code is emitted.
+        MIB.addReg(MI2->getOperand(0).getReg(), RegState::Undef);
+        MIB.add(MI->getOperand(1));
+        MIB.add(MI->getOperand(2));
+      } else { // consecutive backward
+        MIB.add(MI2->getOperand(0));
+        // FIXME: This should be MIB.add(MI->getOperand(0));
+        // See the comment above.
+        MIB.addReg(MI->getOperand(0).getReg(), RegState::Undef);
+        MIB.add(MI2->getOperand(1));
+        MIB.add(MI2->getOperand(2));
+      }
+
+      DEBUG(dbgs() << "and converting 32-bit: " << *MI2
+                   << "       to: " << *MIB);
+
+      MBB.erase_instr(MI);
+      MBB.erase_instr(MI2);
+      return true;
+    }
+
     default:
       llvm_unreachable("Unknown operand transfer!");
     }
 
     // Transfer MI flags.
     MIB.setMIFlags(MI->getFlags());
 
     DEBUG(dbgs() << "       to 16-bit: " << *MIB);
     MBB.erase_instr(MI);
     return true;
   }
   return false;
 }
 
 bool MicroMipsSizeReduce::runOnMachineFunction(MachineFunction &MF) {
 
   Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
 
   // TODO: Add support for other subtargets:
-  // microMIPS32r6 and microMIPS64r6
+  // microMIPS32r6
   if (!Subtarget->inMicroMipsMode() || !Subtarget->hasMips32r2() ||
       Subtarget->hasMips32r6())
     return false;
 
   MipsII = static_cast<const MipsInstrInfo *>(Subtarget->getInstrInfo());
 
   bool Modified = false;
   MachineFunction::iterator I = MF.begin(), E = MF.end();

test/CodeGen/Mips/llvm-ir/and.ll

 ; RUN:    -check-prefixes=ALL,GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,GP64
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MM,MM32
+; RUN:    -check-prefixes=ALL,MM,MM32,MM32r3
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MM,MM32
+; RUN:    -check-prefixes=ALL,MM,MM32,MM32r6
 ; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MM,MM64
 
 define signext i1 @and_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: and_i1:
 
   ; GP32:         and     $2, $4, $5
; ALL-LABEL: and_i128:
   ; GP32:         lw      $[[T2:[0-9]+]], 24($sp)
   ; GP32:         and     $4, $6, $[[T2]]
   ; GP32:         lw      $[[T3:[0-9]+]], 28($sp)
   ; GP32:         and     $5, $7, $[[T3]]
 
   ; GP64:         and     $2, $4, $6
   ; GP64:         and     $3, $5, $7
 
-  ; MM32:         lw      $[[T0:[0-9]+]], 20($sp)
-  ; MM32:         lw      $[[T1:[0-9]+]], 16($sp)
-  ; MM32:         and16   $[[T1]], $4
-  ; MM32:         and16   $[[T0]], $5
+  ; MM32r6:       lw      $[[T0:[0-9]+]], 20($sp)
+  ; MM32r6:       lw      $[[T1:[0-9]+]], 16($sp)
+  ; MM32r6:       and16   $[[T1]], $4
+  ; MM32r6:       and16   $[[T0]], $5
+  ; MM32r3:       lwp     $[[T1:[0-9]+]], 16($sp)
+  ; MM32r3:       and16   $[[T1]], $4
+  ; MM32r3:       and16   $[[T0:[0-9]+]], $5
   ; MM32:         lw      $[[T2:[0-9]+]], 24($sp)
   ; MM32:         and16   $[[T2]], $6
   ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
   ; MM32:         and16   $[[T3]], $7
 
   ; MM64:         and     $2, $4, $6
   ; MM64:         and     $3, $5, $7
 

test/CodeGen/Mips/llvm-ir/or.ll

 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefixes=ALL,GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefixes=ALL,GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefixes=ALL,GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,GP32
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s -check-prefixes=ALL,GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefixes=ALL,GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefixes=ALL,GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s -check-prefixes=ALL,GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GP64
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MM,MM32
+; RUN:    -check-prefixes=ALL,MM,MM32,MM32r3
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MM,MM32
+; RUN:    -check-prefixes=ALL,MM,MM32,MM32r6
 ; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MM,MM64
 
 define signext i1 @or_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: or_i1:
 
   ; GP32:         or      $2, $4, $5
; ALL-LABEL: or_i128:
   ; GP32:         lw      $[[T0:[0-9]+]], 24($sp)
   ; GP32:         or      $4, $6, $[[T0]]
   ; GP32:         lw      $[[T3:[0-9]+]], 28($sp)
   ; GP32:         or      $5, $7, $[[T3]]
 
   ; GP64:         or      $2, $4, $6
   ; GP64:         or      $3, $5, $7
 
-  ; MM32:         lw      $[[T1:[0-9]+]], 20($sp)
-  ; MM32:         lw      $[[T2:[0-9]+]], 16($sp)
-  ; MM32:         or16    $[[T2]], $4
-  ; MM32:         or16    $[[T1]], $5
+  ; MM32r6:       lw      $[[T1:[0-9]+]], 20($sp)
+  ; MM32r6:       lw      $[[T2:[0-9]+]], 16($sp)
+  ; MM32r6:       or16    $[[T2]], $4
+  ; MM32r6:       or16    $[[T1]], $5
+  ; MM32r3:       lwp     $[[T2:[0-9]+]], 16($sp)
+  ; MM32r3:       or16    $[[T2]], $4
+  ; MM32r3:       or16    $[[T1:[0-9]+]], $5
   ; MM32:         lw      $[[T0:[0-9]+]], 24($sp)
   ; MM32:         or16    $[[T0]], $6
   ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
   ; MM32:         or16    $[[T3]], $7
 
   ; MM64:         or      $2, $4, $6
   ; MM64:         or      $3, $5, $7
 

test/CodeGen/Mips/llvm-ir/xor.ll

 ; RUN:    -check-prefixes=ALL,GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,GP64
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MM,MM32
+; RUN:    -check-prefixes=ALL,MM,MM32,MM32r3
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MM,MM32
+; RUN:    -check-prefixes=ALL,MM,MM32,MM32r6
 ; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MM,MM64
 
 define signext i1 @xor_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: xor_i1:
 
   ; GP32:         xor     $2, $4, $5
; ALL-LABEL: xor_i128:
   ; GP32:         lw      $[[T0:[0-9]+]], 24($sp)
   ; GP32:         xor     $4, $6, $[[T0]]
   ; GP32:         lw      $[[T3:[0-9]+]], 28($sp)
   ; GP32:         xor     $5, $7, $[[T3]]
 
   ; GP64:         xor     $2, $4, $6
   ; GP64:         xor     $3, $5, $7
 
-  ; MM32:         lw      $[[T1:[0-9]+]], 20($sp)
-  ; MM32:         lw      $[[T2:[0-9]+]], 16($sp)
-  ; MM32:         xor16   $[[T2]], $4
-  ; MM32:         xor16   $[[T1]], $5
+  ; MM32r6:       lw      $[[T1:[0-9]+]], 20($sp)
+  ; MM32r6:       lw      $[[T2:[0-9]+]], 16($sp)
+  ; MM32r6:       xor16   $[[T2]], $4
+  ; MM32r6:       xor16   $[[T1]], $5
+  ; MM32r3:       lwp     $[[T2:[0-9]+]], 16($sp)
+  ; MM32r3:       xor16   $[[T2]], $4
+  ; MM32r3:       xor16   $[[T1:[0-9]+]], $5
   ; MM32:         lw      $[[T0:[0-9]+]], 24($sp)
   ; MM32:         xor16   $[[T0]], $6
   ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
   ; MM32:         xor16   $[[T3]], $7
 
   ; MM64:         xor     $2, $4, $6
   ; MM64:         xor     $3, $5, $7
 

test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.ll

+; RUN: llc -march=mipsel -mattr=+micromips -mcpu=mips32r2 -verify-machineinstrs < %s | FileCheck %s
+
+; Function Attrs: nounwind
+define i32 @fun(i32* %adr, i32 %val) {
+entry:
+; CHECK: swp
+; CHECK: lwp
+  %call1 =  call i32* @fun1()
+  store i32 %val, i32* %adr, align 4
+  ret i32 0
+}
+
+declare i32* @fun1()
+