[MIPS][MicroMIPS] Extending size reduction pass with LWP and SWP
Needs ReviewPublic

Authored by milena.vujosevic.janicic on Oct 20 2017, 2:14 AM.

Details

Summary

The patch extends size reduction pass for MicroMIPS.
It introduces reduction of two instructions into one instruction:
Two SW instructions are transformed into one SWP instrucition.
Two LW instructions are transformed into one LWP instrucition.

Diff Detail

I would very much appreciate to get some comments.

sdardis requested changes to this revision.Dec 7 2017, 8:16 AM

Can you also provide some tests than ensure that lwp/swp is not formed when the first register is ra? You'll need to use some mir based testing (i.e. compile an ll file and use -stop-before= and the list test will use -start-after=)

lib/Target/Mips/MicroMipsSizeReduction.cpp
92

You should not be using void * pointers. Instead, provide a typedef for the structure you're passing and use that instead.

121–133

Provide a forward declaration and typedef for this structure above 'struct ReduceEntry', as void * should not be used.

190

The parameter flag should have a more descriptive name.

491–495

Swap these two blocks in order and you can the set MI2 to NextMII immediately.

642–647

Unfortunately this is not the case that this pass is among the last to run before machine code is emitted. This pass runs before the delay slot filler+long branch+hazard scheduling. There are other general later passes which do some analysis for stackmaps and debug information and funclet layout and the like.

A particular problem here is that as the lwp/swp instructions either write/read their operands the delay slot filler will not be able to or will incorrect analyse that for the purposes of filling delay slots.

The second problem is that lwp and swp are unpredictable when placed in delay slots and the delay slot filler doesn't know that.

There are number of issues to be resolved here: correcting the definition of lwp and swp so that their definition reflects their actual operation; marking this instructions in some way as being unsuitable for being placed in delay slots.

692

Unnecessary change.

This revision now requires changes to proceed.Dec 7 2017, 8:16 AM

All the comments are taken into account.

sdardis added inline comments.Feb 12 2018, 3:06 AM
lib/Target/Mips/MicroMipsSizeReduction.cpp
338

instruciton -> instruction

402

Rather than passing an explicit end iterator, determine the end from the instruction iterator MII, this reduces the number of arguments to be passed.

test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.ll
2

Change the -march=mipsel to -mtriple=mipsel-unknown-linux-gnu and use update_llc_checks.py to generate the check lines.

Can you add another version of this test that is .mir based but with LW_MM and SW_MM, and mixes of LW & LW_MM, similarly for the stores?

All the comments are taken into account.

I would very much appreciate to get some comments.

Hi Milena, sorry for the delay in getting back to this, I', currently on holiday but I will get back to looking at this sometime next week.

Rebased against trunk.

petarj added a subscriber: petarj.Fri, May 18, 3:11 PM

This looks ok. One the patch that I have made this dependant on lands, you should be able to get rid of the undefs on the registers, as they'll have the correct descriptions.