The patch extends size reduction pass for MicroMIPS.
It introduces reduction of two instructions into one instruction:
Two SW instructions are transformed into one SWP instrucition.
Two LW instructions are transformed into one LWP instrucition.
Can you also provide some tests than ensure that lwp/swp is not formed when the first register is ra? You'll need to use some mir based testing (i.e. compile an ll file and use -stop-before= and the list test will use -start-after=)
You should not be using void * pointers. Instead, provide a typedef for the structure you're passing and use that instead.
Provide a forward declaration and typedef for this structure above 'struct ReduceEntry', as void * should not be used.
The parameter flag should have a more descriptive name.
Swap these two blocks in order and you can the set MI2 to NextMII immediately.
Unfortunately this is not the case that this pass is among the last to run before machine code is emitted. This pass runs before the delay slot filler+long branch+hazard scheduling. There are other general later passes which do some analysis for stackmaps and debug information and funclet layout and the like.
A particular problem here is that as the lwp/swp instructions either write/read their operands the delay slot filler will not be able to or will incorrect analyse that for the purposes of filling delay slots.
The second problem is that lwp and swp are unpredictable when placed in delay slots and the delay slot filler doesn't know that.
There are number of issues to be resolved here: correcting the definition of lwp and swp so that their definition reflects their actual operation; marking this instructions in some way as being unsuitable for being placed in delay slots.