MIPS32r6 compact indexed jumps

[jkolek]

Summary

Implemented *_DESC, *_ENC classes, encoder/decoder methods.

[dsanders]

LGTM but could you explain the need for the custom instruction decode function? It looks like the usual tablegen-erated one would do the same thing but I'm also expecting the branches to have a couple issues with the tablegen-erated code (because of the 'rs < rt' restrictions and similar).

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h

105

'MM' suffix in comment

lib/Target/Mips/Mips32r6InstrInfo.td

163

I'm not sure why a custom instruction decode function is necessary. Can you explain?

[vmedic]

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

896 ↗

(On Diff #9269)

I believe this should be doing a sign extend of the offset value.

[jkolek]

Here the method DecodeJumpOffset16 is removed and the DecodeSimm16 is used instead. Also, the MM sufix is removed from the comment in MipsMCCodeEmitter.h.

[jkolek]

Committed revision: 208981.

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h

public:
 
   // getBranchTarget26OpValue - Return binary encoding of the branch
   // offset operand. If the machine operand requires relocation,
   // record the relocation and return zero.
   unsigned getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
                                     SmallVectorImpl<MCFixup> &Fixups,
                                     const MCSubtargetInfo &STI) const;
 
+  // getJumpOffset16OpValue - Return binary encoding of the jump
+  // offset operand. If the machine operand requires relocation,
+  // record the relocation and return zero.
+  unsigned getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
+                                  SmallVectorImpl<MCFixup> &Fixups,
+                                  const MCSubtargetInfo &STI) const;
+
   // getMachineOpValue - Return binary encoding of operand. If the machin
   // operand requires relocation, record the relocation and return zero.
   unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
                              SmallVectorImpl<MCFixup> &Fixups,
                              const MCSubtargetInfo &STI) const;
 
   unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
                              SmallVectorImpl<MCFixup> &Fixups,

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
 
   assert(MO.isExpr() &&
          "getBranchTarget26OpValue expects only expressions or immediates");
 
   // TODO: Push 26 PC fixup.
   return 0;
 }
 
+/// getJumpOffset16OpValue - Return binary encoding of the jump
+/// target operand. If the machine operand requires relocation,
+/// record the relocation and return zero.
+unsigned MipsMCCodeEmitter::
+getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
+                     SmallVectorImpl<MCFixup> &Fixups,
+                     const MCSubtargetInfo &STI) const {
+
+  const MCOperand &MO = MI.getOperand(OpNo);
+
+  if (MO.isImm()) return MO.getImm();
+
+  assert(MO.isExpr() &&
+         "getJumpOffset16OpValue expects only expressions or an immediate");
+
+  // TODO: Push fixup.
+  return 0;
+}
+
 /// getJumpTargetOpValue - Return binary encoding of the jump
 /// target operand. If the machine operand requires relocation,
 /// record the relocation and return zero.
 unsigned MipsMCCodeEmitter::
 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
                      SmallVectorImpl<MCFixup> &Fixups,
                      const MCSubtargetInfo &STI) const {
 

lib/Target/Mips/Mips32r6InstrFormats.td

class CMP_BRANCH_OFF21_FM<bits<6> funct> : MipsR6Inst {
   bits<21> offset;
 
   bits<32> Inst;
 
   let Inst{31-26} = funct;
   let Inst{25-21} = rs;
   let Inst{20-0}  = offset;
 }
+
+class JMP_IDX_COMPACT_FM<bits<6> funct> : MipsR6Inst {
+  bits<5>  rt;
+  bits<16> offset;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = funct;
+  let Inst{25-21} = 0b000000;
+  let Inst{20-16} = rt;
+  let Inst{15-0}  = offset;
+}

lib/Target/Mips/Mips32r6InstrInfo.td

 
 def brtarget26 : Operand<OtherVT> {
   let EncoderMethod = "getBranchTarget26OpValue";
   let OperandType = "OPERAND_PCREL";
   let DecoderMethod = "DecodeBranchTarget26";
   let ParserMatchClass = MipsJumpTargetAsmOperand;
 }
 
+def jmpoffset16 : Operand<OtherVT> {
+  let EncoderMethod = "getJumpOffset16OpValue";
+  let ParserMatchClass = MipsJumpTargetAsmOperand;
+}
+
+def calloffset16 : Operand<iPTR> {
+  let EncoderMethod = "getJumpOffset16OpValue";
+  let ParserMatchClass = MipsJumpTargetAsmOperand;
+}
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction Encodings
 //
 //===----------------------------------------------------------------------===//
 
 class BALC_ENC   : BRANCH_OFF26_FM<0b111010>;
 class BC_ENC     : BRANCH_OFF26_FM<0b110010>;
 class BEQC_ENC   : CMP_BRANCH_OFF16_FM<0b001000>;
 class BNEC_ENC   : CMP_BRANCH_OFF16_FM<0b011000>;
 
 class BLTZC_ENC  : CMP_BRANCH_OFF16_FM<0b010111>;
 class BGEZC_ENC  : CMP_BRANCH_OFF16_FM<0b010110>;
 
 class BLEZC_ENC  : CMP_BRANCH_RT_OFF16_FM<0b010110>;
 class BGTZC_ENC  : CMP_BRANCH_RT_OFF16_FM<0b010111>;
 
 class BEQZC_ENC  : CMP_BRANCH_OFF21_FM<0b110110>;
 class BNEZC_ENC  : CMP_BRANCH_OFF21_FM<0b111110>;
 
+class JIALC_ENC  : JMP_IDX_COMPACT_FM<0b111110>;
+class JIC_ENC    : JMP_IDX_COMPACT_FM<0b110110>;
+
 class MUH_ENC    : SPECIAL_3R_FM<0b00011, 0b011000>;
 class MUHU_ENC   : SPECIAL_3R_FM<0b00011, 0b011001>;
 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
 class MULU_ENC   : SPECIAL_3R_FM<0b00010, 0b011001>;
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Descriptions
class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
   list<Register> Defs = [AT];
 }
 
 class BALC_DESC   : BC_DESC_BASE<"balc", brtarget26> {
   bit isCall = 1;
   list<Register> Defs = [RA];
 }
 
+class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
+                                RegisterOperand GPROpnd> {
+  dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
+  string AsmString = !strconcat(opstr, "\t$rt, $offset");
+  list<dag> Pattern = [];
+  bit isTerminator = 1;
+  bit hasDelaySlot = 0;
+  string DecoderMethod = "DecodeSimm16";
+}
+
 class BC_DESC     : BC_DESC_BASE<"bc", brtarget26>;
 class BEQC_DESC   : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
 class BNEC_DESC   : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
 
 class BLTZC_DESC  : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd> {
   string Constraints = "$rs = $rt";
 }
 
 class BGEZC_DESC  : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd> {
   string Constraints = "$rs = $rt";
 }
 
 class BLEZC_DESC  : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
 class BGTZC_DESC  : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
 
 class BEQZC_DESC  : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
 class BNEZC_DESC  : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
 
+class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
+                                             GPR32Opnd> {
+  bit isCall = 1;
+  list<Register> Defs = [RA];
+}
+
+class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR32Opnd> {
+  bit isBarrier = 1;
+  list<Register> Defs = [AT];
+}
+
 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
   dag OutOperandList = (outs GPROpnd:$rd);
   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
   list<dag> Pattern = [];
 }
 
 class MUH_DESC    : MUL_R6_DESC_BASE<"muh", GPR32Opnd>;

 def BNVC;
 def BOVC;
 def CLASS_D;
 def CLASS_S;
 def CMP_CC_D;
 def CMP_CC_S;
 def DIV;   // Not to be confused with the old div
 def DIVU;  // Not to be confused with the old div
-def JIALC;
-def JIC;
+def JIALC     : JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
+def JIC       : JIC_ENC, JIC_DESC, ISA_MIPS32R6;
 // def LSA; // See MSA
 def LWPC;
 def LWUPC;
 def MADDF;
 def MAXA_D;
 def MAXA_S;
 def MAX_D;
 def MAX_S;

lib/Target/Mips/MipsCodeEmitter.cpp

private:
   unsigned getJumpTargetOpValueMM(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getBranchTargetOpValueMM(const MachineInstr &MI,
                                     unsigned OpNo) const;
 
   unsigned getBranchTarget21OpValue(const MachineInstr &MI,
                                     unsigned OpNo) const;
   unsigned getBranchTarget26OpValue(const MachineInstr &MI,
                                     unsigned OpNo) const;
+  unsigned getJumpOffset16OpValue(const MachineInstr &MI, unsigned OpNo) const;
 
   unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getMemEncoding(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getMemEncodingMMImm12(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getMSAMemEncoding(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getSizeExtEncoding(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getSizeInsEncoding(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getLSAImmEncoding(const MachineInstr &MI, unsigned OpNo) const;

 }
 
 unsigned MipsCodeEmitter::getBranchTarget26OpValue(const MachineInstr &MI,
                                                    unsigned OpNo) const {
   llvm_unreachable("Unimplemented function.");
   return 0;
 }
 
+unsigned MipsCodeEmitter::getJumpOffset16OpValue(const MachineInstr &MI,
+                                                 unsigned OpNo) const {
+  llvm_unreachable("Unimplemented function.");
+  return 0;
+}
+
 unsigned MipsCodeEmitter::getBranchTargetOpValue(const MachineInstr &MI,
                                                  unsigned OpNo) const {
   MachineOperand MO = MI.getOperand(OpNo);
   emitMachineBasicBlock(MO.getMBB(), getRelocation(MI, MO));
   return 0;
 }
 
 unsigned MipsCodeEmitter::getMemEncoding(const MachineInstr &MI,

test/MC/Mips/mips32r6/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 | FileCheck %s
         beqc    $5, $6, 256      # CHECK: beqc $5, $6, 256 # encoding: [0x20,0xa6,0x00,0x40]
         bnec    $5, $6, 256      # CHECK: bnec $5, $6, 256 # encoding: [0x60,0xa6,0x00,0x40]
         beqzc   $5, 72256        # CHECK: beqzc $5, 72256  # encoding: [0xd8,0xa0,0x46,0x90]
         bnezc   $5, 72256        # CHECK: bnezc $5, 72256  # encoding: [0xf8,0xa0,0x46,0x90]
         bltzc   $5, 256          # CHECK: bltzc $5, 256    # encoding: [0x5c,0xa5,0x00,0x40]
         bgezc   $5, 256          # CHECK: bgezc $5, 256    # encoding: [0x58,0xa5,0x00,0x40]
         blezc   $5, 256          # CHECK: blezc $5, 256    # encoding: [0x58,0x05,0x00,0x40]
         bgtzc   $5, 256          # CHECK: bgtzc $5, 256    # encoding: [0x5c,0x05,0x00,0x40]
+        jialc   $5, 256          # CHECK: jialc $5, 256    # encoding: [0xf8,0x05,0x01,0x00]
+        jic     $5, 256          # CHECK: jic $5, 256      # encoding: [0xd8,0x05,0x01,0x00]

test/MC/Mips/mips64r6/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 | FileCheck %s
         beqc    $5, $6, 256      # CHECK: beqc $5, $6, 256 # encoding: [0x20,0xa6,0x00,0x40]
         bnec    $5, $6, 256      # CHECK: bnec $5, $6, 256 # encoding: [0x60,0xa6,0x00,0x40]
         beqzc   $5, 72256        # CHECK: beqzc $5, 72256  # encoding: [0xd8,0xa0,0x46,0x90]
         bnezc   $5, 72256        # CHECK: bnezc $5, 72256  # encoding: [0xf8,0xa0,0x46,0x90]
         bltzc   $5, 256          # CHECK: bltzc $5, 256    # encoding: [0x5c,0xa5,0x00,0x40]
         bgezc   $5, 256          # CHECK: bgezc $5, 256    # encoding: [0x58,0xa5,0x00,0x40]
         blezc   $5, 256          # CHECK: blezc $5, 256    # encoding: [0x58,0x05,0x00,0x40]
         bgtzc   $5, 256          # CHECK: bgtzc $5, 256    # encoding: [0x5c,0x05,0x00,0x40]
+        jialc   $5, 256          # CHECK: jialc $5, 256    # encoding: [0xf8,0x05,0x01,0x00]
+        jic     $5, 256          # CHECK: jic $5, 256      # encoding: [0xd8,0x05,0x01,0x00]