[mips][mips64r6] Add aui, daui, dahi, and dati

[dsanders]

Summary

Depends on D3671

[vmedic]

LGTM

[dsanders]

Refresh patch so it applies cleanly

[jkolek]

lib/Target/Mips/Mips32r6InstrFormats.td

63

I have just a question. Is there any particular reason why is inheritance used here? Couldn't we have single format class for AUI, DAHI, DATI and DAUI, and just to pass opcode as parameter, like we did for all other similar instructions so far? I'm just wondering why not to have a single style for doing a same things.
Maybe the class name should be different, but I was thinking to have something like this:

class AUI_FM<bits<6> opcode> : MipsR6Inst {
 bits<5> rs;
 bits<5> rt;
 bits<16> imm;

 bits<32> Inst;

 let Inst{31-26} = opcode;
 let Inst{25-21} = rs;
 let Inst{20-16} = rt;
 let Inst{15-0} = imm;
}

[dsanders]

lib/Target/Mips/Mips32r6InstrFormats.td

63

DAHI and DATI are actually in the REGIMM_FM format.

For AUI and DAUI: My thinking was that the format is derived from the top 6 bits of the opcode (with a few exceptions such as the SPECIAL formats). AUI and DAUI differ in these format bits and should therefore be different formats. Inheritance is merely used to exploit the similarity between these two formats.

At the moment the compact branch formats are inconsistent with this line of thinking. I'll probably separate them into BLEZL/BGTZL/etc. formats at some point after we have a minimal compiler working. The main advantage of this is that you can glance at the format name and easily see how it maps to the spec since it uses the same names. It's also easier to spot mistakes in words rather than binary values. The OPCODE*_* constants are the result of the same line of thinking.

[dsanders]

lib/Target/Mips/Mips32r6InstrFormats.td

63

I've just committed the patch (so I can commit the later work) but I'm still open to changing this if that's what we decide to do.

lib/Target/Mips/Mips32r6InstrFormats.td

 }
 
 //===----------------------------------------------------------------------===//
 //
 // Field Values
 //
 //===----------------------------------------------------------------------===//
 
-def OPGROUP_COP1 { bits<6> Value = 0b010001; }
+def OPGROUP_COP1    { bits<6> Value = 0b010001; }
+def OPGROUP_AUI     { bits<6> Value = 0b001111; }
+def OPGROUP_DAUI    { bits<6> Value = 0b011101; }
+def OPGROUP_REGIMM  { bits<6> Value = 0b000001; }
 def OPGROUP_SPECIAL { bits<6> Value = 0b000000; }
 
+class OPCODE5<bits<5> Val> {
+  bits<5> Value = Val;
+}
+def OPCODE5_DAHI : OPCODE5<0b00110>;
+def OPCODE5_DATI : OPCODE5<0b11110>;
+
 class FIELD_FMT<bits<5> Val> {
   bits<5> Value = Val;
 }
 def FIELD_FMT_S : FIELD_FMT<0b10000>;
 def FIELD_FMT_D : FIELD_FMT<0b10001>;
 
 //===----------------------------------------------------------------------===//
 //
 // Encoding Formats
 //
 //===----------------------------------------------------------------------===//
 
+class AUI_FM : MipsR6Inst {
+  bits<5> rs;
+  bits<5> rt;
+  bits<16> imm;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = OPGROUP_AUI.Value;
+  let Inst{25-21} = rs;
+  let Inst{20-16} = rt;
+  let Inst{15-0} = imm;
+}
+
+class DAUI_FM : AUI_FM {
+  let Inst{31-26} = OPGROUP_DAUI.Value;
+}
+
 class COP1_3R_FM<bits<6> funct, FIELD_FMT Format> : MipsR6Inst {
   bits<5> ft;
   bits<5> fs;
   bits<5> fd;
 
   bits<32> Inst;
 
   let Inst{31-26} = OPGROUP_COP1.Value;
class SPECIAL_3R_FM<bits<5> mulop, bits<6> funct> : MipsR6Inst {
 
   let Inst{31-26} = OPGROUP_SPECIAL.Value;
   let Inst{25-21} = rs;
   let Inst{20-16} = rt;
   let Inst{15-11} = rd;
   let Inst{10-6}  = mulop;
   let Inst{5-0}   = funct;
 }
+
+class REGIMM_FM<OPCODE5 Operation> : MipsR6Inst {
+  bits<5> rs;
+  bits<16> imm;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = OPGROUP_REGIMM.Value;
+  let Inst{25-21} = rs;
+  let Inst{20-16} = Operation.Value;
+  let Inst{15-0} = imm;
+}

lib/Target/Mips/Mips32r6InstrInfo.td

 // Rencoded: [ls][wd]c2
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Encodings
 //
 //===----------------------------------------------------------------------===//
 
+class AUI_ENC    : AUI_FM;
 class DIV_ENC    : SPECIAL_3R_FM<0b00010, 0b011010>;
 class DIVU_ENC   : SPECIAL_3R_FM<0b00010, 0b011011>;
 class MOD_ENC    : SPECIAL_3R_FM<0b00011, 0b011010>;
 class MODU_ENC   : SPECIAL_3R_FM<0b00011, 0b011011>;
 class MUH_ENC    : SPECIAL_3R_FM<0b00011, 0b011000>;
 class MUHU_ENC   : SPECIAL_3R_FM<0b00011, 0b011001>;
 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
 class MULU_ENC   : SPECIAL_3R_FM<0b00010, 0b011001>;
 class SEL_D_ENC  : COP1_3R_FM<0b010000, FIELD_FMT_D>;
 class SEL_S_ENC  : COP1_3R_FM<0b010000, FIELD_FMT_S>;
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Descriptions
 //
 //===----------------------------------------------------------------------===//
 
+class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
+  dag OutOperandList = (outs GPROpnd:$rs);
+  dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
+  string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
+  list<dag> Pattern = [];
+}
+
+class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
+
 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
   dag OutOperandList = (outs GPROpnd:$rd);
   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
   list<dag> Pattern = [];
 }
 
 class DIV_DESC  : DIVMOD_DESC_BASE<"div", GPR32Opnd>;

 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
 def ADDIUPC;
 def ALIGN; // Known as as BALIGN in DSP ASE
 def ALUIPC;
-def AUI;
+def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
 def AUIPC;
 def BALC;
 def BC1EQZ;
 def BC1NEZ;
 def BC2EQZ;
 def BC2NEZ;
 def BC;
 def BEQC;

lib/Target/Mips/Mips64r6InstrInfo.td

 // Removed: ldl, ldr, ldle, ldre, sdl, sdr, sdle, sdre
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Encodings
 //
 //===----------------------------------------------------------------------===//
 
+class DAUI_ENC    : DAUI_FM;
+class DAHI_ENC    : REGIMM_FM<OPCODE5_DAHI>;
+class DATI_ENC    : REGIMM_FM<OPCODE5_DATI>;
 class DDIV_ENC    : SPECIAL_3R_FM<0b00010, 0b011110>;
 class DDIVU_ENC   : SPECIAL_3R_FM<0b00010, 0b011111>;
 class DMOD_ENC    : SPECIAL_3R_FM<0b00011, 0b011110>;
 class DMODU_ENC   : SPECIAL_3R_FM<0b00011, 0b011111>;
 class DMUH_ENC    : SPECIAL_3R_FM<0b00011, 0b111000>;
 class DMUHU_ENC   : SPECIAL_3R_FM<0b00011, 0b111001>;
 class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b111000>;
 class DMULU_ENC   : SPECIAL_3R_FM<0b00010, 0b111001>;
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Descriptions
 //
 //===----------------------------------------------------------------------===//
 
+class DAHI_DESC    : AUI_DESC_BASE<"dahi", GPR64Opnd>;
+class DATI_DESC    : AUI_DESC_BASE<"dati", GPR64Opnd>;
+class DAUI_DESC    : AUI_DESC_BASE<"daui", GPR64Opnd>;
 class DDIV_DESC    : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd>;
 class DDIVU_DESC   : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd>;
 class DMOD_DESC    : DIVMOD_DESC_BASE<"dmod", GPR64Opnd>;
 class DMODU_DESC   : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd>;
 class DMUH_DESC    : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd>;
 class DMUHU_DESC   : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd>;
 class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd>;
 class DMULU_DESC   : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd>;
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
-def DAHI;
+def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
 def DALIGN;
-def DATI;
-def DAUI;
+def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
+def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
 def DBITSWAP;
 def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
 def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
 // def DLSA; // See MSA
 def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
 def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
 def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
 def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
 def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
 def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
 def LDPC;

test/MC/Mips/mips32r6/valid.s

 # Instructions that are valid
 #
 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 | FileCheck %s
 
         .set noat
         # FIXME: Add the instructions carried forward from older ISA's
+        aui     $3,$2,-23        # CHECK: aui $3, $2, -23  # encoding: [0x3c,0x62,0xff,0xe9]
         div     $2,$3,$4         # CHECK: div $2, $3, $4   # encoding: [0x00,0x64,0x10,0x9a]
         divu    $2,$3,$4         # CHECK: divu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x9b]
         mod     $2,$3,$4         # CHECK: mod $2, $3, $4   # encoding: [0x00,0x64,0x10,0xda]
         modu    $2,$3,$4         # CHECK: modu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xdb]
 #        mul     $2,$3,$4         # CHECK-TODO: mul $2, $3, $4   # encoding: [0x00,0x64,0x10,0x98]
         muh     $2,$3,$4         # CHECK: muh $2, $3, $4   # encoding: [0x00,0x64,0x10,0xd8]
         mulu    $2,$3,$4         # CHECK: mulu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x99]
         muhu    $2,$3,$4         # CHECK: muhu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xd9]
         sel.d   $f0,$f1,$f2      # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10]
         sel.s   $f0,$f1,$f2      # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10]

test/MC/Mips/mips64r6/valid.s

 # Instructions that are valid
 #
 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 | FileCheck %s
 
         .set noat
         # FIXME: Add the instructions carried forward from older ISA's
+        aui     $3,$2,-23        # CHECK: aui $3, $2, -23    # encoding: [0x3c,0x62,0xff,0xe9]
+        daui    $3,$2,0x1234     # CHECK: daui $3, $2, 4660  # encoding: [0x74,0x62,0x12,0x34]
+        dahi    $3,$3,0x5678     # CHECK: dahi $3, $3, 22136 # encoding: [0x04,0x66,0x56,0x78]
+        dati    $3,$3,0xabcd     # CHECK: dati $3, $3, 43981 # encoding: [0x04,0x7e,0xab,0xcd]
         div     $2,$3,$4         # CHECK: div $2, $3, $4   # encoding: [0x00,0x64,0x10,0x9a]
         divu    $2,$3,$4         # CHECK: divu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x9b]
         mod     $2,$3,$4         # CHECK: mod $2, $3, $4   # encoding: [0x00,0x64,0x10,0xda]
         modu    $2,$3,$4         # CHECK: modu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xdb]
         ddiv    $2,$3,$4         # CHECK: ddiv $2, $3, $4  # encoding: [0x00,0x64,0x10,0x9e]
         ddivu   $2,$3,$4         # CHECK: ddivu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9f]
         dmod    $2,$3,$4         # CHECK: dmod $2, $3, $4  # encoding: [0x00,0x64,0x10,0xde]
         dmodu   $2,$3,$4         # CHECK: dmodu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdf]