MIPS32r6 compact branch instructions

[jkolek]

Summary

Implemented *_DESC, *_ENC classes, decoder/encoder methods.
Instructions: balc, bc, beqc, bnec, beqzc, bnezc, bltzc, bgezc, blezc, bgtzc.

[dsanders]

As explained below, I'd like you to move the tests into the valid.s. There's also one minor naming convention issue, but it otherwise LGTM

Please include the full context in future since it makes it much easier to review. 'arc diff' will do this for you and makes it easier for you to upload the patch.

lib/Target/Mips/Mips32r6InstrInfo.td

102–112

It's a minor thing but it would be nice to keep the '_DESC' in the ALL base classes. Best I can think of is s/BRANCH_DESC_BASE/BC_DESC_BASE/ and s/BRANCH_BASE/BRANCH_DESC_BASE/'

156

This belongs in the encoding class

160

same

test/MC/Mips/mips32r6-compact-branch-instructions.s

1–3 ↗

(On Diff #9246)

Please add your tests to the valid.s for mips32r6. This enables easy generation of the invalid-$isa.s tests by diffing valid.s's

Also, there's no need to explicitly cover both endians, the byte swapping code is very well tested.

1–3 ↗

(On Diff #9246)

Nearly forgot to mention, that they should also be in the mips64r6/valid.s as well

[dsanders]

LGTM, thanks.

[dsanders]

lib/Target/Mips/Mips32r6InstrInfo.td

121

Can you double-check this? I don't think they really do def AT.

[jkolek]

lib/Target/Mips/Mips32r6InstrInfo.td

121

I have put AT in Defs list of *_DESC_BASE classes of the branch instructions because it is in Defs in the base classes of MIPS32r2 branch instructions where AT is used for long branches. I'm not sure if long branch implementation is necessary in MIPS64r6, and if so, whether AT should be used or not. If you think that AT is not needed here I can remove it.

[dsanders]

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

880

In case you are interested, D3761 fixes the same bug but also removes the redundant mask. The SignExtend does the same job.

lib/Target/Mips/Mips32r6InstrInfo.td

121

That makes sense. It's not needed in this patch but if we did remove it, it may need to come back when we add CodeGen support anyway. I think we should leave it in for now. We should probably add it to the other branches when we add CodeGen support as well.

[jkolek]

Committed revision: 208974.

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

static DecodeStatus DecodeBranchTarget(MCInst &Inst,
                                        uint64_t Address,
                                        const void *Decoder);
 
 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
                                      unsigned Insn,
                                      uint64_t Address,
                                      const void *Decoder);
 
+static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
+                                         unsigned Offset,
+                                         uint64_t Address,
+                                         const void *Decoder);
+
+static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
+                                         unsigned Offset,
+                                         uint64_t Address,
+                                         const void *Decoder);
+
 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 // shifted left by 1 bit.
 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
                                          unsigned Offset,
                                          uint64_t Address,
                                          const void *Decoder);
 
 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
static DecodeStatus DecodeJumpTarget(MCInst &Inst,
                                      uint64_t Address,
                                      const void *Decoder) {
 
   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
+                                         unsigned Offset,
+                                         uint64_t Address,
+                                         const void *Decoder) {
+  unsigned BranchOffset = Offset & 0x1fffff;
+  BranchOffset = SignExtend32<23>(BranchOffset << 2);
+  Inst.addOperand(MCOperand::CreateImm(BranchOffset));
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
+                                         unsigned Offset,
+                                         uint64_t Address,
+                                         const void *Decoder) {
+  unsigned BranchOffset = Offset & 0x3ffffff;
+  BranchOffset = SignExtend32<28>(BranchOffset << 2);
+  Inst.addOperand(MCOperand::CreateImm(BranchOffset));
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
                                          unsigned Offset,
                                          uint64_t Address,
                                          const void *Decoder) {
   unsigned BranchOffset = Offset & 0xffff;
   BranchOffset = SignExtend32<18>(BranchOffset << 1);
   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
   return MCDisassembler::Success;

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h

public:
 
   // getBranchTargetOpValue - Return binary encoding of the microMIPS branch
   // target operand. If the machine operand requires relocation,
   // record the relocation and return zero.
   unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
                                     SmallVectorImpl<MCFixup> &Fixups,
                                     const MCSubtargetInfo &STI) const;
 
+  // getBranchTarget21OpValue - Return binary encoding of the branch
+  // offset operand. If the machine operand requires relocation,
+  // record the relocation and return zero.
+  unsigned getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
+                                    SmallVectorImpl<MCFixup> &Fixups,
+                                    const MCSubtargetInfo &STI) const;
+
+  // getBranchTarget26OpValue - Return binary encoding of the branch
+  // offset operand. If the machine operand requires relocation,
+  // record the relocation and return zero.
+  unsigned getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
+                                    SmallVectorImpl<MCFixup> &Fixups,
+                                    const MCSubtargetInfo &STI) const;
+
   // getMachineOpValue - Return binary encoding of operand. If the machin
   // operand requires relocation, record the relocation and return zero.
   unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
                              SmallVectorImpl<MCFixup> &Fixups,
                              const MCSubtargetInfo &STI) const;
 
   unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
                              SmallVectorImpl<MCFixup> &Fixups,

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
 
   const MCExpr *Expr = MO.getExpr();
   Fixups.push_back(MCFixup::Create(0, Expr,
                    MCFixupKind(Mips::
                                fixup_MICROMIPS_PC16_S1)));
   return 0;
 }
 
+/// getBranchTarget21OpValue - Return binary encoding of the branch
+/// target operand. If the machine operand requires relocation,
+/// record the relocation and return zero.
+unsigned MipsMCCodeEmitter::
+getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
+                         SmallVectorImpl<MCFixup> &Fixups,
+                         const MCSubtargetInfo &STI) const {
+
+  const MCOperand &MO = MI.getOperand(OpNo);
+
+  // If the destination is an immediate, divide by 4.
+  if (MO.isImm()) return MO.getImm() >> 2;
+
+  assert(MO.isExpr() &&
+         "getBranchTarget21OpValue expects only expressions or immediates");
+
+  // TODO: Push 21 PC fixup.
+  return 0;
+}
+
+/// getBranchTarget26OpValue - Return binary encoding of the branch
+/// target operand. If the machine operand requires relocation,
+/// record the relocation and return zero.
+unsigned MipsMCCodeEmitter::
+getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
+                         SmallVectorImpl<MCFixup> &Fixups,
+                         const MCSubtargetInfo &STI) const {
+
+  const MCOperand &MO = MI.getOperand(OpNo);
+
+  // If the destination is an immediate, divide by 4.
+  if (MO.isImm()) return MO.getImm() >> 2;
+
+  assert(MO.isExpr() &&
+         "getBranchTarget26OpValue expects only expressions or immediates");
+
+  // TODO: Push 26 PC fixup.
+  return 0;
+}
+
 /// getJumpTargetOpValue - Return binary encoding of the jump
 /// target operand. If the machine operand requires relocation,
 /// record the relocation and return zero.
 unsigned MipsMCCodeEmitter::
 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
                      SmallVectorImpl<MCFixup> &Fixups,
                      const MCSubtargetInfo &STI) const {
 

lib/Target/Mips/Mips32r6InstrFormats.td

class SPECIAL_3R_FM<bits<5> mulop, bits<6> funct> : MipsR6Inst {
   let Inst{31-26} = 0b00000;
   let Inst{25-21} = rs;
   let Inst{20-16} = rt;
   let Inst{15-11} = rd;
   let Inst{10-6}  = mulop;
   let Inst{5-0}   = funct;
 }
 
+class BRANCH_OFF26_FM<bits<6> funct> : MipsR6Inst {
+  bits<32> Inst;
+  bits<26> offset;
+
+  let Inst{31-26} = funct;
+  let Inst{25-0}  = offset;
+}
+
+class CMP_BRANCH_OFF16_FM<bits<6> funct> : MipsR6Inst {
+  bits<5>  rs;
+  bits<5>  rt;
+  bits<16> offset;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = funct;
+  let Inst{25-21} = rs;
+  let Inst{20-16} = rt;
+  let Inst{15-0}  = offset;
+}
+
+class CMP_BRANCH_RT_OFF16_FM<bits<6> funct> : MipsR6Inst {
+  bits<5>  rt;
+  bits<16> offset;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = funct;
+  let Inst{25-21} = 0b00000;
+  let Inst{20-16} = rt;
+  let Inst{15-0}  = offset;
+}
+
+class CMP_BRANCH_OFF21_FM<bits<6> funct> : MipsR6Inst {
+  bits<5>  rs;
+  bits<21> offset;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = funct;
+  let Inst{25-21} = rs;
+  let Inst{20-0}  = offset;
+}

lib/Target/Mips/Mips32r6InstrInfo.td

 // Removed: mult, multu
 // Removed: prefx
 // Removed: sdxc1
 // Removed: suxc1
 // Removed: swxc1
 // Removed: teqi, tgei, tgeiu, tlti, tltiu, tnei
 // Rencoded: [ls][wd]c2
 
+def brtarget21 : Operand<OtherVT> {
+  let EncoderMethod = "getBranchTarget21OpValue";
+  let OperandType = "OPERAND_PCREL";
+  let DecoderMethod = "DecodeBranchTarget21";
+  let ParserMatchClass = MipsJumpTargetAsmOperand;
+}
+
+def brtarget26 : Operand<OtherVT> {
+  let EncoderMethod = "getBranchTarget26OpValue";
+  let OperandType = "OPERAND_PCREL";
+  let DecoderMethod = "DecodeBranchTarget26";
+  let ParserMatchClass = MipsJumpTargetAsmOperand;
+}
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction Encodings
 //
 //===----------------------------------------------------------------------===//
 
+class BALC_ENC   : BRANCH_OFF26_FM<0b111010>;
+class BC_ENC     : BRANCH_OFF26_FM<0b110010>;
+class BEQC_ENC   : CMP_BRANCH_OFF16_FM<0b001000>;
+class BNEC_ENC   : CMP_BRANCH_OFF16_FM<0b011000>;
+
+class BLTZC_ENC  : CMP_BRANCH_OFF16_FM<0b010111>;
+class BGEZC_ENC  : CMP_BRANCH_OFF16_FM<0b010110>;
+
+class BLEZC_ENC  : CMP_BRANCH_RT_OFF16_FM<0b010110>;
+class BGTZC_ENC  : CMP_BRANCH_RT_OFF16_FM<0b010111>;
+
+class BEQZC_ENC  : CMP_BRANCH_OFF21_FM<0b110110>;
+class BNEZC_ENC  : CMP_BRANCH_OFF21_FM<0b111110>;
+
 class MUH_ENC    : SPECIAL_3R_FM<0b00011, 0b011000>;
 class MUHU_ENC   : SPECIAL_3R_FM<0b00011, 0b011001>;
 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
 class MULU_ENC   : SPECIAL_3R_FM<0b00010, 0b011001>;
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Descriptions
 //
 //===----------------------------------------------------------------------===//
 
+class BRANCH_DESC_BASE<string asm_str, dag in_ops> {
+  string AsmString = asm_str;
+  dag InOperandList = in_ops;
+  dag OutOperandList = (outs);
+  list<dag> Pattern = [];
+  bit isBranch = 1;
+  bit isTerminator = 1;
+  bit hasDelaySlot = 0;
+}
+
+class BC_DESC_BASE<string instr_asm, DAGOperand opnd>
+  : BRANCH_DESC_BASE<!strconcat(instr_asm, "\t$offset"), (ins opnd:$offset)> {
+  bit isBarrier = 1;
+}
+
+class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
+                           RegisterOperand GPROpnd>
+  : BRANCH_DESC_BASE<!strconcat(instr_asm, "\t$rs, $rt, $offset"),
+                (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset)> {
+  list<Register> Defs = [AT];
+}
+
+class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
+                             RegisterOperand GPROpnd>
+  : BRANCH_DESC_BASE<!strconcat(instr_asm, "\t$rs, $offset"),
+                (ins GPROpnd:$rs, opnd:$offset)> {
+  list<Register> Defs = [AT];
+}
+
+class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
+                             RegisterOperand GPROpnd>
+  : BRANCH_DESC_BASE<!strconcat(instr_asm, "\t$rt, $offset"),
+                     (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset)> {
+  list<Register> Defs = [AT];
+}
+
+class BALC_DESC   : BC_DESC_BASE<"balc", brtarget26> {
+  bit isCall = 1;
+  list<Register> Defs = [RA];
+}
+
+class BC_DESC     : BC_DESC_BASE<"bc", brtarget26>;
+class BEQC_DESC   : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
+class BNEC_DESC   : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
+
+class BLTZC_DESC  : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd> {
+  string Constraints = "$rs = $rt";
+}
+
+class BGEZC_DESC  : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd> {
+  string Constraints = "$rs = $rt";
+}
+
+class BLEZC_DESC  : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
+class BGTZC_DESC  : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
+
+class BEQZC_DESC  : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
+class BNEZC_DESC  : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
+
 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
   dag OutOperandList = (outs GPROpnd:$rd);
   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
   list<dag> Pattern = [];
 }
 
 class MUH_DESC    : MUL_R6_DESC_BASE<"muh", GPR32Opnd>;
 class MUHU_DESC   : MUL_R6_DESC_BASE<"muhu", GPR32Opnd>;
 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd>;
 class MULU_DESC   : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
 def ADDIUPC;
 def ALIGN; // Known as as BALIGN in DSP ASE
 def ALUIPC;
 def AUI;
 def AUIPC;
-def BALC;
+def BALC      : BALC_ENC, BALC_DESC, ISA_MIPS32R6;
 def BC1EQZ;
 def BC1NEZ;
 def BC2EQZ;
 def BC2NEZ;
-def BC;
-def BEQC;
+def BC        : BC_ENC, BC_DESC, ISA_MIPS32R6;
+def BEQC      : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
 def BEQZALC;
-def BEQZC;
+def BEQZC     : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
 def BGEC;  // Also aliased to blec with operands swapped
 def BGEUC; // Also aliased to bleuc with operands swapped
 def BGEZALC;
-def BGEZC;
+def BGEZC     : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
 def BGTZALC;
-def BGTZC;
+def BGTZC     : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
 def BITSWAP; // Known as BITREV in DSP ASE
 def BLEZALC;
-def BLEZC;
+def BLEZC     : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
 def BLTC; // Also aliased to bgtc with operands swapped
 def BLTUC; // Also aliased to bgtuc with operands swapped
 def BLTZALC;
-def BLTZC;
-def BNEC;
+def BLTZC     : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
+def BNEC      : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
 def BNEZALC;
-def BNEZC;
+def BNEZC     : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
 def BNVC;
 def BOVC;
 def CLASS_D;
 def CLASS_S;
 def CMP_CC_D;
 def CMP_CC_S;
 def DIV;   // Not to be confused with the old div
 def DIVU;  // Not to be confused with the old div

lib/Target/Mips/MipsCodeEmitter.cpp

private:
   unsigned getRelocation(const MachineInstr &MI,
                          const MachineOperand &MO) const;
 
   unsigned getJumpTargetOpValue(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getJumpTargetOpValueMM(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getBranchTargetOpValueMM(const MachineInstr &MI,
                                     unsigned OpNo) const;
 
+  unsigned getBranchTarget21OpValue(const MachineInstr &MI,
+                                    unsigned OpNo) const;
+  unsigned getBranchTarget26OpValue(const MachineInstr &MI,
+                                    unsigned OpNo) const;
+
   unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getMemEncoding(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getMemEncodingMMImm12(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getMSAMemEncoding(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getSizeExtEncoding(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getSizeInsEncoding(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getLSAImmEncoding(const MachineInstr &MI, unsigned OpNo) const;
 

 }
 
 unsigned MipsCodeEmitter::getBranchTargetOpValueMM(const MachineInstr &MI,
                                                    unsigned OpNo) const {
   llvm_unreachable("Unimplemented function.");
   return 0;
 }
 
+unsigned MipsCodeEmitter::getBranchTarget21OpValue(const MachineInstr &MI,
+                                                   unsigned OpNo) const {
+  llvm_unreachable("Unimplemented function.");
+  return 0;
+}
+
+unsigned MipsCodeEmitter::getBranchTarget26OpValue(const MachineInstr &MI,
+                                                   unsigned OpNo) const {
+  llvm_unreachable("Unimplemented function.");
+  return 0;
+}
+
 unsigned MipsCodeEmitter::getBranchTargetOpValue(const MachineInstr &MI,
                                                  unsigned OpNo) const {
   MachineOperand MO = MI.getOperand(OpNo);
   emitMachineBasicBlock(MO.getMBB(), getRelocation(MI, MO));
   return 0;
 }
 
 unsigned MipsCodeEmitter::getMemEncoding(const MachineInstr &MI,

test/MC/Mips/mips32r6/valid.s

 # Instructions that are valid
 #
 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 | FileCheck %s
 
         .set noat
         # FIXME: Add the instructions carried forward from older ISA's
         mul     $2,$3,$4         # CHECK: mul $2, $3, $4   # encoding: [0x00,0x64,0x10,0x98]
         muh     $2,$3,$4         # CHECK: muh $2, $3, $4   # encoding: [0x00,0x64,0x10,0xd8]
         mulu    $2,$3,$4         # CHECK: mulu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x99]
         muhu    $2,$3,$4         # CHECK: muhu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xd9]
+        balc    14572256         # CHECK: balc 14572256    # encoding: [0xe8,0x37,0x96,0xb8]
+        bc      14572256         # CHECK: bc 14572256      # encoding: [0xc8,0x37,0x96,0xb8]
+        beqc    $5, $6, 256      # CHECK: beqc $5, $6, 256 # encoding: [0x20,0xa6,0x00,0x40]
+        bnec    $5, $6, 256      # CHECK: bnec $5, $6, 256 # encoding: [0x60,0xa6,0x00,0x40]
+        beqzc   $5, 72256        # CHECK: beqzc $5, 72256  # encoding: [0xd8,0xa0,0x46,0x90]
+        bnezc   $5, 72256        # CHECK: bnezc $5, 72256  # encoding: [0xf8,0xa0,0x46,0x90]
+        bltzc   $5, 256          # CHECK: bltzc $5, 256    # encoding: [0x5c,0xa5,0x00,0x40]
+        bgezc   $5, 256          # CHECK: bgezc $5, 256    # encoding: [0x58,0xa5,0x00,0x40]
+        blezc   $5, 256          # CHECK: blezc $5, 256    # encoding: [0x58,0x05,0x00,0x40]
+        bgtzc   $5, 256          # CHECK: bgtzc $5, 256    # encoding: [0x5c,0x05,0x00,0x40]

test/MC/Mips/mips64r6/valid.s

 # Instructions that are valid
 #
 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 | FileCheck %s
 
         .set noat
         # FIXME: Add the instructions carried forward from older ISA's
         mul     $2,$3,$4         # CHECK: mul $2, $3, $4   # encoding: [0x00,0x64,0x10,0x98]
         muh     $2,$3,$4         # CHECK: muh $2, $3, $4   # encoding: [0x00,0x64,0x10,0xd8]
         mulu    $2,$3,$4         # CHECK: mulu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x99]
         muhu    $2,$3,$4         # CHECK: muhu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xd9]
         dmul    $2,$3,$4         # CHECK: dmul $2, $3, $4  # encoding: [0x00,0x64,0x10,0xb8]
         dmuh    $2,$3,$4         # CHECK: dmuh $2, $3, $4  # encoding: [0x00,0x64,0x10,0xf8]
         dmulu   $2,$3,$4         # CHECK: dmulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xb9]
         dmuhu   $2,$3,$4         # CHECK: dmuhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xf9]
+        balc    14572256         # CHECK: balc 14572256    # encoding: [0xe8,0x37,0x96,0xb8]
+        bc      14572256         # CHECK: bc 14572256      # encoding: [0xc8,0x37,0x96,0xb8]
+        beqc    $5, $6, 256      # CHECK: beqc $5, $6, 256 # encoding: [0x20,0xa6,0x00,0x40]
+        bnec    $5, $6, 256      # CHECK: bnec $5, $6, 256 # encoding: [0x60,0xa6,0x00,0x40]
+        beqzc   $5, 72256        # CHECK: beqzc $5, 72256  # encoding: [0xd8,0xa0,0x46,0x90]
+        bnezc   $5, 72256        # CHECK: bnezc $5, 72256  # encoding: [0xf8,0xa0,0x46,0x90]
+        bltzc   $5, 256          # CHECK: bltzc $5, 256    # encoding: [0x5c,0xa5,0x00,0x40]
+        bgezc   $5, 256          # CHECK: bgezc $5, 256    # encoding: [0x58,0xa5,0x00,0x40]
+        blezc   $5, 256          # CHECK: blezc $5, 256    # encoding: [0x58,0x05,0x00,0x40]
+        bgtzc   $5, 256          # CHECK: bgtzc $5, 256    # encoding: [0x5c,0x05,0x00,0x40]