Page MenuHomePhabricator

[AArch64] Custom lowering of copysign f16
ClosedPublic

Authored by SjoerdMeijer on Aug 18 2017, 1:28 PM.

Details

Summary

This is a follow up patch of https://reviews.llvm.org/D36396 and introduces custom lowering of copysign f16 to avoid promotions to single precision types when the subtarget supports fullfp16.

Diff Detail

Repository
rL LLVM

Event Timeline

SjoerdMeijer created this revision.Aug 18 2017, 1:28 PM
olista01 added inline comments.Aug 21 2017, 2:24 AM
lib/Target/AArch64/AArch64ISelLowering.cpp
4082 ↗(On Diff #111730)

Why does this need a special case for f16?

4116 ↗(On Diff #111730)

We could also do this for v4f16 and v8f16.

I have removed the special case, and added the vector types.
For the copysign intrinsics working on these vectors, I have not yet added new test cases, because it looks like I first have to first do some work to allow f16 vectors.

Just to clarify my last comment, I will repeat the exercise I did in D36396 allowing f16 scalars, and will now start working on allowing f16 vector types. I will then also add tests for these.

This revision is now accepted and ready to land.Aug 24 2017, 1:52 AM
This revision was automatically updated to reflect the committed changes.