[ARM] Assembler support for the ARMv8.2a dot product instructions

[SjoerdMeijer]

Summary

Commit r310480 added the AArch64 ARMv8.2a dot product instructions, this adds the AArch32 instructions.

[SjoerdMeijer]

Oops, I now see that I forgot to add the disassmbler tests.

[SjoerdMeijer]

Added the disassembler tests.

Note that the AArch32 instructions were added to the an instruction encoding space that has been reclaimed from what was originally allocated for the unused “Coprocessor 13”.
That's why I created a DecoderNamespace CoProc and assigned the coprocessor isntructions to it, otherwise the dot product instructions would get disassembled to coprocessor instructions.

[samparker]

Hi Sjoerd,

Shouldn't the feature be predicated on HasV8_2aOps, not just NEON? It seems weird, from the tests, that we can target arm or thumbv7 but still have access to these instructions.

cheers,
sam

[t.p.northover]

Shouldn't the feature be predicated on HasV8_2aOps, not just NEON? It seems weird, from the tests, that we can target arm or thumbv7 but still have access to these instructions.

They're optional in v8.2a (actually, until I saw the XML I thought they were v8.4) so they need a separate feature. I think those implies fields mostly make sense for the grander features like whole architecture levels; Sjoerd's choice is at least consistent with the FeatureCrypto above.

[SjoerdMeijer]

Hi Sam,
Thanks for reviewing. I agree it looks odd, but the argument of not doing this, is that this is not user-facing. I.e., they are internal options and it's Clang's responsibilities to parse options and set the target features. Other optional instructions/extensions are also not predicated on e.g. v8.1a or v8.2a.

Cheers,
Sjoerd.

[samparker]

Ok, all fair points. LGTM then.

llvm/trunk/lib/Target/ARM/ARM.td

 def FeatureCrypto         : SubtargetFeature<"crypto", "HasCrypto", "true",
                                              "Enable support for "
                                              "Cryptography extensions",
                                              [FeatureNEON]>;
 
 def FeatureCRC            : SubtargetFeature<"crc", "HasCRC", "true",
                                              "Enable support for CRC instructions">;
 
+def FeatureDotProd        : SubtargetFeature<"dotprod", "HasDotProd", "true",
+                                             "Enable support for dot product instructions",
+                                             [FeatureNEON]>;
 
 // Not to be confused with FeatureHasRetAddrStack (return address stack)
 def FeatureRAS            : SubtargetFeature<"ras", "HasRAS", "true",
                                              "Enable Reliability, Availability "
                                              "and Serviceability extensions">;
 
 // Fast computation of non-negative address offsets
 def FeatureFPAO           : SubtargetFeature<"fpao", "HasFPAO", "true",

llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

def HasDPVFP         : Predicate<"!Subtarget->isFPOnlySP()">,
                                  AssemblerPredicate<"!FeatureVFPOnlySP",
                                                     "double precision VFP">;
 def HasFPARMv8       : Predicate<"Subtarget->hasFPARMv8()">,
                                  AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
 def HasNEON          : Predicate<"Subtarget->hasNEON()">,
                                  AssemblerPredicate<"FeatureNEON", "NEON">;
 def HasCrypto        : Predicate<"Subtarget->hasCrypto()">,
                                  AssemblerPredicate<"FeatureCrypto", "crypto">;
+def HasDotProd       : Predicate<"Subtarget->hasDotProd()">,
+                                 AssemblerPredicate<"FeatureDotProd", "dotprod">;
 def HasCRC           : Predicate<"Subtarget->hasCRC()">,
                                  AssemblerPredicate<"FeatureCRC", "crc">;
 def HasRAS           : Predicate<"Subtarget->hasRAS()">,
                                  AssemblerPredicate<"FeatureRAS", "ras">;
 def HasFP16          : Predicate<"Subtarget->hasFP16()">,
                                  AssemblerPredicate<"FeatureFP16","half-float conversions">;
 def HasFullFP16      : Predicate<"Subtarget->hasFullFP16()">,
                                  AssemblerPredicate<"FeatureFullFP16","full half-float">;
def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
 
   let Inst{3-0}   = CRm;
   let Inst{4}     = 0;
   let Inst{7-5}   = opc2;
   let Inst{11-8}  = cop;
   let Inst{15-12} = CRd;
   let Inst{19-16} = CRn;
   let Inst{23-20} = opc1;
+
+  let DecoderNamespace = "CoProc";
 }
 
 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
                c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
                NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
                [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
                               imm:$CRm, imm:$opc2)]>,
                Requires<[IsARM,PreV8]> {
   let Inst{31-28} = 0b1111;
   bits<4> opc1;
   bits<4> CRn;
   bits<4> CRd;
   bits<4> cop;
   bits<3> opc2;
   bits<4> CRm;
 
   let Inst{3-0}   = CRm;
   let Inst{4}     = 0;
   let Inst{7-5}   = opc2;
   let Inst{11-8}  = cop;
   let Inst{15-12} = CRd;
   let Inst{19-16} = CRn;
   let Inst{23-20} = opc1;
+
+  let DecoderNamespace = "CoProc";
 }
 
 class ACI<dag oops, dag iops, string opc, string asm,
             list<dag> pattern, IndexMode im = IndexModeNone>
   : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
       opc, asm, "", pattern> {
   let Inst{27-25} = 0b110;
 }
 class ACInoP<dag oops, dag iops, string opc, string asm,
           list<dag> pattern, IndexMode im = IndexModeNone>
   : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
          opc, asm, "", pattern> {
   let Inst{31-28} = 0b1111;
   let Inst{27-25} = 0b110;
 }
+
+let DecoderNamespace = "CoProc" in {
 multiclass LdStCop<bit load, bit Dbit, string asm, list<dag> pattern> {
   def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
                     asm, "\t$cop, $CRd, $addr", pattern> {
     bits<13> addr;
     bits<4> cop;
     bits<4> CRd;
     let Inst{24} = 1; // P = 1
     let Inst{23} = addr{8};

 defm LDC2  : LdSt2Cop<1, 0, "ldc2", [(int_arm_ldc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>;
 defm LDC2L : LdSt2Cop<1, 1, "ldc2l", [(int_arm_ldc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>;
 
 defm STC   : LdStCop <0, 0, "stc", [(int_arm_stc imm:$cop, imm:$CRd, addrmode5:$addr)]>;
 defm STCL  : LdStCop <0, 1, "stcl", [(int_arm_stcl imm:$cop, imm:$CRd, addrmode5:$addr)]>;
 defm STC2  : LdSt2Cop<0, 0, "stc2", [(int_arm_stc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>;
 defm STC2L : LdSt2Cop<0, 1, "stc2l", [(int_arm_stc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>;
 
+} // DecoderNamespace = "CoProc"
+
 //===----------------------------------------------------------------------===//
 // Move between coprocessor and ARM core register.
 //
 
 class MovRCopro<string opc, bit direction, dag oops, dag iops,
                 list<dag> pattern>
   : ABI<0b1110, oops, iops, NoItinerary, opc,
         "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
   let Inst{20} = direction;
   let Inst{4} = 1;
 
   bits<4> Rt;
   bits<4> cop;
   bits<3> opc1;
   bits<3> opc2;
   bits<4> CRm;
   bits<4> CRn;
 
   let Inst{15-12} = Rt;
   let Inst{11-8}  = cop;
   let Inst{23-21} = opc1;
   let Inst{7-5}   = opc2;
   let Inst{3-0}   = CRm;
   let Inst{19-16} = CRn;
+
+  let DecoderNamespace = "CoProc";
 }
 
 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
                     (outs),
                     (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
                          c_imm:$CRm, imm0_7:$opc2),
                     [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
                                   imm:$CRm, imm:$opc2)]>,
class MovRCopro2<string opc, bit direction, dag oops, dag iops,
   bits<4> CRn;
 
   let Inst{15-12} = Rt;
   let Inst{11-8}  = cop;
   let Inst{23-21} = opc1;
   let Inst{7-5}   = opc2;
   let Inst{3-0}   = CRm;
   let Inst{19-16} = CRn;
+
+  let DecoderNamespace = "CoProc";
 }
 
 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
                       (outs),
                       (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
                            c_imm:$CRm, imm0_7:$opc2),
                       [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
                                      imm:$CRm, imm:$opc2)]>,

llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

def : Pat<(v4f32 (fma QPR:$Vn, QPR:$Vm, QPR:$src1)),
           Requires<[HasVFP4]>;
 def : Pat<(v2f32 (fma (fneg DPR:$Vn), DPR:$Vm, DPR:$src1)),
           (VFMSfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
       Requires<[HasVFP4]>;
 def : Pat<(v4f32 (fma (fneg QPR:$Vn), QPR:$Vm, QPR:$src1)),
           (VFMSfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
       Requires<[HasVFP4]>;
 
+// ARMv8.2a dot product instructions.
+// We put them in the VFPV8 decoder namespace because the ARM and Thumb
+// encodings are the same and thus no further bit twiddling is necessary
+// in the disassembler.
+let Predicates = [HasDotProd], DecoderNamespace = "VFPV8" in {
+
+def VUDOTD : N3Vnp<0b11000, 0b10, 0b1101, 0b0, 0b1,
+                  (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm),
+                  N3RegFrm, IIC_VDOTPROD, "vudot", "u8", []>;
+def VSDOTD : N3Vnp<0b11000, 0b10, 0b1101, 0b0, 0b0,
+                  (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm),
+                  N3RegFrm, IIC_VDOTPROD, "vsdot", "s8", []>;
+def VUDOTQ : N3Vnp<0b11000, 0b10, 0b1101, 0b1, 0b1,
+                  (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm),
+                  N3RegFrm, IIC_VDOTPROD, "vudot", "u8", []>;
+def VSDOTQ : N3Vnp<0b11000, 0b10, 0b1101, 0b1, 0b0,
+                  (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm),
+                  N3RegFrm, IIC_VDOTPROD, "vsdot", "s8", []>;
+
+// Indexed dot product instructions:
+class DOTI<string opc, string dt, bit Q, bit U, RegisterClass Ty> :
+  N3Vnp<0b11100, 0b10, 0b1101, Q, U,
+       (outs Ty:$Vd), (ins Ty:$Vn, DPR:$Vm, VectorIndex32:$lane),
+       N3RegFrm, IIC_VDOTPROD, opc, dt, []> {
+  bit lane;
+  let Inst{5} = lane;
+  let AsmString = !strconcat(opc, ".", dt, "\t$Vd, $Vn, $Vm$lane");
+}
+
+def VUDOTDI : DOTI<"vudot", "u8", 0b0, 0b1, DPR>;
+def VSDOTDI : DOTI<"vsdot", "s8", 0b0, 0b0, DPR>;
+def VUDOTQI : DOTI<"vudot", "u8", 0b1, 0b1, QPR>;
+def VSDOTQI : DOTI<"vsdot", "s8", 0b1, 0b0, QPR>;
+
+}  // HasDotProd
+
 // Vector Subtract Operations.
 
 //   VSUB     : Vector Subtract (integer and floating-point)
 defm VSUB     : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
                          "vsub", "i", sub, 0>;
 def  VSUBfd   : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
                      v2f32, v2f32, fsub, 0>;
 def  VSUBfq   : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",

llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

def _OPTION : T2CI<op31_28, (outs),
     let Inst{19-16} = addr;
     let Inst{15-12} = CRd;
     let Inst{11-8} = cop;
     let Inst{7-0} = option;
     let DecoderMethod = "DecodeCopMemInstruction";
   }
 }
 
+let DecoderNamespace = "Thumb2CoProc" in {
 defm t2LDC   : t2LdStCop<0b1110, 1, 0, "ldc", [(int_arm_ldc imm:$cop, imm:$CRd, addrmode5:$addr)]>;
 defm t2LDCL  : t2LdStCop<0b1110, 1, 1, "ldcl", [(int_arm_ldcl imm:$cop, imm:$CRd, addrmode5:$addr)]>;
 defm t2LDC2  : t2LdStCop<0b1111, 1, 0, "ldc2", [(int_arm_ldc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
 defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l", [(int_arm_ldc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
 
 defm t2STC   : t2LdStCop<0b1110, 0, 0, "stc", [(int_arm_stc imm:$cop, imm:$CRd, addrmode5:$addr)]>;
 defm t2STCL  : t2LdStCop<0b1110, 0, 1, "stcl", [(int_arm_stcl imm:$cop, imm:$CRd, addrmode5:$addr)]>;
 defm t2STC2  : t2LdStCop<0b1111, 0, 0, "stc2", [(int_arm_stc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
 defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l", [(int_arm_stc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
+}
 
 
 //===----------------------------------------------------------------------===//
 // Move between special register and ARM core register -- for disassembly only
 //
 // Move to ARM core register from Special Register
 
 // A/R class MRS.
class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
   bits<4> CRn;
 
   let Inst{15-12} = Rt;
   let Inst{11-8}  = cop;
   let Inst{23-21} = opc1;
   let Inst{7-5}   = opc2;
   let Inst{3-0}   = CRm;
   let Inst{19-16} = CRn;
+
+  let DecoderNamespace = "Thumb2CoProc";
 }
 
 class t2MovRRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
                    list<dag> pattern = []>
   : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
   let Inst{27-24} = 0b1100;
   let Inst{23-21} = 0b010;
   let Inst{20} = direction;
 
   bits<4> Rt;
   bits<4> Rt2;
   bits<4> cop;
   bits<4> opc1;
   bits<4> CRm;
 
   let Inst{15-12} = Rt;
   let Inst{19-16} = Rt2;
   let Inst{11-8}  = cop;
   let Inst{7-4}   = opc1;
   let Inst{3-0}   = CRm;
+
+  let DecoderNamespace = "Thumb2CoProc";
 }
 
 /* from ARM core register to coprocessor */
 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
            (outs),
            (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
                 c_imm:$CRm, imm0_7:$opc2),
            [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
def t2CDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
   let Inst{4}     = 0;
   let Inst{7-5}   = opc2;
   let Inst{11-8}  = cop;
   let Inst{15-12} = CRd;
   let Inst{19-16} = CRn;
   let Inst{23-20} = opc1;
 
   let Predicates = [IsThumb2, PreV8];
+  let DecoderNamespace = "Thumb2CoProc";
 }
 
 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
                    c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
                    "cdp2", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
                    [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
                                   imm:$CRm, imm:$opc2)]> {
   let Inst{27-24} = 0b1110;
def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
   let Inst{4}     = 0;
   let Inst{7-5}   = opc2;
   let Inst{11-8}  = cop;
   let Inst{15-12} = CRd;
   let Inst{19-16} = CRn;
   let Inst{23-20} = opc1;
 
   let Predicates = [IsThumb2, PreV8];
+  let DecoderNamespace = "Thumb2CoProc";
 }
 
 
 
 //===----------------------------------------------------------------------===//
 // ARMv8.1 Privilege Access Never extension
 //
 // SETPAN #imm1

llvm/trunk/lib/Target/ARM/ARMSchedule.td

 def IIC_VTB1       : InstrItinClass;
 def IIC_VTB2       : InstrItinClass;
 def IIC_VTB3       : InstrItinClass;
 def IIC_VTB4       : InstrItinClass;
 def IIC_VTBX1      : InstrItinClass;
 def IIC_VTBX2      : InstrItinClass;
 def IIC_VTBX3      : InstrItinClass;
 def IIC_VTBX4      : InstrItinClass;
+def IIC_VDOTPROD   : InstrItinClass;
 
 //===----------------------------------------------------------------------===//
 // Processor instruction itineraries.
 
 include "ARMScheduleV6.td"
 include "ARMScheduleA8.td"
 include "ARMScheduleA9.td"
 include "ARMScheduleSwift.td"
 include "ARMScheduleR52.td"
 include "ARMScheduleA57.td"
 include "ARMScheduleM3.td"

llvm/trunk/lib/Target/ARM/ARMSubtarget.h

protected:
   /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
   /// floating point ISAs are supported.
   bool HasVFPv2 = false;
   bool HasVFPv3 = false;
   bool HasVFPv4 = false;
   bool HasFPARMv8 = false;
   bool HasNEON = false;
 
+  /// HasDotProd - True if the ARMv8.2A dot product instructions are supported.
+  bool HasDotProd = false;
+
   /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
   /// specified. Use the method useNEONForSinglePrecisionFP() to
   /// determine if NEON should actually be used.
   bool UseNEONForSinglePrecisionFP = false;
 
   /// UseMulOps - True if non-microcoded fused integer multiply-add and
   /// multiply-subtract instructions should be used.
   bool UseMulOps = false;
public:
   bool hasARMOps() const { return !NoARM; }
 
   bool hasVFP2() const { return HasVFPv2; }
   bool hasVFP3() const { return HasVFPv3; }
   bool hasVFP4() const { return HasVFPv4; }
   bool hasFPARMv8() const { return HasFPARMv8; }
   bool hasNEON() const { return HasNEON;  }
   bool hasCrypto() const { return HasCrypto; }
+  bool hasDotProd() const { return HasDotProd; }
   bool hasCRC() const { return HasCRC; }
   bool hasRAS() const { return HasRAS; }
   bool hasVirtualization() const { return HasVirtualization; }
 
   bool useNEONForSinglePrecisionFP() const {
     return hasNEON() && UseNEONForSinglePrecisionFP;
   }
 

llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

if ((Mnemonic == "movs" && isThumb()) ||
       Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
       Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
       Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
       Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
       Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
       Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
       Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
       Mnemonic.startswith("vsel") || Mnemonic == "vins" || Mnemonic == "vmovx" ||
-      Mnemonic == "bxns"  || Mnemonic == "blxns")
+      Mnemonic == "bxns"  || Mnemonic == "blxns" ||
+      Mnemonic == "vudot" || Mnemonic == "vsdot")
     return Mnemonic;
 
   // First, split out any predication code. Ignore mnemonics we know aren't
   // predicated but do have a carry-set and so weren't caught above.
   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
       Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
       Mnemonic != "sbcs" && Mnemonic != "rscs") {
if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
       Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
       Mnemonic.startswith("vsel") || Mnemonic == "vmaxnm" ||
       Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" ||
       Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" ||
       Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" ||
       Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" ||
       Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
       (FullInst.startswith("vmull") && FullInst.endswith(".p64")) ||
-      Mnemonic == "vmovx" || Mnemonic == "vins") {
+      Mnemonic == "vmovx" || Mnemonic == "vins" ||
+      Mnemonic == "vudot" || Mnemonic == "vsdot") {
     // These mnemonics are never predicable
     CanAcceptPredicationCode = false;
   } else if (!isThumb()) {
     // Some instructions are only predicable in Thumb mode
     CanAcceptPredicationCode =
         Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
         Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
         Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&

llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

if (Result != MCDisassembler::Fail) {
       // Add a fake predicate operand, because we share these instruction
       // definitions with Thumb2 where these instructions are predicable.
       if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this))
         return MCDisassembler::Fail;
       return Result;
     }
   }
 
+  Result =
+      decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
+  if (Result != MCDisassembler::Fail) {
+    Size = 4;
+    return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
+  }
+
   Size = 4;
   return MCDisassembler::Fail;
 }
 
 namespace llvm {
 
 extern const MCInstrDesc ARMInsts[];
 
if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
     Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
                                this, STI);
     if (Result != MCDisassembler::Fail) {
       Size = 4;
       return Result;
     }
   }
 
+  Result =
+      decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI);
+  if (Result != MCDisassembler::Fail) {
+    Size = 4;
+    Check(Result, AddThumbPredicate(MI));
+    return Result;
+  }
+
   Size = 0;
   return MCDisassembler::Fail;
 }
 
 extern "C" void LLVMInitializeARMDisassembler() {
   TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(),
                                          createARMDisassembler);
   TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(),

llvm/trunk/test/MC/ARM/armv8.2a-dotprod-a32.s

+// RUN: llvm-mc -triple arm -mattr=+dotprod -show-encoding < %s | FileCheck %s  --check-prefix=CHECK
+
+// RUN: not llvm-mc -triple arm -mattr=-dotprod -show-encoding < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
+// RUN: not llvm-mc -triple arm -show-encoding < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
+// RUN: not llvm-mc -triple arm -mattr=+v8.1a -show-encoding < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
+// RUN: not llvm-mc -triple arm -mattr=+v8.2a -show-encoding < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
+
+vudot.u8 d0, d1, d2
+vsdot.s8 d0, d1, d2
+vudot.u8 q0, q1, q4
+vsdot.s8 q0, q1, q4
+vudot.u8 d0, d1, d2[0]
+vsdot.s8 d0, d1, d2[1]
+vudot.u8 q0, q1, d4[0]
+vsdot.s8 q0, q1, d4[1]
+
+// CHECK: vudot.u8  d0, d1, d2      @ encoding: [0x12,0x0d,0x21,0xfc]
+// CHECK: vsdot.s8  d0, d1, d2      @ encoding: [0x02,0x0d,0x21,0xfc]
+// CHECK: vudot.u8  q0, q1, q4      @ encoding: [0x58,0x0d,0x22,0xfc]
+// CHECK: vsdot.s8  q0, q1, q4      @ encoding: [0x48,0x0d,0x22,0xfc]
+// CHECK: vudot.u8  d0, d1, d2[0]   @ encoding: [0x12,0x0d,0x21,0xfe]
+// CHECK: vsdot.s8  d0, d1, d2[1]   @ encoding: [0x22,0x0d,0x21,0xfe]
+// CHECK: vudot.u8  q0, q1, d4[0]   @ encoding: [0x54,0x0d,0x22,0xfe]
+// CHECK: vsdot.s8  q0, q1, d4[1]   @ encoding: [0x64,0x0d,0x22,0xfe]
+
+// CHECK-NO-DOTPROD: error: instruction requires: dotprod
+// CHECK-NO-DOTPROD: error: instruction requires: dotprod
+// CHECK-NO-DOTPROD: error: instruction requires: dotprod
+// CHECK-NO-DOTPROD: error: instruction requires: dotprod
+// CHECK-NO-DOTPROD: error: instruction requires: dotprod
+// CHECK-NO-DOTPROD: error: instruction requires: dotprod
+// CHECK-NO-DOTPROD: error: instruction requires: dotprod
+// CHECK-NO-DOTPROD: error: instruction requires: dotprod

llvm/trunk/test/MC/ARM/armv8.2a-dotprod-error.s

+// RUN: not llvm-mc -triple arm -mattr=+dotprod -show-encoding < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
+// RUN: not llvm-mc -triple thumb -mattr=+dotprod -show-encoding < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
+
+vudot.u8 d0, d1, d2[2]
+vsdot.s8 d0, d1, d2[2]
+vudot.u8 q0, q1, d4[2]
+vsdot.s8 q0, q1, d4[2]
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: error: invalid operand for instruction

llvm/trunk/test/MC/ARM/armv8.2a-dotprod-t32.s

+// RUN: llvm-mc -triple thumb -mattr=+dotprod -show-encoding < %s | FileCheck %s  --check-prefix=CHECK
+
+// RUN: not llvm-mc -triple thumb -mattr=-dotprod -show-encoding < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
+// RUN: not llvm-mc -triple thumb -show-encoding < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
+// RUN: not llvm-mc -triple thumb -mattr=+v8.1a -show-encoding < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
+// RUN: not llvm-mc -triple thumb -mattr=+v8.2a -show-encoding < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
+
+  vudot.u8  d0, d1, d2
+  vsdot.s8  d0, d1, d2
+  vudot.u8  q0, q1, q4
+  vsdot.s8  q0, q1, q4
+  vudot.u8  d0, d1, d2[0]
+  vsdot.s8  d0, d1, d2[1]
+  vudot.u8  q0, q1, d4[0]
+  vsdot.s8  q0, q1, d4[1]
+
+//CHECK:  vudot.u8  d0, d1, d2      @ encoding: [0x21,0xfc,0x12,0x0d]
+//CHECK:  vsdot.s8  d0, d1, d2      @ encoding: [0x21,0xfc,0x02,0x0d]
+//CHECK:  vudot.u8  q0, q1, q4      @ encoding: [0x22,0xfc,0x58,0x0d]
+//CHECK:  vsdot.s8  q0, q1, q4      @ encoding: [0x22,0xfc,0x48,0x0d]
+//CHECK:  vudot.u8  d0, d1, d2[0]   @ encoding: [0x21,0xfe,0x12,0x0d]
+//CHECK:  vsdot.s8  d0, d1, d2[1]   @ encoding: [0x21,0xfe,0x22,0x0d]
+//CHECK:  vudot.u8  q0, q1, d4[0]   @ encoding: [0x22,0xfe,0x54,0x0d]
+//CHECK:  vsdot.s8  q0, q1, d4[1]   @ encoding: [0x22,0xfe,0x64,0x0d]
+
+//CHECK-ERROR: error: instruction requires: dotprod
+//CHECK-ERROR: error: instruction requires: dotprod
+//CHECK-ERROR: error: instruction requires: dotprod
+//CHECK-ERROR: error: instruction requires: dotprod
+//CHECK-ERROR: error: instruction requires: dotprod
+//CHECK-ERROR: error: instruction requires: dotprod
+//CHECK-ERROR: error: instruction requires: dotprod
+//CHECK-ERROR: error: instruction requires: dotprod
+

llvm/trunk/test/MC/Disassembler/ARM/armv8.2a-dotprod-a32.s

+# RUN: llvm-mc -triple arm-none-linux-gnu -mattr=+dotprod --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple arm-none-linux-gnu -mattr=-dotprod --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+
+0x12,0x0d,0x21,0xfc
+0x02,0x0d,0x21,0xfc
+0x58,0x0d,0x22,0xfc
+0x48,0x0d,0x22,0xfc
+0x12,0x0d,0x21,0xfe
+0x22,0x0d,0x21,0xfe
+0x54,0x0d,0x22,0xfe
+0x64,0x0d,0x22,0xfe
+
+#CHECK: vudot.u8  d0, d1, d2
+#CHECK: vsdot.s8  d0, d1, d2
+#CHECK: vudot.u8  q0, q1, q4
+#CHECK: vsdot.s8  q0, q1, q4
+#CHECK: vudot.u8  d0, d1, d2[0]
+#CHECK: vsdot.s8  d0, d1, d2[1]
+#CHECK: vudot.u8  q0, q1, d4[0]
+#CHECK: vsdot.s8  q0, q1, d4[1]
+
+# without dot product enabled, the instructions get disassembled to these
+# coprocessor instructions:
+
+#CHECK-ERROR: stc2  p13, c0, [r1], #-72
+#CHECK-ERROR: stc2  p13, c0, [r1], #-8
+#CHECK-ERROR: stc2  p13, c0, [r2], #-352
+#CHECK-ERROR: stc2  p13, c0, [r2], #-288
+#CHECK-ERROR: mcr2  p13, #1, r0, c1, c2, #0
+#CHECK-ERROR: cdp2  p13, #2, c0, c1, c2, #1
+#CHECK-ERROR: mcr2  p13, #1, r0, c2, c4, #2
+#CHECK-ERROR: cdp2  p13, #2, c0, c2, c4, #3
+

llvm/trunk/test/MC/Disassembler/ARM/armv8.2a-dotprod-t32.s

+# RUN: llvm-mc -triple thumbv7a -mattr=+dotprod --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple thumbv7a -mattr=-dotprod --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+
+[0x21,0xfc,0x12,0x0d]
+[0x21,0xfc,0x02,0x0d]
+[0x22,0xfc,0x58,0x0d]
+[0x22,0xfc,0x48,0x0d]
+[0x21,0xfe,0x12,0x0d]
+[0x21,0xfe,0x22,0x0d]
+[0x22,0xfe,0x54,0x0d]
+[0x22,0xfe,0x64,0x0d]
+
+#CHECK: vudot.u8  d0, d1, d2
+#CHECK: vsdot.s8  d0, d1, d2
+#CHECK: vudot.u8  q0, q1, q4
+#CHECK: vsdot.s8  q0, q1, q4
+#CHECK: vudot.u8  d0, d1, d2[0]
+#CHECK: vsdot.s8  d0, d1, d2[1]
+#CHECK: vudot.u8  q0, q1, d4[0]
+#CHECK: vsdot.s8  q0, q1, d4[1]
+
+#CHECK-ERROR:  stc2  p13, c0, [r1], #-72
+#CHECK-ERROR:  stc2  p13, c0, [r1], #-8
+#CHECK-ERROR:  stc2  p13, c0, [r2], #-352
+#CHECK-ERROR:  stc2  p13, c0, [r2], #-288
+#CHECK-ERROR:  mcr2  p13, #1, r0, c1, c2, #0
+#CHECK-ERROR:  cdp2  p13, #2, c0, c1, c2, #1
+#CHECK-ERROR:  mcr2  p13, #1, r0, c2, c4, #2
+#CHECK-ERROR:  cdp2  p13, #2, c0, c2, c4, #3