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Differential D36293

AMDGPU: Look through copies for immediates
AbandonedPublic

Authored by arsenm on Aug 3 2017, 4:11 PM.

Details

Reviewers
tstellar
rampitec

Diff Detail

Event Timeline

arsenm created this revision.Aug 3 2017, 4:11 PM
Herald added subscribers: t-tye, tpr, dstuttard and 4 others. · View Herald TranscriptAug 3 2017, 4:11 PM
arsenm added a parent revision: D36292: AMDGPU: Add pass to cleanup DAG SALU/VALU messes.Aug 3 2017, 4:11 PM
rampitec accepted this revision.Aug 3 2017, 9:02 PM

LGTM

This revision is now accepted and ready to land.Aug 3 2017, 9:02 PM
arsenm abandoned this revision.Apr 4 2020, 6:27 PM
Herald added subscribers: kerbowa, jvesely. · View Herald TranscriptApr 4 2020, 6:27 PM

Revision Contents

PathSize
lib/
Target/
AMDGPU/
12 lines
test/
CodeGen/
AMDGPU/
3 lines

Diff 109650

lib/Target/AMDGPU/SIInstrInfo.cpp

Show First 20 Lines • Show All 4,374 Lines • ▼ Show 20 Linesbool SIInstrInfo::isImmOrMaterializedImm(const MachineRegisterInfo &MRI,
uint64_t &Imm) { uint64_t &Imm) {
if (Op.isImm()) { if (Op.isImm()) {
Imm = Op.getImm(); Imm = Op.getImm();
return true; return true;
} }
if (Op.isReg()) { if (Op.isReg()) {
const MachineInstr *Def = MRI.getUniqueVRegDef(Op.getReg()); const MachineInstr *Def = MRI.getUniqueVRegDef(Op.getReg());
if (!Def || !Def->isMoveImmediate()) if (!Def)
return false;
if (!Def->isMoveImmediate()) {
if (Def->isCopy()) {
// Sometimes extra copies are inserted from SGPRs to VGPRs to satisfy
// operand constraints.
return isImmOrMaterializedImm(MRI, Def->getOperand(1), Imm);
}
return false; return false;
}
const MachineOperand &Src = Def->getOperand(1); const MachineOperand &Src = Def->getOperand(1);
if (Src.isImm()) { if (Src.isImm()) {
Imm = Src.getImm(); Imm = Src.getImm();
return true; return true;
} }
return false; return false;
▲ Show 20 Lines • Show All 172 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/lshr.v2i16.ll

Show All 32 Lines
; CI: s_mov_b32 [[MASK:s[0-9]+]], 0xffff{{$}} ; CI: s_mov_b32 [[MASK:s[0-9]+]], 0xffff{{$}}
; CI-DAG: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, [[LHS]] ; CI-DAG: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, [[LHS]]
; CI-DAG: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, [[RHS]] ; CI-DAG: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, [[RHS]]
; CI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}} ; CI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}}
; CI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}} ; CI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}}
; CI: v_bfe_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, 16 ; CI: v_bfe_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, 16
; CI: v_lshrrev_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; CI: v_lshrrev_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; CI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}} ; CI: v_cvt_pk_u16_u32
; CI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @v_lshr_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { define amdgpu_kernel void @v_lshr_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
%out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
%b_ptr = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %in.gep, i32 1 %b_ptr = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %in.gep, i32 1
%a = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep %a = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
%b = load <2 x i16>, <2 x i16> addrspace(1)* %b_ptr %b = load <2 x i16>, <2 x i16> addrspace(1)* %b_ptr
▲ Show 20 Lines • Show All 102 Lines • Show Last 20 Lines