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[AMDGPU][MC][GFX9] Added support of VOP3 'op_sel' modifier
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Authored by dp on Jul 14 2017, 11:00 AM.

Details

Summary

See bug 33591: https://bugs.llvm.org//show_bug.cgi?id=33591

VOP3 op_sel modifier may be used to select low or high 16 bits of src operands.
In contrast with VOP3P, it is also possible to specify where to save the result.

The syntax of op_sel modifier for VOP3 is:

op_sel:[src0, src1, dst] for 2-operand instructions

or

op_sel:[src0, src1, src2, dst] for 3-operand instructions

The op_sel list may be shorter or longer than required.
Missing elements are assumed to be 0, excessive elements are ignored.

For example, opcode

v_add_i16 v5, v1, v2 op_sel:[0,0,1]

implements the following operation:

v5[31:16] = v_add_i16(v1[15:0], v2[15:0])

op_sel elements are meaningless for 32-bit src/dst operands and should be 0.
For example,

v_pack_b32_f16 v5, v1, v2 op_sel:[1,1,1]

is not legal because dst size is 32 bits.
Currently this is not verified but a check may be added in the future.

op_sel modifier for srcX operand is encoded in srcX_modifiers the same way as it is implemented for VOP3P.
op_sel modifier for dst operand is encoded in src0_modifiers.

Postponed features:

  • validation of op_sel length;
  • validation of op_sel elements for 32-bit operands/destination;
  • validation of 'clamp' which should not be allowed for bit-type dst;
  • support of op_sel for gfx8 opcodes which have subtle changes in gfx9 (see bug 33629: https://bugs.llvm.org//show_bug.cgi?id=33629).

NB: changes in generated tests for assembler and disassembler are not included in the diff because of too large size.

Diff Detail

Event Timeline

dp created this revision.Jul 14 2017, 11:00 AM
dp edited the summary of this revision. (Show Details)Jul 14 2017, 11:21 AM
dp edited the summary of this revision. (Show Details)Jul 14 2017, 12:51 PM
This revision is now accepted and ready to land.Jul 17 2017, 7:44 AM
This revision was automatically updated to reflect the committed changes.