[ARM] Add .w aliases of MOV with shifted operand

[john.brawn]

Summary

These appear to have been simply missing.

[SjoerdMeijer]

Looks good to me.

lib/Target/ARM/ARMInstrThumb2.td

 def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift",
                           (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
 
 def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift",
                          (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
 def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift",
                           (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
 
+// Aliases for the above with the .w qualifier
+def : t2InstAlias<"mov${p}.w $Rd, $shift",
+                  (t2MOVsi rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
+def : t2InstAlias<"movs${p}.w $Rd, $shift",
+                  (t2MOVSsi rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
+def : t2InstAlias<"mov${p}.w $Rd, $shift",
+                  (t2MOVsr rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
+def : t2InstAlias<"movs${p}.w $Rd, $shift",
+                  (t2MOVSsr rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
+
 // ADR w/o the .w suffix
 def : t2InstAlias<"adr${p} $Rd, $addr",
                   (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>;
 
 // LDR(literal) w/ alternate [pc, #imm] syntax.
 def t2LDRpcrel   : t2AsmPseudo<"ldr${p} $Rt, $addr",
                          (ins GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
 def t2LDRBpcrel  : t2AsmPseudo<"ldrb${p} $Rt, $addr",

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

case ARM::t2MOVSsr: {
     // Which instruction to expand to depends on the CCOut operand and
     // whether we're in an IT block if the register operands are low
     // registers.
     bool isNarrow = false;
     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
         isARMLowRegister(Inst.getOperand(1).getReg()) &&
         isARMLowRegister(Inst.getOperand(2).getReg()) &&
         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
-        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
+        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr) &&
+        !HasWideQualifier)
       isNarrow = true;
     MCInst TmpInst;
     unsigned newOpc;
     switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
     default: llvm_unreachable("unexpected opcode!");
     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;

   case ARM::t2MOVsi:
   case ARM::t2MOVSsi: {
     // Which instruction to expand to depends on the CCOut operand and
     // whether we're in an IT block if the register operands are low
     // registers.
     bool isNarrow = false;
     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
         isARMLowRegister(Inst.getOperand(1).getReg()) &&
-        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
+        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi) &&
+        !HasWideQualifier)
       isNarrow = true;
     MCInst TmpInst;
     unsigned newOpc;
     unsigned Shift = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
     unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
     bool isMov = false;
     // MOV rd, rm, LSL #0 is actually a MOV instruction
     if (Shift == ARM_AM::lsl && Amount == 0) {

test/MC/ARM/basic-thumb2-instructions.s

 @ CHECK: itt    eq                      @ encoding: [0x04,0xbf]
 @ CHECK: moveq  r0, #255                @ encoding: [0xff,0x20]
 @ CHECK: movweq r1, #256                @ encoding: [0x40,0xf2,0x00,0x11]
 
 @------------------------------------------------------------------------------
 @ MOV(shifted register)
 @------------------------------------------------------------------------------
         mov r6, r2, lsl #16
+        mov.w r6, r2, lsl #16
         mov r6, r2, lsr #16
+        mov.w r6, r2, lsr #16
         movs r6, r2, asr #32
+        movs.w r6, r2, asr #32
         movs r6, r2, ror #5
+        movs.w r6, r2, ror #5
         movs r4, r4, lsl r5
+        movs.w r4, r4, lsl r5
         movs r4, r4, lsr r5
+        movs.w r4, r4, lsr r5
         movs r4, r4, asr r5
+        movs.w r4, r4, asr r5
         movs r4, r4, ror r5
+        movs.w r4, r4, ror r5
         mov r4, r4, lsl r5
         movs r4, r4, ror r8
         movs r4, r5, lsr r6
         itttt eq
         moveq r4, r4, lsl r5
         moveq r4, r4, lsr r5
         moveq r4, r4, asr r5
         moveq r4, r4, ror r5
         mov r4, r4, rrx
 
 @ CHECK: lsl.w  r6, r2, #16             @ encoding: [0x4f,0xea,0x02,0x46]
+@ CHECK: lsl.w  r6, r2, #16             @ encoding: [0x4f,0xea,0x02,0x46]
+@ CHECK: lsr.w  r6, r2, #16             @ encoding: [0x4f,0xea,0x12,0x46]
 @ CHECK: lsr.w  r6, r2, #16             @ encoding: [0x4f,0xea,0x12,0x46]
 @ CHECK: asrs  r6, r2, #32             @ encoding: [0x16,0x10]
+@ CHECK: asrs.w  r6, r2, #32             @ encoding: [0x5f,0xea,0x22,0x06]
+@ CHECK: rors.w  r6, r2, #5              @ encoding: [0x5f,0xea,0x72,0x16]
 @ CHECK: rors.w  r6, r2, #5              @ encoding: [0x5f,0xea,0x72,0x16]
 @ CHECK: lsls  r4, r5                  @ encoding: [0xac,0x40]
+@ CHECK: lsls.w  r4, r4, r5              @ encoding: [0x14,0xfa,0x05,0xf4]
 @ CHECK: lsrs  r4, r5                  @ encoding: [0xec,0x40]
+@ CHECK: lsrs.w  r4, r4, r5              @ encoding: [0x34,0xfa,0x05,0xf4]
 @ CHECK: asrs  r4, r5                  @ encoding: [0x2c,0x41]
+@ CHECK: asrs.w  r4, r4, r5              @ encoding: [0x54,0xfa,0x05,0xf4]
 @ CHECK: rors  r4, r5                  @ encoding: [0xec,0x41]
+@ CHECK: rors.w  r4, r4, r5              @ encoding: [0x74,0xfa,0x05,0xf4]
 @ CHECK: lsl.w  r4, r4, r5              @ encoding: [0x04,0xfa,0x05,0xf4]
 @ CHECK: rors.w  r4, r4, r8              @ encoding: [0x74,0xfa,0x08,0xf4]
 @ CHECK: lsrs.w  r4, r5, r6              @ encoding: [0x35,0xfa,0x06,0xf4]
 @ CHECK: itttt  eq                      @ encoding: [0x01,0xbf]
 @ CHECK: lsleq  r4, r5                  @ encoding: [0xac,0x40]
 @ CHECK: lsreq  r4, r5                  @ encoding: [0xec,0x40]
 @ CHECK: asreq  r4, r5                  @ encoding: [0x2c,0x41]
 @ CHECK: roreq  r4, r5                  @ encoding: [0xec,0x41]