MachineVerifier: Verify liveins list

[MatzeB]

Summary

• Make sure that at the end of basic blocks the liveins of the successor blocks are live (or the CSRs in case of return blocks).
• Do not allow reserved registers in livein lists, they are unnecessary.
• Do not allow pristine registers in livein lists, they are unnecessary.

[MatzeB]

This is a preview. I am currently cleaning the aarch64 backend for these stricter verifier rules. Esp. the first one is worth putting into LLVM. The 2nd and 3rd can be debated as they aren't technically wrong, though often hint at bad code.

[kparzysz]

I don't think we should be aborting on legal code. Maybe we should add an option to treat all verifier reports as warnings (i.e. continue the compilation even if issues were reported)?

Also, didn't you want to eventually get rid of the concept of pristine registers? Doing that would require the opposite---having them as live-ins almost everywhere. Is this patch meant as a short-term solution?

[MatzeB]

In D33650#767962, @kparzysz wrote:

I don't think we should be aborting on legal code. Maybe we should add an option to treat all verifier reports as warnings (i.e. continue the compilation even if issues were reported)?

Also, didn't you want to eventually get rid of the concept of pristine registers? Doing that would require the opposite---having them as live-ins almost everywhere. Is this patch meant as a short-term solution?

Well if we remove the concept we remove the verifier check with it, that's easy :)
So far however seeing pristine registers in livein lists was a good smell for bad code.

[MatzeB]

In D33650#767962, @kparzysz wrote:

I don't think we should be aborting on legal code. Maybe we should add an option to treat all verifier reports as warnings (i.e. continue the compilation even if issues were reported)?

Well looking at the existing situation with targets, we probably have to keep the pristine/reserved checks separate. Just looking at the liveness check currently fails a bunch of lit tests for me:

LLVM :: CodeGen/ARM/2010-05-18-LocalAllocCrash.ll
LLVM :: CodeGen/ARM/2011-04-12-FastRegAlloc.ll
LLVM :: CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll
LLVM :: CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll
LLVM :: CodeGen/ARM/ARMLoadStoreDBG.mir
LLVM :: CodeGen/ARM/Windows/dbzchk.ll
LLVM :: CodeGen/ARM/Windows/no-aeabi.ll
LLVM :: CodeGen/ARM/atomic-cmpxchg.ll
LLVM :: CodeGen/ARM/atomic-load-store.ll
LLVM :: CodeGen/ARM/atomic-op.ll
LLVM :: CodeGen/ARM/atomic-ops-v8.ll
LLVM :: CodeGen/ARM/cmpxchg-O0.ll
LLVM :: CodeGen/ARM/coalesce-dbgvalue.ll
LLVM :: CodeGen/ARM/coalesce-subregs.ll
LLVM :: CodeGen/ARM/copy-paired-reg.ll
LLVM :: CodeGen/ARM/crash-greedy.ll
LLVM :: CodeGen/ARM/domain-conv-vmovs.ll
LLVM :: CodeGen/ARM/fast-isel-br-const.ll
LLVM :: CodeGen/ARM/fast-isel-br-phi.ll
LLVM :: CodeGen/ARM/fast-isel-call-multi-reg-return.ll
LLVM :: CodeGen/ARM/fast-isel-call.ll
LLVM :: CodeGen/ARM/fast-isel-cmp-imm.ll
LLVM :: CodeGen/ARM/fast-isel-conversion.ll
LLVM :: CodeGen/ARM/fast-isel-crash.ll
LLVM :: CodeGen/ARM/fast-isel-deadcode.ll
LLVM :: CodeGen/ARM/fast-isel-fold.ll
LLVM :: CodeGen/ARM/fast-isel-frameaddr.ll
LLVM :: CodeGen/ARM/fast-isel-intrinsic.ll
LLVM :: CodeGen/ARM/fast-isel-mvn.ll
LLVM :: CodeGen/ARM/fast-isel-pred.ll
LLVM :: CodeGen/ARM/fast-isel-static.ll
LLVM :: CodeGen/ARM/fast-isel-update-valuemap-for-extract.ll
LLVM :: CodeGen/ARM/fast-isel-vaddd.ll
LLVM :: CodeGen/ARM/fast-isel-vararg.ll
LLVM :: CodeGen/ARM/fast-isel.ll
LLVM :: CodeGen/ARM/func-argpassing-endian.ll
LLVM :: CodeGen/ARM/gpr-paired-spill.ll
LLVM :: CodeGen/ARM/ifconv-kills.ll
LLVM :: CodeGen/ARM/ifcvt-dead-def.ll
LLVM :: CodeGen/ARM/inlineasm-64bit.ll
LLVM :: CodeGen/ARM/ldm-stm-base-materialization.ll
LLVM :: CodeGen/ARM/ldm-stm-i256.ll
LLVM :: CodeGen/ARM/ldrd.ll
LLVM :: CodeGen/ARM/memcpy-ldm-stm.ll
LLVM :: CodeGen/ARM/neon_spill.ll
LLVM :: CodeGen/ARM/optselect-regclass.ll
LLVM :: CodeGen/ARM/pic.ll
LLVM :: CodeGen/ARM/sched-it-debug-nodes.mir
LLVM :: CodeGen/ARM/stack-alignment.ll
LLVM :: CodeGen/ARM/struct_byval_arm_t1_t2.ll
LLVM :: CodeGen/ARM/swift-return.ll
LLVM :: CodeGen/ARM/swifterror.ll
LLVM :: CodeGen/ARM/swiftself.ll
LLVM :: CodeGen/ARM/tail-dup-kill-flags.ll
LLVM :: CodeGen/ARM/thumb-big-stack.ll
LLVM :: CodeGen/ARM/urem-opt-size.ll
LLVM :: CodeGen/Hexagon/ifcvt-live-subreg.mir
LLVM :: CodeGen/Hexagon/livephysregs-lane-masks.mir
LLVM :: CodeGen/Hexagon/livephysregs-lane-masks2.mir
LLVM :: CodeGen/MIR/ARM/cfi-same-value.mir
LLVM :: CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll
LLVM :: CodeGen/PowerPC/2006-12-07-SelectCrash.ll
LLVM :: CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll
LLVM :: CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll
LLVM :: CodeGen/PowerPC/2008-10-28-f128-i32.ll
LLVM :: CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll
LLVM :: CodeGen/PowerPC/2012-09-16-TOC-entry-check.ll
LLVM :: CodeGen/PowerPC/crbit-asm.ll
LLVM :: CodeGen/PowerPC/crbits.ll
LLVM :: CodeGen/PowerPC/ctrloop-sh.ll
LLVM :: CodeGen/PowerPC/ctrloops.ll
LLVM :: CodeGen/PowerPC/expand-contiguous-isel.ll
LLVM :: CodeGen/PowerPC/expand-isel.ll
LLVM :: CodeGen/PowerPC/fast-isel-conversion.ll
LLVM :: CodeGen/PowerPC/float-to-int.ll
LLVM :: CodeGen/PowerPC/fold-zero.ll
LLVM :: CodeGen/PowerPC/fp-to-int-to-fp.ll
LLVM :: CodeGen/PowerPC/i1-ext-fold.ll
LLVM :: CodeGen/PowerPC/i1-to-double.ll
LLVM :: CodeGen/PowerPC/i64_fp_round.ll
LLVM :: CodeGen/PowerPC/ifcvt.ll
LLVM :: CodeGen/PowerPC/int-fp-conv-1.ll
LLVM :: CodeGen/PowerPC/isel.ll
LLVM :: CodeGen/PowerPC/mul-with-overflow.ll
LLVM :: CodeGen/PowerPC/optcmp.ll
LLVM :: CodeGen/PowerPC/p8-isel-sched.ll
LLVM :: CodeGen/PowerPC/ppc-crbits-onoff.ll
LLVM :: CodeGen/PowerPC/ppc32-lshrti3.ll
LLVM :: CodeGen/PowerPC/ppc64-32bit-addic.ll
LLVM :: CodeGen/PowerPC/ppc64-toc.ll
LLVM :: CodeGen/PowerPC/ppcf128sf.ll
LLVM :: CodeGen/PowerPC/pristine-and-livein.mir
LLVM :: CodeGen/PowerPC/select-i1-vs-i1.ll
LLVM :: CodeGen/PowerPC/select_const.ll
LLVM :: CodeGen/PowerPC/subreg-postra.ll
LLVM :: CodeGen/Thumb/2009-08-20-ISelBug.ll
LLVM :: CodeGen/Thumb/2014-06-10-thumb1-ldst-opt-bug.ll
LLVM :: CodeGen/Thumb/and_neg.ll
LLVM :: CodeGen/Thumb/ldm-merge-call.ll
LLVM :: CodeGen/Thumb/ldm-stm-base-materialization-thumb2.ll
LLVM :: CodeGen/Thumb/ldm-stm-base-materialization.ll
LLVM :: CodeGen/Thumb/optionaldef-scheduling.ll
LLVM :: CodeGen/Thumb/tbb-reuse.mir
LLVM :: CodeGen/Thumb/thumb-ldm.ll
LLVM :: CodeGen/Thumb2/constant-islands.ll
LLVM :: CodeGen/Thumb2/crash.ll
LLVM :: CodeGen/Thumb2/large-call.ll
LLVM :: CodeGen/Thumb2/segmented-stacks.ll
LLVM :: CodeGen/X86/block-placement.mir
LLVM :: CodeGen/X86/catchret-fallthrough.ll
LLVM :: CodeGen/X86/crash.ll
LLVM :: CodeGen/X86/implicit-null-check.ll
LLVM :: CodeGen/X86/implicit-null-checks.mir
LLVM :: CodeGen/X86/inline-asm-fpstack.ll
LLVM :: CodeGen/X86/win-catchpad-csrs.ll
LLVM :: CodeGen/X86/win-catchpad-nested-cxx.ll
LLVM :: CodeGen/X86/win-catchpad.ll
LLVM :: CodeGen/X86/win-cleanuppad.ll

Fixing this will be some effort and will take time. I have fixed aarch64 related checks and will look some more into ARM and X86.

But I think this brings us back to a similar discussion as http://llvm.org/PR32146. I think it may be a good idea to add some hooks so targets can indicate their level of verifier cleanliness. This would be a nice bringup tool that would allow us to enable the machine verifier in expensive checks by default or in this case indicate whether we want the "no pristines and no reserved regs in liveins" rule in the verifier enabled yet.

[MatzeB]

Turns out it isn't even possible to have ARM pass this verifier rule: We currently assume that all CSRs need to be alive at the end of a return block, however LR is modeled as a CSR register, but it does not need to be alive at the end of a return block because it gets copied to PC in the very last instruction.

This was already discovered as part of https://reviews.llvm.org/D33003, I am running into the same problem here.

[jonpa]

Make sure that at the end of basic blocks the liveins of the successor blocks are live (or the CSRs in case of return blocks)

So this only checks that there are not any false live-in entries in the live-in lists of successors, meaning that there could still be missing regs in the live-in lists of successors?

I remember a discussion a while back ago to switch to reg-units instead for live-in lists - what is the status on it?

How about using the RDF patch instead of this? I am thinking that since it actually computes the live-ins, it can easily verify the live-in lists. This would also be a way to get RDF into outside Hexagon.

[MatzeB]

In D33650#864758, @jonpa wrote:

Make sure that at the end of basic blocks the liveins of the successor blocks are live (or the CSRs in case of return blocks)

So this only checks that there are not any false live-in entries in the live-in lists of successors, meaning that there could still be missing regs in the live-in lists of successors?

Missing regs will already be catched (use of an undefined register). The important check here is that regs marked live-in are actually alive at the end of the predecessor blocks.

I remember a discussion a while back ago to switch to reg-units instead for live-in lists - what is the status on it?

No active work on it.

How about using the RDF patch instead of this? I am thinking that since it actually computes the live-ins, it can easily verify the live-in lists. This would also be a way to get RDF into outside Hexagon.

It's a good idea to write separate code for the verifier so bugs don't cancel each other out (it's also deliberately not using LiveIntervals here).

[MatzeB]

• Rebased on ToT.
• Now that we have the Restored member on CalleeSavedInfo we can deal with the ARM/LR problems cleanly.
• Factor out the pristine/reserved register check to a separate commit for now, it's hard enough to get tests passing without them.
• Various fixes.

This cannot be applied yet as a number of tests fail the new check:
test/CodeGen/ARM/cmpxchg-O0-be.ll
test/CodeGen/ARM/cmpxchg-O0.ll
test/CodeGen/BPF/objdump_intrinsics.ll
test/CodeGen/Hexagon/livephysregs-lane-masks.mir
test/CodeGen/Hexagon/livephysregs-lane-masks2.mir
test/CodeGen/Hexagon/rdf-phi-up.ll
test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll
test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll
test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll
test/CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll
test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
test/CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll
test/CodeGen/PowerPC/2012-09-16-TOC-entry-check.ll
test/CodeGen/PowerPC/crbit-asm.ll
test/CodeGen/PowerPC/ctrloop-sh.ll
test/CodeGen/PowerPC/ctrloops.ll
test/CodeGen/PowerPC/expand-contiguous-isel.ll
test/CodeGen/PowerPC/fast-isel-conversion.ll
test/CodeGen/PowerPC/float-to-int.ll
test/CodeGen/PowerPC/fold-zero.ll
test/CodeGen/PowerPC/fp-to-int-to-fp.ll
test/CodeGen/PowerPC/i1-ext-fold.ll
test/CodeGen/PowerPC/i1-to-double.ll
test/CodeGen/PowerPC/i64_fp_round.ll
test/CodeGen/PowerPC/ifcvt.ll
test/CodeGen/PowerPC/int-fp-conv-1.ll
test/CodeGen/PowerPC/isel.ll
test/CodeGen/PowerPC/mul-with-overflow.ll
test/CodeGen/PowerPC/p8-isel-sched.ll
test/CodeGen/PowerPC/ppc32-lshrti3.ll
test/CodeGen/PowerPC/ppc64-32bit-addic.ll
test/CodeGen/PowerPC/ppc64-toc.ll
test/CodeGen/PowerPC/ppcf128sf.ll
test/CodeGen/PowerPC/select-i1-vs-i1.ll
test/CodeGen/PowerPC/select_const.ll
test/CodeGen/PowerPC/subreg-postra.ll
test/CodeGen/X86/catchret-fallthrough.ll
test/CodeGen/X86/win-catchpad-csrs.ll
test/CodeGen/X86/win-catchpad-nested-cxx.ll
test/CodeGen/X86/win-catchpad.ll
test/CodeGen/X86/win-cleanuppad.ll

lib/CodeGen/MachineVerifier.cpp

struct MachineVerifier {
     using BlockSet = SmallPtrSet<const MachineBasicBlock *, 8>;
 
     const MachineInstr *FirstTerminator;
     BlockSet FunctionBlocks;
 
     BitVector regsReserved;
     RegSet regsLive;
     RegVector regsDefined, regsDead, regsKilled;
+    SmallVector<MCPhysReg, 16> expectedLiveOuts;
     RegMaskVector regMasks;
+    BitVector PristineRegs;
 
     SlotIndex lastIndex;
 
     // Add Reg and any sub-registers to RV
     void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
       RV.push_back(Reg);
       if (TargetRegisterInfo::isPhysicalRegister(Reg))
         for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
struct MachineVerifier {
     void report_context(const LiveInterval &LI) const;
     void report_context(const LiveRange &LR, unsigned VRegUnit,
                         LaneBitmask LaneMask) const;
     void report_context(const LiveRange::Segment &S) const;
     void report_context(const VNInfo &VNI) const;
     void report_context(SlotIndex Pos) const;
     void report_context_liverange(const LiveRange &LR) const;
     void report_context_lanemask(LaneBitmask LaneMask) const;
+    void report_context_reg(unsigned Reg) const;
     void report_context_vreg(unsigned VReg) const;
     void report_context_vreg_regunit(unsigned VRegOrRegUnit) const;
 
     void verifyInlineAsm(const MachineInstr *MI);
 
     void checkLiveness(const MachineOperand *MO, unsigned MONum);
     void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
                             SlotIndex UseIdx, const LiveRange &LR, unsigned Reg,

 void MachineVerifier::report_context(const VNInfo &VNI) const {
   errs() << "- ValNo:       " << VNI.id << " (def " << VNI.def << ")\n";
 }
 
 void MachineVerifier::report_context_liverange(const LiveRange &LR) const {
   errs() << "- liverange:   " << LR << '\n';
 }
 
+void MachineVerifier::report_context_reg(unsigned Reg) const {
+  errs() << "- register:    " << PrintReg(Reg, TRI) << '\n';
+}
+
 void MachineVerifier::report_context_vreg(unsigned VReg) const {
   errs() << "- v. register: " << PrintReg(VReg, TRI) << '\n';
 }
 
 void MachineVerifier::report_context_vreg_regunit(unsigned VRegOrUnit) const {
   if (TargetRegisterInfo::isVirtualRegister(VRegOrUnit)) {
     report_context_vreg(VRegOrUnit);
   } else {
if (MInfo.Succs.size() != MBB.succ_size())
       report("MBB has duplicate entries in its successor list.", &MBB);
   }
 
   // Check that the register use lists are sane.
   MRI->verifyUseLists();
 
   if (!MF->empty())
     verifyStackFrame();
+
+  const MachineFrameInfo &MFI = MF->getFrameInfo();
+  PristineRegs = MFI.getPristineRegs(*MF);
 }
 
 // Does iterator point to a and b as the first two elements?
 static bool matchPair(MachineBasicBlock::const_succ_iterator i,
                       const MachineBasicBlock *a, const MachineBasicBlock *b) {
   if (*i == a)
     return *++i == b;
   if (*i == b)
if (!TII->analyzeBranch(*const_cast<MachineBasicBlock *>(MBB), TBB, FBB,
     } else {
       report("AnalyzeBranch returned invalid data!", MBB);
     }
   }
 
   regsLive.clear();
   if (MRI->tracksLiveness()) {
     for (const auto &LI : MBB->liveins()) {
-      if (!TargetRegisterInfo::isPhysicalRegister(LI.PhysReg)) {
+      unsigned Reg = LI.PhysReg;
+      if (!TargetRegisterInfo::isPhysicalRegister(Reg)) {
         report("MBB live-in list contains non-physical register", MBB);
+        report_context_reg(Reg);
         continue;
       }
       for (MCSubRegIterator SubRegs(LI.PhysReg, TRI, /*IncludeSelf=*/true);
            SubRegs.isValid(); ++SubRegs)
         regsLive.insert(*SubRegs);
     }
   }
 
-  const MachineFrameInfo &MFI = MF->getFrameInfo();
-  BitVector PR = MFI.getPristineRegs(*MF);
-  for (unsigned I : PR.set_bits()) {
+  for (unsigned I : PristineRegs.set_bits()) {
     for (MCSubRegIterator SubRegs(I, TRI, /*IncludeSelf=*/true);
          SubRegs.isValid(); ++SubRegs)
       regsLive.insert(*SubRegs);
   }
 
   regsKilled.clear();
   regsDefined.clear();
 
void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
   }
   set_subtract(regsLive, regsDead);   regsDead.clear();
   set_union(regsLive, regsDefined);   regsDefined.clear();
 }
 
 void
 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
   MBBInfoMap[MBB].regsLiveOut = regsLive;
-  regsLive.clear();
 
   if (Indexes) {
     SlotIndex stop = Indexes->getMBBEndIdx(MBB);
     if (!(stop > lastIndex)) {
       report("Block ends before last instruction index", MBB);
       errs() << "Block ends at " << stop
           << " last instruction was at " << lastIndex << '\n';
     }
     lastIndex = stop;
   }
+
+  // Now that we now the liveness at the end of this basic block, we can
+  // verify that it matches the successors live-in lists or our expectations
+  // for return blocks.
+  if (MRI->tracksLiveness()) {
+    expectedLiveOuts.clear();
+    if (MBB->isReturnBlock() && !MBB->back().isCall()) {
+      // Note: We excluded tailcalls here as we do not care about CSR after the
+      // call. TODO: We should check CSRs before the tailcall instead.
+
+      const MachineFrameInfo &MFI = MF->getFrameInfo();
+      if (MFI.isCalleeSavedInfoValid()) {
+        for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo()) {
+          if (!Info.isRestored())
+            continue;
+          MCPhysReg Reg = Info.getReg();
+          if (MRI->isReserved(Reg))
+            continue;
+          expectedLiveOuts.push_back(Reg);
+        }
+      }
+    } else {
+      for (const MachineBasicBlock *Succ : MBB->successors()) {
+        // Don't add anything for EHPads. They have live-ins that are the result
+        // of the unwind/personality function that are not live-out of the
+        // predecessor and we don't know which is which.
+        if (Succ->isEHPad())
+          break;
+        for (const auto &LI : Succ->liveins()) {
+          MCPhysReg Reg = LI.PhysReg;
+          if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
+              !MRI->isReserved(Reg))
+            expectedLiveOuts.push_back(Reg);
+        }
+      }
+    }
+
+    for (MCPhysReg Reg : expectedLiveOuts) {
+      /* At least any of the subregisters should be live. */
+      bool IsLive = false;
+      for (MCSubRegIterator SR(Reg, TRI, true); SR.isValid(); ++SR) {
+        if (regsLive.count(*SR)) {
+          IsLive = true;
+          break;
+        }
+      }
+      if (!IsLive) {
+        report("Expected register to be live at end of MBB", MBB);
+        report_context_reg(Reg);
+      }
+    }
+    expectedLiveOuts.clear();
+  }
+
+  regsLive.clear();
 }
 
 // Calculate the largest possible vregsPassed sets. These are the registers that
 // can pass through an MBB live, but may not be live every time. It is assumed
 // that all vregsPassed sets are empty before the call.
 void MachineVerifier::calcRegsPassed() {
   // First push live-out regs to successors' vregsPassed. Remember the MBBs that
   // have any vregsPassed.

test/CodeGen/AArch64/machine-copy-remove.mir

 #  AArch64RedundantCopyElimination::optimizeCopy works correctly.
 # CHECK-LABEL: name: test8
 # CHECK: x0 = COPY %xzr
 # CHECK: x1 = COPY %xzr
 name:            test8
 tracksRegLiveness: true
 body:             |
   bb.0:
-    liveins: %x0, %x1
+    liveins: %x0, %x1, %x2
 
     %x1 = COPY %x0
     CBNZX %x1, %bb.2
 
   bb.1:
     liveins: %x0, %x2
 
     %x0, %x1 = LDPXi %x2, 0

 # Check that copy isn't removed from a block with multiple predecessors.
 # CHECK-LABEL: name: test9
 # CHECK: x0 = COPY %xzr
 # CHECK-NEXT: B %bb.3
 name:            test9
 tracksRegLiveness: true
 body:             |
   bb.0:
-    liveins: %x0, %x1
+    liveins: %x0, %x1, %x2
 
     CBNZX %x0, %bb.2
 
   bb.1:
     liveins: %x0, %x2
 
     %x0 = COPY %xzr
     B %bb.3
 
   bb.2:
-    liveins: %x1
+    liveins: %x1, %x2
 
     %x0 = LDRXui %x1, 0
 
     CBNZX %x1, %bb.1
 
   bb.3:
     liveins: %x0
 

test/CodeGen/AArch64/machine-zero-copy-remove.mir

 # RUN: llc -mtriple=aarch64--linux-gnu -run-pass=aarch64-copyelim %s -verify-machineinstrs -o - | FileCheck %s
 ---
 # CHECK-LABEL: name: test1
 # CHECK: ANDSWri %w0, 1, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: COPY %wzr
 name:            test1
 tracksRegLiveness: true
 body:             |
-  bb.0.entry:
+  bb.0:
     liveins: %w0, %x1, %x2
 
     %w0 = ANDSWri %w0, 1, implicit-def %nzcv
     STRWui killed %w0, killed %x1, 0
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
     liveins: %x2
 
     %w0 = COPY %wzr
     STRWui killed %w0, killed %x2, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # CHECK-LABEL: name: test2
 # CHECK: ANDSXri %x0, 1, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: COPY %xzr
 name:            test2
 tracksRegLiveness: true
 body:             |
-  bb.0.entry:
+  bb.0:
     liveins: %x0, %x1, %x2
 
     %x0 = ANDSXri %x0, 1, implicit-def %nzcv
     STRXui killed %x0, killed %x1, 0
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
     liveins: %x2
 
     %x0 = COPY %xzr
     STRXui killed %x0, killed %x2, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # CHECK-LABEL: name: test3
 # CHECK: ADDSWri %w0, 1, 0, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: COPY %wzr
 name:            test3
 tracksRegLiveness: true
 body:             |
-  bb.0.entry:
+  bb.0:
     liveins: %w0, %x1, %x2
 
     %w0 = ADDSWri %w0, 1, 0, implicit-def %nzcv
     STRWui killed %w0, killed %x1, 0
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
     liveins: %x2
 
     %w0 = COPY %wzr
     STRWui killed %w0, killed %x2, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # CHECK-LABEL: name: test4
 # CHECK: ADDSXri %x0, 1, 0, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: COPY %xzr
 name:            test4
 tracksRegLiveness: true
 body:             |
-  bb.0.entry:
+  bb.0:
     liveins: %x0, %x1, %x2
 
     %x0 = ADDSXri %x0, 1, 0, implicit-def %nzcv
     STRXui killed %x0, killed %x1, 0
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
     liveins: %x2
 
     %x0 = COPY %xzr
     STRXui killed %x0, killed %x2, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # CHECK-LABEL: name: test5
 # CHECK: SUBSWri %w0, 1, 0, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: COPY %wzr
 name:            test5
 tracksRegLiveness: true
 body:             |
-  bb.0.entry:
+  bb.0:
     liveins: %w0, %x1, %x2
 
     %w0 = SUBSWri %w0, 1, 0, implicit-def %nzcv
     STRWui killed %w0, killed %x1, 0
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
     liveins: %x2
 
     %w0 = COPY %wzr
     STRWui killed %w0, killed %x2, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # CHECK-LABEL: name: test6
 # CHECK: SUBSXri %x0, 1, 0, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: COPY %xzr
 name:            test6
 tracksRegLiveness: true
 body:             |
-  bb.0.entry:
+  bb.0:
     liveins: %x0, %x1, %x2
 
     %x0 = SUBSXri %x0, 1, 0, implicit-def %nzcv
     STRXui killed %x0, killed %x1, 0
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
     liveins: %x2
 
     %x0 = COPY %xzr
     STRXui killed %x0, killed %x2, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # CHECK-LABEL: name: test7
 # CHECK: ADDSWrr %w0, %w1, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: COPY %wzr
 name:            test7
 tracksRegLiveness: true
 body:             |
-  bb.0.entry:
+  bb.0:
     liveins: %w0, %w1, %x2, %x3
 
     %w0 = ADDSWrr %w0, %w1, implicit-def %nzcv
     STRWui killed %w0, killed %x2, 0
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
     liveins: %x3
 
     %w0 = COPY %wzr
     STRWui killed %w0, killed %x3, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # CHECK-LABEL: name: test8
 # CHECK: ADDSXrr %x0, %x1, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: COPY %xzr
 name:            test8
 tracksRegLiveness: true
 body:             |
-  bb.0.entry:
+  bb.0:
     liveins: %x0, %x1, %x2, %x3
 
     %x0 = ADDSXrr %x0, %x1, implicit-def %nzcv
     STRXui killed %x0, killed %x2, 0
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
     liveins: %x3
 
     %x0 = COPY %xzr
     STRXui killed %x0, killed %x3, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # CHECK-LABEL: name: test9
 # CHECK: ANDSWrr %w0, %w1, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: COPY %wzr
 name:            test9
 tracksRegLiveness: true
 body:             |
-  bb.0.entry:
+  bb.0:
     liveins: %w0, %w1, %x2, %x3
 
     %w0 = ANDSWrr %w0, %w1, implicit-def %nzcv
     STRWui killed %w0, killed %x2, 0
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
     liveins: %x3
 
     %w0 = COPY %wzr
     STRWui killed %w0, killed %x3, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # CHECK-LABEL: name: test10
 # CHECK: ANDSXrr %x0, %x1, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: COPY %xzr
 name:            test10
 tracksRegLiveness: true
 body:             |
-  bb.0.entry:
+  bb.0:
     liveins: %x0, %x1, %x2, %x3
 
     %x0 = ANDSXrr %x0, %x1, implicit-def %nzcv
     STRXui killed %x0, killed %x2, 0
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
     liveins: %x3
 
     %x0 = COPY %xzr
     STRXui killed %x0, killed %x3, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # CHECK-LABEL: name: test11
 # CHECK: BICSWrr %w0, %w1, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: COPY %wzr
 name:            test11
 tracksRegLiveness: true
 body:             |
-  bb.0.entry:
+  bb.0:
     liveins: %w0, %w1, %x2, %x3
 
     %w0 = BICSWrr %w0, %w1, implicit-def %nzcv
     STRWui killed %w0, killed %x2, 0
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
     liveins: %x3
 
     %w0 = COPY %wzr
     STRWui killed %w0, killed %x3, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # CHECK-LABEL: name: test12
 # CHECK: BICSXrr %x0, %x1, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: COPY %xzr
 name:            test12
 tracksRegLiveness: true
 body:             |
-  bb.0.entry:
+  bb.0:
     liveins: %x0, %x1, %x2, %x3
 
     %x0 = BICSXrr %x0, %x1, implicit-def %nzcv
     STRXui killed %x0, killed %x2, 0
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
     liveins: %x3
 
     %x0 = COPY %xzr
     STRXui killed %x0, killed %x3, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # CHECK-LABEL: name: test13
 # CHECK: SUBSWrr %w0, %w1, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: COPY %wzr
 name:            test13
 tracksRegLiveness: true
 body:             |
-  bb.0.entry:
+  bb.0:
     liveins: %w0, %w1, %x2, %x3
 
     %w0 = SUBSWrr %w0, %w1, implicit-def %nzcv
     STRWui killed %w0, killed %x2, 0
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
     liveins: %x3
 
     %w0 = COPY %wzr
     STRWui killed %w0, killed %x3, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # CHECK-LABEL: name: test14
 # CHECK: SUBSXrr %x0, %x1, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: COPY %xzr
 name:            test14
 tracksRegLiveness: true
 body:             |
-  bb.0.entry:
+  bb.0:
     liveins: %x0, %x1, %x2, %x3
 
     %x0 = SUBSXrr %x0, %x1, implicit-def %nzcv
     STRXui killed %x0, killed %x2, 0
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
     liveins: %x3
 
     %x0 = COPY %xzr
     STRXui killed %x0, killed %x3, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # CHECK-LABEL: name: test15
 # CHECK: ADDSWrs %w0, %w1, 0, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: COPY %wzr
 name:            test15
 tracksRegLiveness: true
 body:             |
-  bb.0.entry:
+  bb.0:
     liveins: %w0, %w1, %x2, %x3
 
     %w0 = ADDSWrs %w0, %w1, 0, implicit-def %nzcv
     STRWui killed %w0, killed %x2, 0
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
     liveins: %x3
 
     %w0 = COPY %wzr
     STRWui killed %w0, killed %x3, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # CHECK-LABEL: name: test16
 # CHECK: ADDSXrs %x0, %x1, 0, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: COPY %xzr
 name:            test16
 tracksRegLiveness: true
 body:             |
-  bb.0.entry:
+  bb.0:
     liveins: %x0, %x1, %x2, %x3
 
     %x0 = ADDSXrs %x0, %x1, 0, implicit-def %nzcv
     STRXui killed %x0, killed %x2, 0
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
     liveins: %x3
 
     %x0 = COPY %xzr
     STRXui killed %x0, killed %x3, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # CHECK-LABEL: name: test17
 # CHECK: ANDSWrs %w0, %w1, 0, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: COPY %wzr
 name:            test17
 tracksRegLiveness: true
 body:             |
-  bb.0.entry:
+  bb.0:
     liveins: %w0, %w1, %x2, %x3
 
     %w0 = ANDSWrs %w0, %w1, 0, implicit-def %nzcv
     STRWui killed %w0, killed %x2, 0
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
     liveins: %x3
 
     %w0 = COPY %wzr
     STRWui killed %w0, killed %x3, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # CHECK-LABEL: name: test18
 # CHECK: ANDSXrs %x0, %x1, 0, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: COPY %xzr
 name:            test18
 tracksRegLiveness: true
 body:             |
-  bb.0.entry:
+  bb.0:
     liveins: %x0, %x1, %x2, %x3
 
     %x0 = ANDSXrs %x0, %x1, 0, implicit-def %nzcv
     STRXui killed %x0, killed %x2, 0
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
     liveins: %x3
 
     %x0 = COPY %xzr
     STRXui killed %x0, killed %x3, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # CHECK-LABEL: name: test19
 # CHECK: BICSWrs %w0, %w1, 0, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: COPY %wzr
 name:            test19
 tracksRegLiveness: true
 body:             |
-  bb.0.entry:
+  bb.0:
     liveins: %w0, %w1, %x2, %x3
 
     %w0 = BICSWrs %w0, %w1, 0, implicit-def %nzcv
     STRWui killed %w0, killed %x2, 0
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:

 # CHECK-LABEL: name: test20
 # CHECK: SUBSWri %w1, 1, 0, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK-NOT: %w0 = COPY %wzr
 # CHECK-NOT: %w1 = MOVi32imm 1
 name:            test20
 tracksRegLiveness: true
 body:             |
-  bb.0.entry:
+  bb.0:
     liveins: %w1, %x2
 
     %w0 = SUBSWri %w1, 1, 0, implicit-def %nzcv
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
     liveins: %x2

 # Negative test - MOVi32imm clobbers %w0
 # CHECK-LABEL: name: test21
 # CHECK: ANDSWri %w0, 1, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK: %w0 = COPY %wzr
 name:            test21
 tracksRegLiveness: true
 body:             |
-  bb.0.entry:
+  bb.0:
     liveins: %w0, %x1, %x2
 
     %w0 = ANDSWri %w0, 1, implicit-def %nzcv
     STRWui killed %w0, %x1, 0
     %w0 = MOVi32imm -1
     STRWui killed %w0, killed %x1, 1
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1

 # Negative test - SUBSXri self-clobbers x0, so MOVi64imm can't be removed
 # CHECK-LABEL: name: test22
 # CHECK: SUBSXri %x0, 1, 0, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK: %x0 = MOVi64imm 1
 name:            test22
 tracksRegLiveness: true
 body:             |
-  bb.0.entry:
+  bb.0:
     liveins: %x0, %x1, %x2
 
     %x0 = SUBSXri %x0, 1, 0, implicit-def %nzcv
     STRXui killed %x0, killed %x1, 0
     Bcc 1, %bb.2, implicit killed %nzcv
     B %bb.1
 
   bb.1:
     liveins: %x2
 
     %x0 = MOVi64imm 1
     STRXui killed %x0, killed %x2, 0
 
   bb.2:
     RET_ReallyLR
 ...
 # Negative test - bb.1 has multiple preds
 # CHECK-LABEL: name: test23
 # CHECK: ADDSWri %w0, 1, 0, implicit-def %nzcv
 # CHECK: bb.1:
 # CHECK: COPY %wzr
 name:            test23
 tracksRegLiveness: true
 body:             |
-  bb.0.entry:
+  bb.0:
     liveins: %w0, %x1, %x2
 
     %w0 = ADDSWri %w0, 1, 0, implicit-def %nzcv
     STRWui killed %w0, killed %x1, 0
-    Bcc 1, %bb.2, implicit killed %nzcv
-    B %bb.1
-
-  bb.3:
-    B %bb.1
+    Bcc 1, %bb.3, implicit killed %nzcv
+    B %bb.2
 
   bb.1:
     liveins: %x2
+    B %bb.2
+
+  bb.2:
+    liveins: %x2
 
     %w0 = COPY %wzr
     STRWui killed %w0, killed %x2, 0
 
-  bb.2:
+  bb.3:
     RET_ReallyLR

test/CodeGen/Hexagon/livephysregs-lane-masks.mir

 
 
 ---
 name: foo
 tracksRegLiveness: true
 
 body: |
   bb.0:
-    liveins: %r16
+    liveins: %r16, %r0
     successors: %bb.1, %bb.2
         %p0 = C2_cmpeqi %r16, 0
         J2_jumpt %p0, %bb.2, implicit-def %pc
 
   bb.1:
     ; The lane mask %d0:0002 is equivalent to %r0. LivePhysRegs would ignore
     ; it and treat it as the whole %d0, which is a pair %r1, %r0. The extra
     ; %r1 would cause an (undefined) implicit use to be added during

test/CodeGen/Hexagon/livephysregs-lane-masks2.mir

 # RUN: llc -march=hexagon -verify-machineinstrs -run-pass branch-folder -o - %s | FileCheck %s
 
 # CHECK-LABEL: name: fred
 
 --- |
   define void @fred() { ret void }
 
 ...
 ---
 
 name: fred
 tracksRegLiveness: true
 
 body: |
   bb.0:
-    liveins: %p0:0x1, %p2, %r0
+    liveins: %p0:0x1, %p2, %r0, %r18, %r19
     successors: %bb.1, %bb.2
         J2_jumpt killed %p2, %bb.1, implicit-def %pc
         J2_jump %bb.2, implicit-def %pc
 
   bb.1:
     liveins: %p0:0x1, %r0, %r19
     successors: %bb.3
         %r2 = A2_tfrsi 4

test/CodeGen/MIR/ARM/cfi-same-value.mir

 frameInfo:
   stackSize:       48
   maxAlignment:    4
   adjustsStack:    true
   hasCalls:        true
 stack:
   - { id: 0, name: mem, offset: -48, size: 40, alignment: 4 }
   - { id: 1, type: spill-slot, offset: -4, size: 4, alignment: 4,
-      callee-saved-register: '%lr' }
+      callee-saved-register: '%lr', callee-saved-restored: false }
   - { id: 2, type: spill-slot, offset: -8, size: 4, alignment: 4,
       callee-saved-register: '%r11' }
 body: |
   bb.0:
     successors: %bb.2, %bb.1
     liveins: %r11, %lr
 
     %sp = STMDB_UPD %sp, 14, _, %r4, %r5
bb.2:
     liveins: %r11, %lr
 
     %sp = LDMIA_UPD %sp, 14, _, %r4, %r5
     CFI_INSTRUCTION def_cfa_offset 0
   ; CHECK:      CFI_INSTRUCTION same_value %r4
   ; CHECK-NEXT: CFI_INSTRUCTION same_value %r5
     CFI_INSTRUCTION same_value %r4
     CFI_INSTRUCTION same_value %r5
-    %sp = frame-setup STMDB_UPD %sp, 14, _, killed %r11, killed %lr
+    %sp = frame-setup STMDB_UPD %sp, 14, _, %r11, killed %lr
     frame-setup CFI_INSTRUCTION def_cfa_offset 8
     frame-setup CFI_INSTRUCTION offset %lr, -4
     frame-setup CFI_INSTRUCTION offset %r11, -8
     %sp = frame-setup SUBri killed %sp, 40, 14, _, _
     frame-setup CFI_INSTRUCTION def_cfa_offset 48
     %r0 = MOVr %sp, 14, _, _
     %r1 = MOVi 10, 14, _, _
     BL @dummy_use, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit killed %r1, implicit-def %sp
     %sp = ADDri killed %sp, 40, 14, _, _
     %sp = LDMIA_UPD %sp, 14, _, %r4, %r5
     MOVPCLR 14, _
 ...

test/CodeGen/X86/block-placement.mir

 # CHECK: name:            f
 name:            f
 alignment:       4
 tracksRegLiveness: true
 liveins:         
   - { reg: '%rdi' }
   - { reg: '%esi' }
 
-# CHECK: %eax = FAULTING_OP 1, %bb.3.null, 1684, killed %rdi, 1, _, 0, _ :: (load 4 from %ir.ptr)
+# CHECK: %eax = FAULTING_OP 1, %bb.3.null, 1684, %rdi, 1, _, 0, _ :: (load 4 from %ir.ptr)
 # CHECK-NEXT: JMP_1 %bb.2.not_null
 # CHECK: bb.3.null:
 # CHECK:  bb.4.right:
 # CHECK:  bb.2.not_null:
 
 body:             |
   bb.0.entry:
     successors: %bb.1.left(0x7ffff800), %bb.3.right(0x00000800)
     liveins: %esi, %rdi
   
     frame-setup PUSH64r undef %rax, implicit-def %rsp, implicit %rsp
     CFI_INSTRUCTION def_cfa_offset 16
     TEST8ri %sil, 1, implicit-def %eflags, implicit killed %esi
     JE_1 %bb.3.right, implicit killed %eflags
   
   bb.1.left:
     successors: %bb.2.null(0x7ffff800), %bb.4.not_null(0x00000800)
     liveins: %rdi
   
-    %eax = FAULTING_OP 1, %bb.2.null, 1684, killed %rdi, 1, _, 0, _ :: (load 4 from %ir.ptr)
+    %eax = FAULTING_OP 1, %bb.2.null, 1684, %rdi, 1, _, 0, _ :: (load 4 from %ir.ptr)
     JMP_1 %bb.4.not_null
   
   bb.4.not_null:
     liveins: %rdi, %eax
   
     %rcx = POP64r implicit-def %rsp, implicit %rsp
     RETQ %eax
 

test/CodeGen/X86/implicit-null-checks.mir

bb.1.not_null:
     CMP32rr killed %eax, killed %esi, implicit-def %eflags
     JE_1 %bb.4.ret_100, implicit %eflags
 
   bb.2.ret_200:
 
     %eax = MOV32ri 200
 
   bb.3.is_null:
-    liveins: %eax, %ah, %al, %ax, %bh, %bl, %bp, %bpl, %bx, %eax, %ebp, %ebx, %rax, %rbp, %rbx, %r12, %r13, %r14, %r15, %r12b, %r13b, %r14b, %r15b, %r12d, %r13d, %r14d, %r15d, %r12w, %r13w, %r14w, %r15w
+    liveins: %eax
 
     RETQ %eax
 
   bb.4.ret_100:
     %eax = MOV32ri 100
     RETQ %eax
 
 ...