[KnownBits] Add methods to set and clear all bits.

[craig.topper]

Summary

This adds a clearAll and setAll method to KnownBits that call either clearAllBits or setAllBits on both.

We also still need methods to clear Zero/One and and set all bits in the opposite. I'm considering makeZero() and makeAllOnes(). As I'm writing this I'm wondering if clearAllBits should be makeUnknown. Not sure what setAll would be in that naming.

I'm worried about mixing the "clearing" a bit to unknown state vs making a bit known to be zero which would be consider clearing its value. I want to be able to treat KnownBits as a value so we can say is it known negative or nonnegative or zero or all ones. But I also want to be able to refer to its unknown/known set of bits.

[craig.topper]

I think my previous diff may have been incomplete.

[craig.topper]

Fix a misnamed call.

[RKSimon]

This looks incomplete - the addition of the method to the KnownBits struct is missing and there is no context to the diff.

[RKSimon]

We also still need methods to clear Zero/One and and set all bits in the opposite. I'm considering makeZero() and makeAllOnes(). As I'm writing this I'm wondering if clearAllBits should be makeUnknown. Not sure what setAll would be in that naming.

Would KnowBits::makeInvalid make sense?

[RKSimon]

Why not KnownBits::clearAllBits() + KnownBits::setAllBits() ?

[craig.topper]

I've removed the method that sets all bits in both zero and one for now. I think that should be done in a future patch that adds intersecting support since setting all vectors always proceeds an intersection loop. Maybe the method should just be prepareForIntersection or something that stresses that its only useful for that.

I've added methods for testing and setting all ones and all zeros. To preserve existing code semantics I've added two versions of setting zero/one, one that just asserts if it creates a conflict, and one that erases all previous information. The latter is called 'force', but I'm not sure if that's a good name.

Making the vector unknown is now called resetAll. And there is a method to check if the known bits are all unknown.

Let me know if these names make sense. I'm open to other suggestions.

[RKSimon]

I'm not sure we have a need for both the 'set' and 'force' versions - AFAICT all the 'set' cases above could be 'force' as we're just making use of the fact that we know that the KnownBits are all zero at initialization. Maybe just have 'force' version and call them 'set'? If that make sense at all......

[craig.topper]

Merge setAllZero and forceAllZero. Same for AllOnes.

[RKSimon]

LGTM

llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h

public:
   /// the larger bit width by zero extension. The bit width must be no smaller
   /// than the LiveOutInfo's existing bit width.
   const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth);
 
   /// AddLiveOutRegInfo - Adds LiveOutInfo for a register.
   void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits,
                          const KnownBits &Known) {
     // Only install this information if it tells us something.
-    if (NumSignBits == 1 && Known.Zero == 0 && Known.One == 0)
+    if (NumSignBits == 1 && Known.isUnknown())
       return;
 
     LiveOutRegInfo.grow(Reg);
     LiveOutInfo &LOI = LiveOutRegInfo[Reg];
     LOI.NumSignBits = NumSignBits;
     LOI.Known.One = Known.One;
     LOI.Known.Zero = Known.Zero;
   }

llvm/trunk/include/llvm/Support/KnownBits.h

public:
 
   /// Returns the value when all bits have a known value. This just returns One
   /// with a protective assertion.
   const APInt &getConstant() const {
     assert(isConstant() && "Can only get value when all bits are known");
     return One;
   }
 
+  /// Returns true if we don't know any bits.
+  bool isUnknown() const { return Zero.isNullValue() && One.isNullValue(); }
+
+  /// Resets the known state of all bits.
+  void resetAll() {
+    Zero.clearAllBits();
+    One.clearAllBits();
+  }
+
+  /// Returns true if value is all zero.
+  bool isZero() const {
+    assert(!hasConflict() && "KnownBits conflict!");
+    return Zero.isAllOnesValue();
+  }
+
+  /// Returns true if value is all one bits.
+  bool isAllOnes() const {
+    assert(!hasConflict() && "KnownBits conflict!");
+    return One.isAllOnesValue();
+  }
+
+  /// Make all bits known to be zero and discard any previous information.
+  void setAllZero() {
+    Zero.setAllBits();
+    One.clearAllBits();
+  }
+
+  /// Make all bits known to be one and discard any previous information.
+  void setAllOnes() {
+    Zero.clearAllBits();
+    One.setAllBits();
+  }
+
   /// Returns true if this value is known to be negative.
   bool isNegative() const { return One.isSignBitSet(); }
 
   /// Returns true if this value is known to be non-negative.
   bool isNonNegative() const { return Zero.isSignBitSet(); }
 
   /// Make this value negative.
   void makeNegative() {

llvm/trunk/lib/Analysis/Lint.cpp

static bool isZero(Value *V, const DataLayout &DL, DominatorTree *DT,
   if (isa<UndefValue>(V))
     return true;
 
   VectorType *VecTy = dyn_cast<VectorType>(V->getType());
   if (!VecTy) {
     unsigned BitWidth = V->getType()->getIntegerBitWidth();
     KnownBits Known(BitWidth);
     computeKnownBits(V, Known, DL, 0, AC, dyn_cast<Instruction>(V), DT);
-    return Known.Zero.isAllOnesValue();
+    return Known.isZero();
   }
 
   // Per-component check doesn't work with zeroinitializer
   Constant *C = dyn_cast<Constant>(V);
   if (!C)
     return false;
 
   if (C->isZeroValue())
     return true;
 
   // For a vector, KnownZero will only be true if all values are zero, so check
   // this per component
   unsigned BitWidth = VecTy->getElementType()->getIntegerBitWidth();
   for (unsigned I = 0, N = VecTy->getNumElements(); I != N; ++I) {
     Constant *Elem = C->getAggregateElement(I);
     if (isa<UndefValue>(Elem))
       return true;
 
     KnownBits Known(BitWidth);
     computeKnownBits(Elem, Known, DL);
-    if (Known.Zero.isAllOnesValue())
+    if (Known.isZero())
       return true;
   }
 
   return false;
 }
 
 void Lint::visitSDiv(BinaryOperator &I) {
   Assert(!isZero(I.getOperand(1), I.getModule()->getDataLayout(), DT, AC),

llvm/trunk/lib/Analysis/ValueTracking.cpp

if (Op0 == Op1) {
                            isKnownNonZero(Op1, Depth, Q));
     }
   }
 
   // If low bits are zero in either operand, output low known-0 bits.
   // Also compute a conservative estimate for high known-0 bits.
   // More trickiness is possible, but this is sufficient for the
   // interesting case of alignment computation.
-  Known.One.clearAllBits();
   unsigned TrailZ = Known.Zero.countTrailingOnes() +
                     Known2.Zero.countTrailingOnes();
   unsigned LeadZ =  std::max(Known.Zero.countLeadingOnes() +
                              Known2.Zero.countLeadingOnes(),
                              BitWidth) - BitWidth;
 
   TrailZ = std::min(TrailZ, BitWidth);
   LeadZ = std::min(LeadZ, BitWidth);
-  Known.Zero.clearAllBits();
+  Known.resetAll();
   Known.Zero.setLowBits(TrailZ);
   Known.Zero.setHighBits(LeadZ);
 
   // Only make use of no-wrap flags if we failed to compute the sign bit
   // directly.  This matters if the multiplication always overflows, in
   // which case we prefer to follow the result of the direct computation,
   // though as the program is invoking undefined behaviour we can choose
   // whatever we like here.
for (auto &AssumeVH : Q.AC->assumptionsFor(V)) {
 
     assert(I->getCalledFunction()->getIntrinsicID() == Intrinsic::assume &&
            "must be an assume intrinsic");
 
     Value *Arg = I->getArgOperand(0);
 
     if (Arg == V && isValidAssumeForContext(I, Q.CxtI, Q.DT)) {
       assert(BitWidth == 1 && "assume operand is not i1?");
-      Known.Zero.clearAllBits();
-      Known.One.setAllBits();
+      Known.setAllOnes();
       return;
     }
     if (match(Arg, m_Not(m_Specific(V))) &&
         isValidAssumeForContext(I, Q.CxtI, Q.DT)) {
       assert(BitWidth == 1 && "assume operand is not i1?");
-      Known.Zero.setAllBits();
-      Known.One.clearAllBits();
+      Known.setAllZero();
       return;
     }
 
     // The remaining tests are all recursive, so bail out if we hit the limit.
     if (Depth == MaxDepth)
       continue;
 
     Value *A, *B;
// assume(v >=_s c) where c is non-negative
       }
     // assume(v >_s c) where c is at least -1.
     } else if (match(Arg, m_ICmp(Pred, m_V, m_Value(A))) &&
                Pred == ICmpInst::ICMP_SGT &&
                isValidAssumeForContext(I, Q.CxtI, Q.DT)) {
       KnownBits RHSKnown(BitWidth);
       computeKnownBits(A, RHSKnown, Depth+1, Query(Q, I));
 
-      if (RHSKnown.One.isAllOnesValue() || RHSKnown.isNonNegative()) {
+      if (RHSKnown.isAllOnes() || RHSKnown.isNonNegative()) {
         // We know that the sign bit is zero.
         Known.makeNonNegative();
       }
     // assume(v <=_s c) where c is negative
     } else if (match(Arg, m_ICmp(Pred, m_V, m_Value(A))) &&
                Pred == ICmpInst::ICMP_SLE &&
                isValidAssumeForContext(I, Q.CxtI, Q.DT)) {
       KnownBits RHSKnown(BitWidth);
       computeKnownBits(A, RHSKnown, Depth+1, Query(Q, I));
 
       if (RHSKnown.isNegative()) {
         // We know that the sign bit is one.
         Known.makeNegative();
       }
     // assume(v <_s c) where c is non-positive
     } else if (match(Arg, m_ICmp(Pred, m_V, m_Value(A))) &&
                Pred == ICmpInst::ICMP_SLT &&
                isValidAssumeForContext(I, Q.CxtI, Q.DT)) {
       KnownBits RHSKnown(BitWidth);
       computeKnownBits(A, RHSKnown, Depth+1, Query(Q, I));
 
-      if (RHSKnown.Zero.isAllOnesValue() || RHSKnown.isNegative()) {
+      if (RHSKnown.isZero() || RHSKnown.isNegative()) {
         // We know that the sign bit is one.
         Known.makeNegative();
       }
     // assume(v <=_u c)
     } else if (match(Arg, m_ICmp(Pred, m_V, m_Value(A))) &&
                Pred == ICmpInst::ICMP_ULE &&
                isValidAssumeForContext(I, Q.CxtI, Q.DT)) {
       KnownBits RHSKnown(BitWidth);
static void computeKnownBitsFromAssume(const Value *V, KnownBits &Known,
   }
 
   // If assumptions conflict with each other or previous known bits, then we
   // have a logical fallacy. It's possible that the assumption is not reachable,
   // so this isn't a real bug. On the other hand, the program may have undefined
   // behavior, or we might have a bug in the compiler. We can't assert/crash, so
   // clear out the known bits, try to warn the user, and hope for the best.
   if (Known.Zero.intersects(Known.One)) {
-    Known.Zero.clearAllBits();
-    Known.One.clearAllBits();
+    Known.resetAll();
 
     if (Q.ORE) {
       auto *CxtI = const_cast<Instruction *>(Q.CxtI);
       OptimizationRemarkAnalysis ORA("value-tracking", "BadAssumption", CxtI);
       Q.ORE->emit(ORA << "Detected conflicting code assumptions. Program may "
                          "have undefined behavior, or compiler may have "
                          "internal error.");
     }
if (auto *SA = dyn_cast<ConstantInt>(I->getOperand(1))) {
     unsigned ShiftAmt = SA->getLimitedValue(BitWidth-1);
 
     computeKnownBits(I->getOperand(0), Known, Depth + 1, Q);
     Known.Zero = KZF(Known.Zero, ShiftAmt);
     Known.One  = KOF(Known.One, ShiftAmt);
     // If there is conflict between Known.Zero and Known.One, this must be an
     // overflowing left shift, so the shift result is undefined. Clear Known
     // bits so that other code could propagate this undef.
-    if ((Known.Zero & Known.One) != 0) {
-      Known.Zero.clearAllBits();
-      Known.One.clearAllBits();
-    }
+    if ((Known.Zero & Known.One) != 0)
+      Known.resetAll();
 
     return;
   }
 
   computeKnownBits(I->getOperand(1), Known, Depth + 1, Q);
 
   // If the shift amount could be greater than or equal to the bit-width of the LHS, the
   // value could be undef, so we don't know anything about it.
   if ((~Known.Zero).uge(BitWidth)) {
-    Known.Zero.clearAllBits();
-    Known.One.clearAllBits();
+    Known.resetAll();
     return;
   }
 
   // Note: We cannot use Known.Zero.getLimitedValue() here, because if
   // BitWidth > 64 and any upper bits are known, we'll end up returning the
   // limit value (which implies all bits are known).
   uint64_t ShiftAmtKZ = Known.Zero.zextOrTrunc(64).getZExtValue();
   uint64_t ShiftAmtKO = Known.One.zextOrTrunc(64).getZExtValue();
 
   // It would be more-clearly correct to use the two temporaries for this
   // calculation. Reusing the APInts here to prevent unnecessary allocations.
-  Known.Zero.clearAllBits();
-  Known.One.clearAllBits();
+  Known.resetAll();
 
   // If we know the shifter operand is nonzero, we can sometimes infer more
   // known bits. However this is expensive to compute, so be lazy about it and
   // only compute it when absolutely necessary.
   Optional<bool> ShifterOperandIsNonZero;
 
   // Early exit if we can't constrain any well-defined shift amount.
   if (!(ShiftAmtKZ & (BitWidth - 1)) && !(ShiftAmtKO & (BitWidth - 1))) {
for (unsigned ShiftAmt = 0; ShiftAmt < BitWidth; ++ShiftAmt) {
     Known.One  &= KOF(Known2.One, ShiftAmt);
   }
 
   // If there are no compatible shift amounts, then we've proven that the shift
   // amount must be >= the BitWidth, and the result is undefined. We could
   // return anything we'd like, but we need to make sure the sets of known bits
   // stay disjoint (it should be better for some other code to actually
   // propagate the undef than to pick a value here using known bits).
-  if (Known.Zero.intersects(Known.One)) {
-    Known.Zero.clearAllBits();
-    Known.One.clearAllBits();
-  }
+  if (Known.Zero.intersects(Known.One))
+    Known.resetAll();
 }
 
 static void computeKnownBitsFromOperator(const Operator *I, KnownBits &Known,
                                          unsigned Depth, const Query &Q) {
   unsigned BitWidth = Known.getBitWidth();
 
   KnownBits Known2(Known);
   switch (I->getOpcode()) {
case Instruction::And: {
     // TODO: This could be generalized to clearing any bit set in y where the
     // following bit is known to be unset in y.
     Value *Y = nullptr;
     if (!Known.Zero[0] && !Known.One[0] &&
         (match(I->getOperand(0), m_Add(m_Specific(I->getOperand(1)),
                                        m_Value(Y))) ||
          match(I->getOperand(1), m_Add(m_Specific(I->getOperand(0)),
                                        m_Value(Y))))) {
-      Known2.Zero.clearAllBits(); Known2.One.clearAllBits();
+      Known2.resetAll();
       computeKnownBits(Y, Known2, Depth + 1, Q);
       if (Known2.One.countTrailingOnes() > 0)
         Known.Zero.setBit(0);
     }
     break;
   }
   case Instruction::Or: {
     computeKnownBits(I->getOperand(1), Known, Depth + 1, Q);
static void computeKnownBitsFromOperator(const Operator *I, KnownBits &Known,
   }
   case Instruction::UDiv: {
     // For the purposes of computing leading zeros we can conservatively
     // treat a udiv as a logical right shift by the power of 2 known to
     // be less than the denominator.
     computeKnownBits(I->getOperand(0), Known2, Depth + 1, Q);
     unsigned LeadZ = Known2.Zero.countLeadingOnes();
 
-    Known2.One.clearAllBits();
-    Known2.Zero.clearAllBits();
+    Known2.resetAll();
     computeKnownBits(I->getOperand(1), Known2, Depth + 1, Q);
     unsigned RHSUnknownLeadingOnes = Known2.One.countLeadingZeros();
     if (RHSUnknownLeadingOnes != BitWidth)
       LeadZ = std::min(BitWidth,
                        LeadZ + BitWidth - RHSUnknownLeadingOnes - 1);
 
     Known.Zero.setHighBits(LeadZ);
     break;
case Instruction::URem: {
 
     // Since the result is less than or equal to either operand, any leading
     // zero bits in either operand must also exist in the result.
     computeKnownBits(I->getOperand(0), Known, Depth + 1, Q);
     computeKnownBits(I->getOperand(1), Known2, Depth + 1, Q);
 
     unsigned Leaders = std::max(Known.Zero.countLeadingOnes(),
                                 Known2.Zero.countLeadingOnes());
-    Known.One.clearAllBits();
-    Known.Zero.clearAllBits();
+    Known.resetAll();
     Known.Zero.setHighBits(Leaders);
     break;
   }
 
   case Instruction::Alloca: {
     const AllocaInst *AI = cast<AllocaInst>(I);
     unsigned Align = AI->getAlignment();
     if (Align == 0)
void computeKnownBits(const Value *V, KnownBits &Known, unsigned Depth,
   if (match(V, m_APInt(C))) {
     // We know all of the bits for a scalar constant or a splat vector constant!
     Known.One = *C;
     Known.Zero = ~Known.One;
     return;
   }
   // Null and aggregate-zero are all-zeros.
   if (isa<ConstantPointerNull>(V) || isa<ConstantAggregateZero>(V)) {
-    Known.One.clearAllBits();
-    Known.Zero.setAllBits();
+    Known.setAllZero();
     return;
   }
   // Handle a constant vector by taking the intersection of the known bits of
   // each element.
   if (const ConstantDataSequential *CDS = dyn_cast<ConstantDataSequential>(V)) {
     // We know that CDS must be a vector of integers. Take the intersection of
     // each element.
     Known.Zero.setAllBits(); Known.One.setAllBits();
if (const auto *CV = dyn_cast<ConstantVector>(V)) {
     // We know that CV must be a vector of integers. Take the intersection of
     // each element.
     Known.Zero.setAllBits(); Known.One.setAllBits();
     APInt Elt(BitWidth, 0);
     for (unsigned i = 0, e = CV->getNumOperands(); i != e; ++i) {
       Constant *Element = CV->getAggregateElement(i);
       auto *ElementCI = dyn_cast_or_null<ConstantInt>(Element);
       if (!ElementCI) {
-        Known.Zero.clearAllBits();
-        Known.One.clearAllBits();
+        Known.resetAll();
         return;
       }
       Elt = ElementCI->getValue();
       Known.Zero &= ~Elt;
       Known.One &= Elt;
     }
     return;
   }
 
   // Start out not knowing anything.
-  Known.Zero.clearAllBits(); Known.One.clearAllBits();
+  Known.resetAll();
 
   // We can't imply anything about undefs.
   if (isa<UndefValue>(V))
     return;
 
   // There's no point in looking through other users of ConstantData for
   // assumptions.  Confirm that we've handled them all.
   assert(!isa<ConstantData>(V) && "Unhandled constant data!");

llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

case ISD::VECTOR_SHUFFLE: {
     for (unsigned i = 0; i != NumElts; ++i) {
       if (!DemandedElts[i])
         continue;
 
       int M = SVN->getMaskElt(i);
       if (M < 0) {
         // For UNDEF elements, we don't know anything about the common state of
         // the shuffle result.
-        Known.One.clearAllBits();
-        Known.Zero.clearAllBits();
+        Known.resetAll();
         DemandedLHS.clearAllBits();
         DemandedRHS.clearAllBits();
         break;
       }
 
       if ((unsigned)M < NumElts)
         DemandedLHS.setBit((unsigned)M % NumElts);
       else
void SelectionDAG::computeKnownBits(SDValue Op, KnownBits &Known,
   case ISD::MUL: {
     computeKnownBits(Op.getOperand(1), Known, DemandedElts, Depth + 1);
     computeKnownBits(Op.getOperand(0), Known2, DemandedElts, Depth + 1);
 
     // If low bits are zero in either operand, output low known-0 bits.
     // Also compute a conservative estimate for high known-0 bits.
     // More trickiness is possible, but this is sufficient for the
     // interesting case of alignment computation.
-    Known.One.clearAllBits();
     unsigned TrailZ = Known.Zero.countTrailingOnes() +
                       Known2.Zero.countTrailingOnes();
     unsigned LeadZ =  std::max(Known.Zero.countLeadingOnes() +
                                Known2.Zero.countLeadingOnes(),
                                BitWidth) - BitWidth;
 
-    Known.Zero.clearAllBits();
+    Known.resetAll();
     Known.Zero.setLowBits(std::min(TrailZ, BitWidth));
     Known.Zero.setHighBits(std::min(LeadZ, BitWidth));
     break;
   }
   case ISD::UDIV: {
     // For the purposes of computing leading zeros we can conservatively
     // treat a udiv as a logical right shift by the power of 2 known to
     // be less than the denominator.
case ISD::UREM: {
 
     // Since the result is less than or equal to either operand, any leading
     // zero bits in either operand must also exist in the result.
     computeKnownBits(Op.getOperand(0), Known, DemandedElts, Depth + 1);
     computeKnownBits(Op.getOperand(1), Known2, DemandedElts, Depth + 1);
 
     uint32_t Leaders = std::max(Known.Zero.countLeadingOnes(),
                                 Known2.Zero.countLeadingOnes());
-    Known.One.clearAllBits();
-    Known.Zero.clearAllBits();
+    Known.resetAll();
     Known.Zero.setHighBits(Leaders);
     break;
   }
   case ISD::EXTRACT_ELEMENT: {
     computeKnownBits(Op.getOperand(0), Known, Depth+1);
     const unsigned Index = Op.getConstantOperandVal(1);
     const unsigned BitWidth = Op.getValueSizeInBits();
 

llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp

void TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
                                                    const SelectionDAG &DAG,
                                                    unsigned Depth) const {
   assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
           Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
           Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
           Op.getOpcode() == ISD::INTRINSIC_VOID) &&
          "Should use MaskedValueIsZero if you don't know whether Op"
          " is a target node!");
-  Known.Zero.clearAllBits(); Known.One.clearAllBits();
+  Known.resetAll();
 }
 
 /// This method can be implemented by targets that want to expose additional
 /// information about sign bits to the DAG Combiner.
 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
                                                          const APInt &,
                                                          const SelectionDAG &,
                                                          unsigned Depth) const {

llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
 
   return SDValue();
 }
 
 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
     const SDValue Op, KnownBits &Known,
     const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const {
 
-  Known.Zero.clearAllBits(); Known.One.clearAllBits(); // Don't know anything.
+  Known.resetAll(); // Don't know anything.
 
   KnownBits Known2;
   unsigned Opc = Op.getOpcode();
 
   switch (Opc) {
   default:
     break;
   case AMDGPUISD::CARRY:

llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

 }
 
 void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
                                                       KnownBits &Known,
                                                       const APInt &DemandedElts,
                                                       const SelectionDAG &DAG,
                                                       unsigned Depth) const {
   unsigned BitWidth = Known.getBitWidth();
-  Known.Zero.clearAllBits(); Known.One.clearAllBits();
+  Known.resetAll();
   switch (Op.getOpcode()) {
   default: break;
   case ARMISD::ADDC:
   case ARMISD::ADDE:
   case ARMISD::SUBC:
   case ARMISD::SUBE:
     // These nodes' second result is a boolean
     if (Op.getResNo() == 0)
       break;
     Known.Zero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
     break;
   case ARMISD::CMOV: {
     // Bits are known zero/one if known on the LHS and RHS.
     DAG.computeKnownBits(Op.getOperand(0), Known, Depth+1);
-    if (Known.Zero == 0 && Known.One == 0) return;
+    if (Known.isUnknown())
+      return;
 
     KnownBits KnownRHS;
     DAG.computeKnownBits(Op.getOperand(1), KnownRHS, Depth+1);
     Known.Zero &= KnownRHS.Zero;
     Known.One  &= KnownRHS.One;
     return;
   }
   case ISD::INTRINSIC_W_CHAIN: {

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

 // Inline Assembly Support
 //===----------------------------------------------------------------------===//
 
 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
                                                       KnownBits &Known,
                                                       const APInt &DemandedElts,
                                                       const SelectionDAG &DAG,
                                                       unsigned Depth) const {
-  Known.Zero.clearAllBits(); Known.One.clearAllBits();
+  Known.resetAll();
   switch (Op.getOpcode()) {
   default: break;
   case PPCISD::LBRX: {
     // lhbrx is known to have the top bits cleared out.
     if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
       Known.Zero = 0xFFFF0000;
     break;
   }

llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp

 /// combiner.
 void SparcTargetLowering::computeKnownBitsForTargetNode
                                 (const SDValue Op,
                                  KnownBits &Known,
                                  const APInt &DemandedElts,
                                  const SelectionDAG &DAG,
                                  unsigned Depth) const {
   KnownBits Known2;
-  Known.Zero.clearAllBits(); Known.One.clearAllBits();
+  Known.resetAll();
 
   switch (Op.getOpcode()) {
   default: break;
   case SPISD::SELECT_ICC:
   case SPISD::SELECT_XCC:
   case SPISD::SELECT_FCC:
     DAG.computeKnownBits(Op.getOperand(1), Known, Depth+1);
     DAG.computeKnownBits(Op.getOperand(0), Known2, Depth+1);

llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
   EVT VT = Op.getValueType();
   assert((Opc >= ISD::BUILTIN_OP_END ||
           Opc == ISD::INTRINSIC_WO_CHAIN ||
           Opc == ISD::INTRINSIC_W_CHAIN ||
           Opc == ISD::INTRINSIC_VOID) &&
          "Should use MaskedValueIsZero if you don't know whether Op"
          " is a target node!");
 
-  Known.Zero.clearAllBits(); Known.One.clearAllBits();
+  Known.resetAll();
   switch (Opc) {
   default: break;
   case X86ISD::ADD:
   case X86ISD::SUB:
   case X86ISD::ADC:
   case X86ISD::SBB:
   case X86ISD::SMUL:
   case X86ISD::UMUL:
case X86ISD::MOVMSK: {
     unsigned NumLoBits = Op.getOperand(0).getValueType().getVectorNumElements();
     Known.Zero.setBitsFrom(NumLoBits);
     break;
   }
   case X86ISD::VSHLI:
   case X86ISD::VSRLI: {
     if (auto *ShiftImm = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
       if (ShiftImm->getAPIntValue().uge(VT.getScalarSizeInBits())) {
-        Known.Zero.setAllBits();
+        Known.setAllZero();
         break;
       }
 
       DAG.computeKnownBits(Op.getOperand(0), Known, Depth + 1);
       unsigned ShAmt = ShiftImm->getZExtValue();
       if (Opc == X86ISD::VSHLI) {
         Known.Zero <<= ShAmt;
         Known.One <<= ShAmt;

llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp

SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,
   return SDValue();
 }
 
 void XCoreTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
                                                         KnownBits &Known,
                                                         const APInt &DemandedElts,
                                                         const SelectionDAG &DAG,
                                                         unsigned Depth) const {
-  Known.Zero.clearAllBits(); Known.One.clearAllBits();
+  Known.resetAll();
   switch (Op.getOpcode()) {
   default: break;
   case XCoreISD::LADD:
   case XCoreISD::LSUB:
     if (Op.getResNo() == 1) {
       // Top bits of carry / borrow are clear.
       Known.Zero = APInt::getHighBitsSet(Known.getBitWidth(),
                                          Known.getBitWidth() - 1);

llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp

if (match(IIOperand, m_ICmp(Pred, m_Instruction(LHS), m_Zero())) &&
       // TODO: apply nonnull return attributes to calls and invokes
       // TODO: apply range metadata for range check patterns?
     }
 
     // If there is a dominating assume with the same condition as this one,
     // then this one is redundant, and should be removed.
     KnownBits Known(1);
     computeKnownBits(IIOperand, Known, 0, II);
-    if (Known.One.isAllOnesValue())
+    if (Known.isAllOnes())
       return eraseInstFromFunction(*II);
 
     // Update the cache of affected values for this assumption (we might be
     // here because we just simplified the condition).
     AC.updateAffectedValues(II);
     break;
   }
   case Intrinsic::experimental_gc_relocate: {

llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp

if (Op0Max.ult(Op1Min) || Op0Min.ugt(Op1Max)) {
                  ? replaceInstUsesWith(I, ConstantInt::getFalse(I.getType()))
                  : replaceInstUsesWith(I, ConstantInt::getTrue(I.getType()));
     }
 
     // If all bits are known zero except for one, then we know at most one bit
     // is set. If the comparison is against zero, then this is a check to see if
     // *that* bit is set.
     APInt Op0KnownZeroInverted = ~Op0Known.Zero;
-    if (~Op1Known.Zero == 0) {
+    if (Op1Known.isZero()) {
       // If the LHS is an AND with the same constant, look through it.
       Value *LHS = nullptr;
       const APInt *LHSC;
       if (!match(Op0, m_And(m_Value(LHS), m_APInt(LHSC))) ||
           *LHSC != Op0KnownZeroInverted)
         LHS = Op0;
 
       Value *X;

llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp

assert(
       Known.getBitWidth() == BitWidth &&
       "Value *V, DemandedMask and Known must have same BitWidth");
 
   if (isa<Constant>(V)) {
     computeKnownBits(V, Known, Depth, CxtI);
     return nullptr;
   }
 
-  Known.Zero.clearAllBits();
-  Known.One.clearAllBits();
+  Known.resetAll();
   if (DemandedMask == 0)     // Not demanding any bits from V.
     return UndefValue::get(VTy);
 
   if (Depth == 6)        // Limit search depth.
     return nullptr;
 
   Instruction *I = dyn_cast<Instruction>(V);
   if (!I) {