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Differential D31849

[PowerPC] Eliminate compares - add i64 sext/zext handling
AbandonedPublic

Authored by nemanjai on Apr 8 2017, 10:07 AM.

Details

Reviewers
echristo
inouehrs
syzaara
kbarton
sfertile
jtony
hfinkel
lei
Summary

This patch provides functions that transform 64 bit compares into GPR sequences (both zero and sign-extended).

Diff Detail

Repository
rL LLVM

Event Timeline

nemanjai created this revision.Apr 8 2017, 10:07 AM
nemanjai added a parent revision: D31848: [PowerPC] Eliminate compares - add i32 sext/zext handling.
nemanjai added a child revision: D31850: [PowerPC] Eliminate compares - add handling for SELECT and SELECT_CC without the use of the condition register.Apr 8 2017, 10:10 AM
lei commandeered this revision.Apr 10 2017, 12:20 PM
lei edited reviewers, added: nemanjai; removed: lei.
nemanjai commandeered this revision.Apr 12 2017, 11:27 AM
nemanjai edited reviewers, added: lei; removed: nemanjai.
nemanjai edited edge metadata.

Temporarily commandeering this revision to update it with a more logical split of the original patch.

nemanjai updated this revision to Diff 95006.Apr 12 2017, 11:28 AM
nemanjai retitled this revision from [PowerPC] Eliminate compares in instruction selection - Vol. 3 to [PowerPC] Eliminate compares - add i64 sext/zext handling.
nemanjai edited the summary of this revision. (Show Details)
lei commandeered this revision.Apr 17 2017, 12:59 PM
lei removed a reviewer: lei.
nemanjai commandeered this revision.May 11 2017, 1:31 PM
nemanjai abandoned this revision.
nemanjai edited reviewers, added: lei; removed: nemanjai.

This is being split into smaller patches. Abandoning the large patch.

Revision Contents

PathSize
lib/
Target/
PowerPC/
223 lines

Diff 94599

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Show First 20 Lines • Show All 263 Lines • ▼ Show 20 Linesprivate:
SDValue signExtendInputIfNeeded(SDValue Input); SDValue signExtendInputIfNeeded(SDValue Input);
SDValue zeroExtendInputIfNeeded(SDValue Input); SDValue zeroExtendInputIfNeeded(SDValue Input);
SDValue addExtOrTrunc(SDValue NatWidthRes, bool From32Bit, SDValue addExtOrTrunc(SDValue NatWidthRes, bool From32Bit,
bool To32Bit); bool To32Bit);
SDValue getSETGE0I32InGPR(SDValue LHS, SDLoc dl, bool IsSext); SDValue getSETGE0I32InGPR(SDValue LHS, SDLoc dl, bool IsSext);
SDValue getSETGE0I64InGPR(SDValue LHS, SDLoc dl, bool IsSext); SDValue getSETGE0I64InGPR(SDValue LHS, SDLoc dl, bool IsSext);
SDValue getSETLE0I32InGPR(SDValue LHS, SDLoc dl, bool IsSext); SDValue getSETLE0I32InGPR(SDValue LHS, SDLoc dl, bool IsSext);
SDValue getSETLE0I64InGPR(SDValue LHS, SDLoc dl, bool IsSext); SDValue getSETLE0I64InGPR(SDValue LHS, SDLoc dl, bool IsSext);
SDValue get32BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
int64_t RHSValue, SDLoc dl);
SDValue get32BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
int64_t RHSValue, SDLoc dl);
void PeepholePPC64(); void PeepholePPC64();
void PeepholePPC64ZExt(); void PeepholePPC64ZExt();
void PeepholeCROps(); void PeepholeCROps();
SDValue combineToCMPB(SDNode *N); SDValue combineToCMPB(SDNode *N);
void foldBoolExts(SDValue &Res, SDNode *&N); void foldBoolExts(SDValue &Res, SDNode *&N);
▲ Show 20 Lines • Show All 2,346 Lines • ▼ Show 20 Lines SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
Addi, LHS), 0); Addi, LHS), 0);
if (IsSext) if (IsSext)
return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, Or, return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, Or,
getI64Imm(63, dl)), 0); getI64Imm(63, dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
Or, getI64Imm(1, dl), Or, getI64Imm(1, dl),
getI64Imm(63, dl)), 0); getI64Imm(63, dl)), 0);
} }
static void swapAndReset(SDValue &LHS, SDValue &RHS, bool &IsRHSZero,
bool &IsRHSOne, bool &IsRHSNegOne) {
std::swap(LHS, RHS);
ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
IsRHSZero = RHSConst && RHSConst->isNullValue();
IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
IsRHSNegOne = RHSConst && RHSConst->isAllOnesValue();
}
/// Produces a zero-extended result of comparing two 32-bit values according to
/// the passed condition code.
SDValue PPCDAGToDAGISel::get32BitZExtCompare(SDValue LHS, SDValue RHS,
ISD::CondCode CC,
int64_t RHSValue, SDLoc dl) {
bool IsRHSZero = RHSValue == 0;
bool IsRHSOne = RHSValue == 1;
bool IsRHSNegOne = RHSValue == -1LL;
switch (CC) {
default: llvm_unreachable("Unknown condition!");
case ISD::SETEQ: {
SDValue Xor = IsRHSZero ? LHS :
SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
SDValue Clz =
SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
SDValue ShiftOps[] = { Clz, getI32Imm(27, dl), getI32Imm(5, dl),
getI32Imm(31, dl) };
return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
ShiftOps), 0);
}
case ISD::SETNE: {
SDValue Xor = IsRHSZero ? LHS :
SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
SDValue Clz =
SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
SDValue ShiftOps[] = { Clz, getI32Imm(27, dl), getI32Imm(5, dl),
getI32Imm(31, dl) };
SDValue Shift =
SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0);
return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,
getI32Imm(1, dl)), 0);
}
case ISD::SETGE: {
if(IsRHSZero)
return getSETGE0I32InGPR(LHS, dl, false);
swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
LLVM_FALLTHROUGH;
}
case ISD::SETLE: {
SDValue SubOrNeg = IsRHSZero ?
SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, LHS), 0) :
SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, LHS, RHS), 0);
SDValue Shift =
SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32, SubOrNeg,
getI64Imm(1, dl), getI64Imm(63, dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::XORI, dl,
MVT::i32, Shift, getI32Imm(1, dl)), 0);
}
case ISD::SETGT: {
if (IsRHSNegOne)
return getSETGE0I32InGPR(LHS, dl, false);
if (IsRHSZero) {
SDValue Neg =
SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, LHS), 0);
return SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,
Neg, getI32Imm(1, dl), getI32Imm(63, dl)), 0);
}
swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
LLVM_FALLTHROUGH;
}
case ISD::SETLT: {
// Handle SETLT 1 (which is equivalent to SETLE 0)
if (IsRHSOne)
return getSETLE0I32InGPR(LHS, dl, false);
if (IsRHSZero) {
SDValue ShiftOps[] = { LHS, getI32Imm(1, dl), getI32Imm(31, dl),
getI32Imm(31, dl) };
return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
ShiftOps), 0);
}
SDValue SUBFNode =
SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, RHS, LHS), 0);
return SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,
SUBFNode, getI64Imm(1, dl),
getI64Imm(63, dl)), 0);
}
case ISD::SETUGE:
swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
LLVM_FALLTHROUGH;
case ISD::SETULE: {
SDValue Subtract =
SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, LHS, RHS), 0);
SDValue SrdiNode =
SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,
Subtract, getI64Imm(1, dl),
getI64Imm(63, dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, SrdiNode,
getI32Imm(1, dl)), 0);
}
case ISD::SETUGT:
swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
LLVM_FALLTHROUGH;
case ISD::SETULT: {
// FIXME: This is converted upstream to a shift/subtract sequence that
// does excessive zero extension/truncation for i8 and i16.
SDValue Subtract =
SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, RHS, LHS), 0);
return SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,
Subtract, getI64Imm(1, dl),
getI64Imm(63, dl)), 0);
}
}
}
/// Produces a sign-extended result of comparing two 32-bit values according to
/// the passed condition code.
SDValue PPCDAGToDAGISel::get32BitSExtCompare(SDValue LHS, SDValue RHS,
ISD::CondCode CC,
int64_t RHSValue, SDLoc dl) {
bool IsRHSZero = RHSValue == 0;
bool IsRHSOne = RHSValue == 1;
bool IsRHSNegOne = RHSValue == -1LL;
switch (CC) {
default: llvm_unreachable("Unknown condition!");
case ISD::SETEQ: {
SDValue CountInput = IsRHSZero ? LHS :
SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
SDValue Cntlzw =
SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, CountInput), 0);
SDValue LSHROps[] =
{ Cntlzw, getI32Imm(27, dl), getI32Imm(5, dl), getI32Imm(31, dl) };
SDValue Srwi =
SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, LSHROps), 0);
SDValue SHLOps[] = { Srwi, getI32Imm(63, dl), getI32Imm(0, dl) };
SDValue Sldi =
SDValue(CurDAG->getMachineNode(PPC::RLDICR_32, dl, MVT::i32, SHLOps), 0);
return SDValue(CurDAG->getMachineNode(PPC::SRADI_32, dl, MVT::i32, Sldi,
getI32Imm(63, dl)), 0);
}
case ISD::SETNE: {
SDValue Xor = IsRHSZero ? LHS :
SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
SDValue Clz =
SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
SDValue ShiftOps[] =
{ Clz, getI32Imm(27, dl), getI32Imm(5, dl), getI32Imm(31, dl) };
SDValue Shift =
SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0);
SDValue Xori =
SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,
getI32Imm(1, dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Xori), 0);
}
case ISD::SETGE: {
if(IsRHSZero)
return getSETGE0I32InGPR(LHS, dl, true);
swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
LLVM_FALLTHROUGH;
}
case ISD::SETLE: {
if (IsRHSZero)
return getSETLE0I32InGPR(LHS, dl, true);
SDValue SUBFNode =
SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, MVT::Glue,
LHS, RHS), 0);
SDValue Srdi =
SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32, MVT::Glue,
SUBFNode, getI64Imm(1, dl),
getI64Imm(63, dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Srdi,
getI32Imm(-1, dl)), 0);
}
case ISD::SETGT: {
if (IsRHSNegOne)
return getSETGE0I32InGPR(LHS, dl, true);
if (IsRHSZero) {
SDValue Neg =
SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, LHS), 0);
return SDValue(CurDAG->getMachineNode(PPC::SRADI_32, dl, MVT::i32, Neg,
getI64Imm(63, dl)), 0);
}
swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
LLVM_FALLTHROUGH;
}
case ISD::SETLT: {
if (IsRHSOne)
return getSETLE0I32InGPR(LHS, dl, true);
if (IsRHSZero)
return SDValue(CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, LHS,
getI32Imm(31, dl)), 0);
SDValue SUBFNode =
SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, RHS, LHS), 0);
return SDValue(CurDAG->getMachineNode(PPC::SRADI_32, dl, MVT::i32,
SUBFNode, getI64Imm(63, dl)), 0);
}
case ISD::SETUGE:
swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
LLVM_FALLTHROUGH;
case ISD::SETULE: {
SDValue Subtract =
SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, LHS, RHS), 0);
SDValue Shift =
SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32, Subtract,
getI32Imm(1, dl), getI32Imm(63,dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Shift,
getI32Imm(-1, dl)), 0);
}
case ISD::SETUGT:
swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
LLVM_FALLTHROUGH;
case ISD::SETULT: {
SDValue Subtract =
SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, RHS, LHS), 0);
return SDValue(CurDAG->getMachineNode(PPC::SRADI_32, dl, MVT::i32,
Subtract, getI64Imm(63, dl)), 0);
}
}
}
void PPCDAGToDAGISel::transferMemOperands(SDNode *N, SDNode *Result) { void PPCDAGToDAGISel::transferMemOperands(SDNode *N, SDNode *Result) {
// Transfer memoperands. // Transfer memoperands.
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
MemOp[0] = cast<MemSDNode>(N)->getMemOperand(); MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1); cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
} }
// Select - Convert the specified operand from a target-independent to a // Select - Convert the specified operand from a target-independent to a
▲ Show 20 Lines • Show All 2,111 Lines • Show Last 20 Lines