Fix signed multiplication with overflow fallback.

[jamesduley]

Summary

For targets that don't have ISD::MULHS or ISD::SMUL_LOHI for the type
and the double width type is illegal, then the two operands are
sign extended to twice their size then multiplied to check for overflow.
The extended upper halves were mismatched causing an incorrect result.
This fixes the mismatch.

A test was added for ARM V6-M where the bug was detected.

Original bug report here https://github.com/rust-lang/rust/issues/39056

[ab]

Nice catch, LGTM.

Looks like this should already be exercised by test/CodeGen/ARM/umulo-32.ll; I'd say remove that file entirely.

test/CodeGen/ARM/v6m-smul-with-overflow.ll

3 ↗

(On Diff #94512)

Remove 'unnamed_addr' ?

[jamesduley]

removed unnamed_addr

[jamesduley]

Looks like this should already be exercised by test/CodeGen/ARM/umulo-32.ll; I'd say remove that file entirely.

That's testing unsigned though, so shouldn't I leave it?

[rs]

Looks fine, I think it's ready to land. Do you have commit access ? If not do you want me to commit on your behalf ?

[jamesduley]

In D31807#738030, @rs wrote:

Looks fine, I think it's ready to land. Do you have commit access ? If not do you want me to commit on your behalf ?

No, I don't so yes please.

llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
       else if (WideVT == MVT::i128)
         LC = RTLIB::MUL_I128;
       assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
 
       // The high part is obtained by SRA'ing all but one of the bits of low
       // part.
       unsigned LoSize = VT.getSizeInBits();
       SDValue HiLHS =
-          DAG.getNode(ISD::SRA, dl, VT, RHS,
+          DAG.getNode(ISD::SRA, dl, VT, LHS,
                       DAG.getConstant(LoSize - 1, dl,
                                       TLI.getPointerTy(DAG.getDataLayout())));
       SDValue HiRHS =
-          DAG.getNode(ISD::SRA, dl, VT, LHS,
+          DAG.getNode(ISD::SRA, dl, VT, RHS,
                       DAG.getConstant(LoSize - 1, dl,
                                       TLI.getPointerTy(DAG.getDataLayout())));
 
       // Here we're passing the 2 arguments explicitly as 4 arguments that are
       // pre-lowered to the correct types. This all depends upon WideVT not
       // being a legal type for the architecture and thus has to be split to
       // two arguments.
       SDValue Ret;

llvm/trunk/test/CodeGen/ARM/v6m-smul-with-overflow.ll

+; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s
+
+define i1 @signed_multiplication_did_overflow(i32, i32) {
+; CHECK-LABEL: signed_multiplication_did_overflow:
+entry-block:
+  %2 = tail call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %0, i32 %1)
+  %3 = extractvalue { i32, i1 } %2, 1
+  ret i1 %3
+
+; CHECK: mov    r2, r1
+; CHECK: asrs   r1, r0, #31
+; CHECK: asrs   r3, r2, #31
+; CHECK: bl     __aeabi_lmul
+}
+
+declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32)