[PowerPC] MachineSSA pass to reduce the number of CR-logical operations

[nemanjai]

Summary

This is an initial attempt at a pass that will traverse the machine code while still in SSA form and attempt various transformations aimed at reducing the number of CR-logical operations. The only support provided by the initial patch is for splitting basic blocks on binary CR-logical operations (i.e. branch early on operands). The hope however is that the provided infrastructure will allow for further transformations that can reduce the number of these operations.

[echristo]

How does this work on the testcases that hfinkel added in PR32320?

-eric

[nemanjai]

In D30431#711695, @echristo wrote:

How does this work on the testcases that hfinkel added in PR32320?

-eric

I plan to run those to try to get reliable performance data to motivate heuristics for this pass. I'll do that after the dev conference and report the impact of this patch on those.

[jtony]

lib/Target/PowerPC/PPCMachineBasicBlockUtils.h

93 ↗

(On Diff #89942)

It looks to me this static function uses too many parameters, which makes it a little bit hard to understand. Is it possible for us to reduce the number of parameters used here? One way I could think of is to make this a member function of class PPCReduceCRLogicals. In that case we could make some of the parameters member of the class, so that we don't have to pass them around. But it is totally up to you to decide whether the effort is worthwhile or not.

lib/Target/PowerPC/PPCReduceCRLogicals.cpp

220 ↗

(On Diff #89942)

Can we do what the FIXME suggested here in this patch? Since the community doesn't like us putting FIXME in the code.

[nemanjai]

lib/Target/PowerPC/PPCMachineBasicBlockUtils.h

93 ↗

(On Diff #89942)

I don't want to make it a member variable as I think this is useful for other purposes than just this pass. However, I think it might be useful to wrap all the parameters into a struct that we'll build up and pass.

lib/Target/PowerPC/PPCReduceCRLogicals.cpp

220 ↗

(On Diff #89942)

I meant to remove this FIXME. Thanks for pointing it out.

[nemanjai]

• Rebase
• Fix test cases that fail on ToT
• Simplify the split function signature
• Add the input CR logical instructions back to the queue if we split on the use

[nemanjai]

Some performance numbers as requested by @echristo (all run on a Power8 2GHz machine, bound to a specific physical CPU):
SPEC2006 (run time improvements - negative is good):
444.namd,868.7807,0.0000,850.4903,0.0000,-2.11%
447.dealII,630.6040,0.0000,631.2014,0.0000,0.09%
450.soplex,473.6103,0.0000,417.0427,0.0000,-11.94%
453.povray,505.4464,0.0000,487.0534,0.0000,-3.64%
401.bzip2,969.0608,0.0000,923.7337,0.0000,-4.68%
445.gobmk,868.6733,0.0000,857.6179,0.0000,-1.27%
464.h264ref,1053.8501,0.0000,1005.3811,0.0000,-4.60%
471.omnetpp,473.8660,0.0000,444.2557,0.0000,-6.25%
Changes below 1% omitted.
This was from a single run of SPEC2016 with r319300 and then same revision with this patch applied. Since it was a single run, I don't have information about the noise range, but the important thing is that the trend seems to be rather clear - performance improves with this patch.

For Hal's benchmarks, the relative performance doesn't change almost at all with this patch. The absolute performance improves with 4,3,float, 4,4,float by about 30% and degrades with 4,4,int by about 20%. The rest are unchanged.

[echristo]

In D30431#940296, @nemanjai wrote:

Some performance numbers as requested by @echristo (all run on a Power8 2GHz machine, bound to a specific physical CPU):
SPEC2006 (run time improvements - negative is good):
444.namd,868.7807,0.0000,850.4903,0.0000,-2.11%
447.dealII,630.6040,0.0000,631.2014,0.0000,0.09%
450.soplex,473.6103,0.0000,417.0427,0.0000,-11.94%
453.povray,505.4464,0.0000,487.0534,0.0000,-3.64%
401.bzip2,969.0608,0.0000,923.7337,0.0000,-4.68%
445.gobmk,868.6733,0.0000,857.6179,0.0000,-1.27%
464.h264ref,1053.8501,0.0000,1005.3811,0.0000,-4.60%
471.omnetpp,473.8660,0.0000,444.2557,0.0000,-6.25%
Changes below 1% omitted.
This was from a single run of SPEC2016 with r319300 and then same revision with this patch applied. Since it was a single run, I don't have information about the noise range, but the important thing is that the trend seems to be rather clear - performance improves with this patch.

Quite.

For Hal's benchmarks, the relative performance doesn't change almost at all with this patch. The absolute performance improves with 4,3,float, 4,4,float by about 30% and degrades with 4,4,int by about 20%. The rest are unchanged.

Weird.

Anyhow, I'm ok with this.

llvm/trunk/lib/Target/PowerPC/CMakeLists.txt

add_llvm_target(PowerPCCodeGen
   PPCQPXLoadSplat.cpp
   PPCSubtarget.cpp
   PPCTargetMachine.cpp
   PPCTargetObjectFile.cpp
   PPCTargetTransformInfo.cpp
   PPCTOCRegDeps.cpp
   PPCTLSDynamicCall.cpp
   PPCVSXCopy.cpp
+  PPCReduceCRLogicals.cpp
   PPCVSXFMAMutate.cpp
   PPCVSXSwapRemoval.cpp
   PPCExpandISEL.cpp
   )
 
 add_subdirectory(AsmParser)
 add_subdirectory(Disassembler)
 add_subdirectory(InstPrinter)
 add_subdirectory(TargetInfo)
 add_subdirectory(MCTargetDesc)

llvm/trunk/lib/Target/PowerPC/PPC.h

#ifndef NDEBUG
   FunctionPass *createPPCCTRLoopsVerify();
 #endif
   FunctionPass *createPPCLoopPreIncPrepPass(PPCTargetMachine &TM);
   FunctionPass *createPPCTOCRegDepsPass();
   FunctionPass *createPPCEarlyReturnPass();
   FunctionPass *createPPCVSXCopyPass();
   FunctionPass *createPPCVSXFMAMutatePass();
   FunctionPass *createPPCVSXSwapRemovalPass();
+  FunctionPass *createPPCReduceCRLogicalsPass();
   FunctionPass *createPPCMIPeepholePass();
   FunctionPass *createPPCBranchSelectionPass();
   FunctionPass *createPPCBranchCoalescingPass();
   FunctionPass *createPPCQPXLoadSplatPass();
   FunctionPass *createPPCISelDag(PPCTargetMachine &TM, CodeGenOpt::Level OL);
   FunctionPass *createPPCTLSDynamicCallPass();
   FunctionPass *createPPCBoolRetToIntPass();
   FunctionPass *createPPCExpandISELPass();

llvm/trunk/lib/Target/PowerPC/PPCMachineBasicBlockUtils.h

+//==-- PPCMachineBasicBlockUtils.h - Functions for common MBB operations ---==//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines utility functions for commonly used operations on
+// MachineBasicBlock's.
+// NOTE: Include this file after defining DEBUG_TYPE so that the debug messages
+//       can be emitted for the pass that is using this.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_PPC_MACHINE_BASIC_BLOCK_UTILS_H
+#define LLVM_LIB_TARGET_PPC_MACHINE_BASIC_BLOCK_UTILS_H
+
+#include "PPCInstrInfo.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+
+#ifndef DEBUG_TYPE
+#define DEBUG_TYPE "ppc-generic-mbb-utilities"
+#endif
+
+using namespace llvm;
+
+/// Given a basic block \p Successor that potentially contains PHIs, this
+/// function will look for any incoming values in the PHIs that are supposed to
+/// be coming from \p OrigMBB but whose definition is actually in \p NewMBB.
+/// Any such PHIs will be updated to reflect reality.
+static void updatePHIs(MachineBasicBlock *Successor, MachineBasicBlock *OrigMBB,
+                       MachineBasicBlock *NewMBB, MachineRegisterInfo *MRI) {
+  for (auto &MI : Successor->instrs()) {
+    if (!MI.isPHI())
+      continue;
+    // This is a really ugly-looking loop, but it was pillaged directly from
+    // MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
+    for (unsigned i = 2, e = MI.getNumOperands()+1; i != e; i += 2) {
+      MachineOperand &MO = MI.getOperand(i);
+      if (MO.getMBB() == OrigMBB) {
+        // Check if the instruction is actualy defined in NewMBB.
+        if (MI.getOperand(i-1).isReg()) {
+          MachineInstr *DefMI = MRI->getVRegDef(MI.getOperand(i-1).getReg());
+          if (DefMI->getParent() == NewMBB || !OrigMBB->isSuccessor(Successor)) {
+            MO.setMBB(NewMBB);
+            break;
+          }
+        }
+      }
+    }
+  }
+}
+
+/// Given a basic block \p Successor that potentially contains PHIs, this
+/// function will look for PHIs that have an incoming value from \p OrigMBB
+/// and will add the same incoming value from \p NewMBB.
+/// NOTE: This should only be used if \p NewMBB is an immediate dominator of
+/// \p OrigMBB.
+static void addIncomingValuesToPHIs(MachineBasicBlock *Successor,
+                                    MachineBasicBlock *OrigMBB,
+                                    MachineBasicBlock *NewMBB,
+                                    MachineRegisterInfo *MRI) {
+  assert(OrigMBB->isSuccessor(NewMBB) && "NewMBB must be a sucessor of OrigMBB");
+  for (auto &MI : Successor->instrs()) {
+    if (!MI.isPHI())
+      continue;
+    // This is a really ugly-looking loop, but it was pillaged directly from
+    // MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
+    for (unsigned i = 2, e = MI.getNumOperands()+1; i != e; i += 2) {
+      MachineOperand &MO = MI.getOperand(i);
+      if (MO.getMBB() == OrigMBB) {
+        MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI);
+        MIB.addReg(MI.getOperand(i-1).getReg()).addMBB(NewMBB);
+        break;
+      }
+    }
+  }
+}
+
+struct BlockSplitInfo {
+  MachineInstr *OrigBranch;
+  MachineInstr *SplitBefore;
+  MachineInstr *SplitCond;
+  bool InvertNewBranch;
+  bool InvertOrigBranch;
+  bool BranchToFallThrough;
+  const MachineBranchProbabilityInfo *MBPI;
+  MachineInstr *MIToDelete;
+  MachineInstr *NewCond;
+  bool allInstrsInSameMBB() {
+    if (!OrigBranch || !SplitBefore || !SplitCond)
+      return false;
+    MachineBasicBlock *MBB = OrigBranch->getParent();
+    if (SplitBefore->getParent() != MBB ||
+        SplitCond->getParent() != MBB)
+      return false;
+    if (MIToDelete && MIToDelete->getParent() != MBB)
+      return false;
+    if (NewCond && NewCond->getParent() != MBB)
+      return false;
+    return true;
+  }
+};
+
+/// Splits a MachineBasicBlock to branch before \p SplitBefore. The original
+/// branch is \p OrigBranch. The target of the new branch can either be the same
+/// as the target of the original branch or the fallthrough successor of the
+/// original block as determined by \p BranchToFallThrough. The branch
+/// conditions will be inverted according to \p InvertNewBranch and
+/// \p InvertOrigBranch. If an instruction that previously fed the branch is to
+/// be deleted, it is provided in \p MIToDelete and \p NewCond will be used as
+/// the branch condition. The branch probabilities will be set if the
+/// MachineBranchProbabilityInfo isn't null.
+static bool splitMBB(BlockSplitInfo &BSI) {
+  assert(BSI.allInstrsInSameMBB() &&
+         "All instructions must be in the same block.");
+
+  MachineBasicBlock *ThisMBB = BSI.OrigBranch->getParent();
+  MachineFunction *MF = ThisMBB->getParent();
+  MachineRegisterInfo *MRI = &MF->getRegInfo();
+  assert(MRI->isSSA() && "Can only do this while the function is in SSA form.");
+  if (ThisMBB->succ_size() != 2) {
+    DEBUG(dbgs() << "Don't know how to handle blocks that don't have exactly"
+                 << " two succesors.\n");
+    return false;
+  }
+
+  const PPCInstrInfo *TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
+  unsigned OrigBROpcode = BSI.OrigBranch->getOpcode();
+  unsigned InvertedOpcode =
+    OrigBROpcode == PPC::BC ? PPC::BCn :
+    OrigBROpcode == PPC::BCn ? PPC::BC :
+    OrigBROpcode == PPC::BCLR ? PPC::BCLRn : PPC::BCLR;
+  unsigned NewBROpcode = BSI.InvertNewBranch ? InvertedOpcode : OrigBROpcode;
+  MachineBasicBlock *OrigTarget = BSI.OrigBranch->getOperand(1).getMBB();
+  MachineBasicBlock *OrigFallThrough =
+    OrigTarget == *ThisMBB->succ_begin() ? *ThisMBB->succ_rbegin() :
+    *ThisMBB->succ_begin();
+  MachineBasicBlock *NewBRTarget =
+    BSI.BranchToFallThrough ? OrigFallThrough : OrigTarget;
+  BranchProbability ProbToNewTarget =
+    !BSI.MBPI ? BranchProbability::getUnknown() :
+    BSI.MBPI->getEdgeProbability(ThisMBB, NewBRTarget);
+
+  // Create a new basic block.
+  MachineBasicBlock::iterator InsertPoint = BSI.SplitBefore;
+  const BasicBlock *LLVM_BB = ThisMBB->getBasicBlock();
+  MachineFunction::iterator It = ThisMBB->getIterator();
+  MachineBasicBlock *NewMBB = MF->CreateMachineBasicBlock(LLVM_BB);
+  MF->insert(++It, NewMBB);
+
+  // Move everything after SplitBefore into the new block.
+  NewMBB->splice(NewMBB->end(), ThisMBB, InsertPoint, ThisMBB->end());
+  NewMBB->transferSuccessors(ThisMBB);
+
+  // Add the two successors to ThisMBB. The probabilities come from the
+  // existing blocks if available.
+  ThisMBB->addSuccessor(NewBRTarget, ProbToNewTarget);
+  ThisMBB->addSuccessor(NewMBB, ProbToNewTarget.getCompl());
+
+  // Add the branches to ThisMBB.
+  BuildMI(*ThisMBB, ThisMBB->end(), BSI.SplitBefore->getDebugLoc(),
+          TII->get(NewBROpcode)).addReg(BSI.SplitCond->getOperand(0).getReg())
+          .addMBB(NewBRTarget);
+  BuildMI(*ThisMBB, ThisMBB->end(), BSI.SplitBefore->getDebugLoc(),
+          TII->get(PPC::B)).addMBB(NewMBB);
+  if (BSI.MIToDelete)
+    BSI.MIToDelete->eraseFromParent();
+
+  // Change the condition on the original branch and invert it if requested.
+  auto FirstTerminator = NewMBB->getFirstTerminator();
+  if (BSI.NewCond) {
+    assert(FirstTerminator->getOperand(0).isReg() &&
+           "Can't update condition of unconditional branch.");
+    FirstTerminator->getOperand(0).setReg(BSI.NewCond->getOperand(0).getReg());
+  }
+  if (BSI.InvertOrigBranch)
+    FirstTerminator->setDesc(TII->get(InvertedOpcode));
+
+  // If any of the PHIs in the successors of NewMBB reference values that
+  // now come from NewMBB, they need to be updated.
+  for (auto *Succ : NewMBB->successors()) {
+    updatePHIs(Succ, ThisMBB, NewMBB, MRI);
+  }
+  addIncomingValuesToPHIs(NewBRTarget, ThisMBB, NewMBB, MRI);
+
+  DEBUG(dbgs() << "After splitting, ThisMBB:\n"; ThisMBB->dump());
+  DEBUG(dbgs() << "NewMBB:\n"; NewMBB->dump());
+  DEBUG(dbgs() << "New branch-to block:\n"; NewBRTarget->dump());
+  return true;
+}
+
+
+#endif

llvm/trunk/lib/Target/PowerPC/PPCReduceCRLogicals.cpp

+//===---- PPCReduceCRLogicals.cpp - Reduce CR Bit Logical operations ------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===---------------------------------------------------------------------===//
+//
+// This pass aims to reduce the number of logical operations on bits in the CR
+// register. These instructions have a fairly high latency and only a single
+// pipeline at their disposal in modern PPC cores. Furthermore, they have a
+// tendency to occur in fairly small blocks where there's little opportunity
+// to hide the latency between the CR logical operation and its user.
+//
+//===---------------------------------------------------------------------===//
+
+#include "PPCInstrInfo.h"
+#include "PPC.h"
+#include "PPCTargetMachine.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/ADT/Statistic.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "ppc-reduce-cr-ops"
+#include "PPCMachineBasicBlockUtils.h"
+
+STATISTIC(NumContainedSingleUseBinOps,
+          "Number of single-use binary CR logical ops contained in a block");
+STATISTIC(NumToSplitBlocks,
+          "Number of binary CR logical ops that can be used to split blocks");
+STATISTIC(TotalCRLogicals, "Number of CR logical ops.");
+STATISTIC(TotalNullaryCRLogicals,
+          "Number of nullary CR logical ops (CRSET/CRUNSET).");
+STATISTIC(TotalUnaryCRLogicals, "Number of unary CR logical ops.");
+STATISTIC(TotalBinaryCRLogicals, "Number of CR logical ops.");
+STATISTIC(NumBlocksSplitOnBinaryCROp,
+          "Number of blocks split on CR binary logical ops.");
+STATISTIC(NumNotSplitIdenticalOperands,
+          "Number of blocks not split due to operands being identical.");
+STATISTIC(NumNotSplitChainCopies,
+          "Number of blocks not split due to operands being chained copies.");
+STATISTIC(NumNotSplitWrongOpcode,
+          "Number of blocks not split due to the wrong opcode.");
+
+namespace llvm {
+  void initializePPCReduceCRLogicalsPass(PassRegistry&);
+}
+
+namespace {
+
+static bool isBinary(MachineInstr &MI) {
+  return MI.getNumOperands() == 3;
+}
+
+static bool isNullary(MachineInstr &MI) {
+  return MI.getNumOperands() == 1;
+}
+
+/// Given a CR logical operation \p CROp, branch opcode \p BROp as well as
+/// a flag to indicate if the first operand of \p CROp is used as the
+/// SplitBefore operand, determines whether either of the branches are to be
+/// inverted as well as whether the new target should be the original
+/// fall-through block.
+static void
+computeBranchTargetAndInversion(unsigned CROp, unsigned BROp, bool UsingDef1,
+                                bool &InvertNewBranch, bool &InvertOrigBranch,
+                                bool &TargetIsFallThrough) {
+  // The conditions under which each of the output operands should be [un]set
+  // can certainly be written much more concisely with just 3 if statements or
+  // ternary expressions. However, this provides a much clearer overview to the
+  // reader as to what is set for each <CROp, BROp, OpUsed> combination.
+  if (BROp == PPC::BC || BROp == PPC::BCLR) {
+    // Regular branches.
+    switch (CROp) {
+    default:
+      llvm_unreachable("Don't know how to handle this CR logical.");
+    case PPC::CROR:
+      InvertNewBranch = false;
+      InvertOrigBranch = false;
+      TargetIsFallThrough = false;
+      return;
+    case PPC::CRAND:
+      InvertNewBranch = true;
+      InvertOrigBranch = false;
+      TargetIsFallThrough = true;
+      return;
+    case PPC::CRNAND:
+      InvertNewBranch = true;
+      InvertOrigBranch = true;
+      TargetIsFallThrough = false;
+      return;
+    case PPC::CRNOR:
+      InvertNewBranch = false;
+      InvertOrigBranch = true;
+      TargetIsFallThrough = true;
+      return;
+    case PPC::CRORC:
+      InvertNewBranch = UsingDef1;
+      InvertOrigBranch = !UsingDef1;
+      TargetIsFallThrough = false;
+      return;
+    case PPC::CRANDC:
+      InvertNewBranch = !UsingDef1;
+      InvertOrigBranch = !UsingDef1;
+      TargetIsFallThrough = true;
+      return;
+    }
+  } else if (BROp == PPC::BCn || BROp == PPC::BCLRn) {
+    // Negated branches.
+    switch (CROp) {
+    default:
+      llvm_unreachable("Don't know how to handle this CR logical.");
+    case PPC::CROR:
+      InvertNewBranch = true;
+      InvertOrigBranch = false;
+      TargetIsFallThrough = true;
+      return;
+    case PPC::CRAND:
+      InvertNewBranch = false;
+      InvertOrigBranch = false;
+      TargetIsFallThrough = false;
+      return;
+    case PPC::CRNAND:
+      InvertNewBranch = false;
+      InvertOrigBranch = true;
+      TargetIsFallThrough = true;
+      return;
+    case PPC::CRNOR:
+      InvertNewBranch = true;
+      InvertOrigBranch = true;
+      TargetIsFallThrough = false;
+      return;
+    case PPC::CRORC:
+      InvertNewBranch = !UsingDef1;
+      InvertOrigBranch = !UsingDef1;
+      TargetIsFallThrough = true;
+      return;
+    case PPC::CRANDC:
+      InvertNewBranch = UsingDef1;
+      InvertOrigBranch = !UsingDef1;
+      TargetIsFallThrough = false;
+      return;
+    }
+  } else
+    llvm_unreachable("Don't know how to handle this branch.");
+}
+
+class PPCReduceCRLogicals : public MachineFunctionPass {
+
+public:
+  static char ID;
+  struct CRLogicalOpInfo {
+    MachineInstr *MI;
+    // FIXME: If chains of copies are to be handled, this should be a vector.
+    std::pair<MachineInstr*, MachineInstr*> CopyDefs;
+    std::pair<MachineInstr*, MachineInstr*> TrueDefs;
+    unsigned IsBinary : 1;
+    unsigned IsNullary : 1;
+    unsigned ContainedInBlock : 1;
+    unsigned FeedsISEL : 1;
+    unsigned FeedsBR : 1;
+    unsigned FeedsLogical : 1;
+    unsigned SingleUse : 1;
+    unsigned DefsSingleUse : 1;
+    unsigned SubregDef1;
+    unsigned SubregDef2;
+    CRLogicalOpInfo() : MI(nullptr), IsBinary(0), IsNullary(0),
+                        ContainedInBlock(0), FeedsISEL(0), FeedsBR(0),
+                        FeedsLogical(0), SingleUse(0), DefsSingleUse(1),
+                        SubregDef1(0), SubregDef2(0) { }
+    void dump();
+  };
+
+private:
+  const PPCInstrInfo *TII;
+  MachineFunction *MF;
+  MachineRegisterInfo *MRI;
+  const MachineBranchProbabilityInfo *MBPI;
+
+  // A vector to contain all the CR logical operations
+  std::vector<CRLogicalOpInfo> AllCRLogicalOps;
+  void initialize(MachineFunction &MFParm);
+  void collectCRLogicals();
+  bool handleCROp(CRLogicalOpInfo &CRI);
+  bool splitBlockOnBinaryCROp(CRLogicalOpInfo &CRI);
+  static bool isCRLogical(MachineInstr &MI) {
+    unsigned Opc = MI.getOpcode();
+    return Opc == PPC::CRAND || Opc == PPC::CRNAND || Opc == PPC::CROR ||
+      Opc == PPC::CRXOR || Opc == PPC::CRNOR || Opc == PPC::CREQV ||
+      Opc == PPC::CRANDC || Opc == PPC::CRORC || Opc == PPC::CRSET ||
+      Opc == PPC::CRUNSET || Opc == PPC::CR6SET || Opc == PPC::CR6UNSET;
+  }
+  bool simplifyCode() {
+    bool Changed = false;
+    // Not using a range-based for loop here as the vector may grow while being
+    // operated on.
+    for (unsigned i = 0; i < AllCRLogicalOps.size(); i++)
+      Changed |= handleCROp(AllCRLogicalOps[i]);
+    return Changed;
+  }
+
+public:
+  PPCReduceCRLogicals() : MachineFunctionPass(ID) {
+    initializePPCReduceCRLogicalsPass(*PassRegistry::getPassRegistry());
+  }
+
+  MachineInstr *lookThroughCRCopy(unsigned Reg, unsigned &Subreg,
+                                  MachineInstr *&CpDef);
+  bool runOnMachineFunction(MachineFunction &MF) override {
+    if (skipFunction(*MF.getFunction()))
+      return false;
+
+    // If the subtarget doesn't use CR bits, there's nothing to do.
+    const PPCSubtarget &STI = MF.getSubtarget<PPCSubtarget>();
+    if (!STI.useCRBits())
+      return false;
+
+    initialize(MF);
+    collectCRLogicals();
+    return simplifyCode();
+  }
+  CRLogicalOpInfo createCRLogicalOpInfo(MachineInstr &MI);
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.addRequired<MachineBranchProbabilityInfo>();
+    AU.addRequired<MachineDominatorTree>();
+    MachineFunctionPass::getAnalysisUsage(AU);
+  }
+};
+
+void PPCReduceCRLogicals::CRLogicalOpInfo::dump() {
+  dbgs() << "CRLogicalOpMI: ";
+  MI->dump();
+  dbgs() << "IsBinary: " << IsBinary << ", FeedsISEL: " << FeedsISEL;
+  dbgs() << ", FeedsBR: " << FeedsBR << ", FeedsLogical: ";
+  dbgs() << FeedsLogical << ", SingleUse: " << SingleUse;
+  dbgs() << ", DefsSingleUse: " << DefsSingleUse;
+  dbgs() << ", SubregDef1: " << SubregDef1 << ", SubregDef2: ";
+  dbgs() << SubregDef2 << ", ContainedInBlock: " << ContainedInBlock;
+  if (!IsNullary) {
+    dbgs() << "\nDefs:\n";
+    TrueDefs.first->dump();
+  }
+  if (IsBinary)
+    TrueDefs.second->dump();
+  dbgs() << "\n";
+  if (CopyDefs.first) {
+    dbgs() << "CopyDef1: ";
+    CopyDefs.first->dump();
+  }
+  if (CopyDefs.second) {
+    dbgs() << "CopyDef2: ";
+    CopyDefs.second->dump();
+  }
+}
+
+PPCReduceCRLogicals::CRLogicalOpInfo
+PPCReduceCRLogicals::createCRLogicalOpInfo(MachineInstr &MIParam) {
+  CRLogicalOpInfo Ret;
+  Ret.MI = &MIParam;
+  // Get the defs
+  if (isNullary(MIParam)) {
+    Ret.IsNullary = 1;
+    Ret.TrueDefs = std::make_pair(nullptr, nullptr);
+    Ret.CopyDefs = std::make_pair(nullptr, nullptr);
+  } else {
+    MachineInstr *Def1 = lookThroughCRCopy(MIParam.getOperand(1).getReg(),
+                                           Ret.SubregDef1, Ret.CopyDefs.first);
+    Ret.DefsSingleUse &=
+      MRI->hasOneNonDBGUse(Def1->getOperand(0).getReg());
+    Ret.DefsSingleUse &=
+      MRI->hasOneNonDBGUse(Ret.CopyDefs.first->getOperand(0).getReg());
+    assert(Def1 && "Must be able to find a definition of operand 1.");
+    if (isBinary(MIParam)) {
+      Ret.IsBinary = 1;
+      MachineInstr *Def2 = lookThroughCRCopy(MIParam.getOperand(2).getReg(),
+                                             Ret.SubregDef2,
+                                             Ret.CopyDefs.second);
+      Ret.DefsSingleUse &=
+        MRI->hasOneNonDBGUse(Def2->getOperand(0).getReg());
+      Ret.DefsSingleUse &=
+        MRI->hasOneNonDBGUse(Ret.CopyDefs.second->getOperand(0).getReg());
+      assert(Def2 && "Must be able to find a definition of operand 2.");
+      Ret.TrueDefs = std::make_pair(Def1, Def2);
+    } else {
+      Ret.TrueDefs = std::make_pair(Def1, nullptr);
+      Ret.CopyDefs.second = nullptr;
+    }
+  }
+
+  Ret.ContainedInBlock = 1;
+  // Get the uses
+  for (MachineInstr &UseMI :
+       MRI->use_nodbg_instructions(MIParam.getOperand(0).getReg())) {
+    unsigned Opc = UseMI.getOpcode();
+    if (Opc == PPC::ISEL || Opc == PPC::ISEL8)
+      Ret.FeedsISEL = 1;
+    if (Opc == PPC::BC || Opc == PPC::BCn || Opc == PPC::BCLR ||
+        Opc == PPC::BCLRn)
+      Ret.FeedsBR = 1;
+    Ret.FeedsLogical = isCRLogical(UseMI);
+    if (UseMI.getParent() != MIParam.getParent())
+      Ret.ContainedInBlock = 0;
+  }
+  Ret.SingleUse = MRI->hasOneNonDBGUse(MIParam.getOperand(0).getReg()) ? 1 : 0;
+
+  // We now know whether all the uses of the CR logical are in the same block.
+  if (!Ret.IsNullary) {
+    Ret.ContainedInBlock &=
+      (MIParam.getParent() == Ret.TrueDefs.first->getParent());
+    if (Ret.IsBinary)
+      Ret.ContainedInBlock &=
+        (MIParam.getParent() == Ret.TrueDefs.second->getParent());
+  }
+  DEBUG(Ret.dump());
+  if (Ret.IsBinary && Ret.ContainedInBlock && Ret.SingleUse) {
+    NumContainedSingleUseBinOps++;
+    if (Ret.FeedsBR && Ret.DefsSingleUse)
+      NumToSplitBlocks++;
+  }
+  return Ret;
+}
+
+/// Looks trhough a COPY instruction to the actual definition of the CR-bit
+/// register and returns the instruction that defines it.
+/// FIXME: This currently handles what is by-far the most common case:
+/// an instruction that defines a CR field followed by a single copy of a bit
+/// from that field into a virtual register. If chains of copies need to be
+/// handled, this should have a loop until a non-copy instruction is found.
+MachineInstr *PPCReduceCRLogicals::lookThroughCRCopy(unsigned Reg,
+                                                     unsigned &Subreg,
+                                                     MachineInstr *&CpDef) {
+  Subreg = -1;
+  if (!TargetRegisterInfo::isVirtualRegister(Reg))
+    return nullptr;
+  MachineInstr *Copy = MRI->getVRegDef(Reg);
+  CpDef = Copy;
+  if (!Copy->isCopy())
+    return Copy;
+  unsigned CopySrc = Copy->getOperand(1).getReg();
+  Subreg = Copy->getOperand(1).getSubReg();
+  if (!TargetRegisterInfo::isVirtualRegister(CopySrc)) {
+    const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
+    // Set the Subreg
+    if (CopySrc == PPC::CR0EQ || CopySrc == PPC::CR6EQ)
+      Subreg = PPC::sub_eq;
+    if (CopySrc == PPC::CR0LT || CopySrc == PPC::CR6LT)
+      Subreg = PPC::sub_lt;
+    if (CopySrc == PPC::CR0GT || CopySrc == PPC::CR6GT)
+      Subreg = PPC::sub_gt;
+    if (CopySrc == PPC::CR0UN || CopySrc == PPC::CR6UN)
+      Subreg = PPC::sub_un;
+    // Loop backwards and return the first MI that modifies the physical CR Reg.
+    MachineBasicBlock::iterator Me = Copy, B = Copy->getParent()->begin();
+    while (Me != B)
+      if ((--Me)->modifiesRegister(CopySrc, TRI))
+        return &*Me;
+    return nullptr;
+  }
+  return MRI->getVRegDef(CopySrc);
+}
+
+void PPCReduceCRLogicals::initialize(MachineFunction &MFParam) {
+  MF = &MFParam;
+  MRI = &MF->getRegInfo();
+  TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
+  MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
+
+  AllCRLogicalOps.clear();
+}
+
+/// Contains all the implemented transformations on CR logical operations.
+/// For example, a binary CR logical can be used to split a block on its inputs,
+/// a unary CR logical might be used to change the condition code on a
+/// comparison feeding it. A nullary CR logical might simply be removable
+/// if the user of the bit it [un]sets can be transformed.
+bool PPCReduceCRLogicals::handleCROp(CRLogicalOpInfo &CRI) {
+  // We can definitely split a block on the inputs to a binary CR operation
+  // whose defs and (single) use are within the same block.
+  bool Changed = false;
+  if (CRI.IsBinary && CRI.ContainedInBlock && CRI.SingleUse && CRI.FeedsBR &&
+      CRI.DefsSingleUse) {
+    Changed = splitBlockOnBinaryCROp(CRI);
+    if (Changed)
+      NumBlocksSplitOnBinaryCROp++;
+  }
+  return Changed;
+}
+
+/// Splits a block that contains a CR-logical operation that feeds a branch
+/// and whose operands are produced within the block.
+/// Example:
+///    %vr5<def> = CMPDI %vr2, 0; CRRC:%vr5 G8RC:%vr2
+///    %vr6<def> = COPY %vr5:sub_eq; CRBITRC:%vr6 CRRC:%vr5
+///    %vr7<def> = CMPDI %vr3, 0; CRRC:%vr7 G8RC:%vr3
+///    %vr8<def> = COPY %vr7:sub_eq; CRBITRC:%vr8 CRRC:%vr7
+///    %vr9<def> = CROR %vr6<kill>, %vr8<kill>; CRBITRC:%vr9,%vr6,%vr8
+///    BC %vr9<kill>, <BB#2>; CRBITRC:%vr9
+/// Becomes:
+///    %vr5<def> = CMPDI %vr2, 0; CRRC:%vr5 G8RC:%vr2
+///    %vr6<def> = COPY %vr5:sub_eq; CRBITRC:%vr6 CRRC:%vr5
+///    BC %vr6<kill>, <BB#2>; CRBITRC:%vr6
+///
+///    %vr7<def> = CMPDI %vr3, 0; CRRC:%vr7 G8RC:%vr3
+///    %vr8<def> = COPY %vr7:sub_eq; CRBITRC:%vr8 CRRC:%vr7
+///    BC %vr9<kill>, <BB#2>; CRBITRC:%vr9
+bool PPCReduceCRLogicals::splitBlockOnBinaryCROp(CRLogicalOpInfo &CRI) {
+  if (CRI.CopyDefs.first == CRI.CopyDefs.second) {
+    DEBUG(dbgs() << "Unable to split as the two operands are the same\n");
+    NumNotSplitIdenticalOperands++;
+    return false;
+  }
+  if (CRI.TrueDefs.first->isCopy() || CRI.TrueDefs.second->isCopy() ||
+      CRI.TrueDefs.first->isPHI() || CRI.TrueDefs.second->isPHI()) {
+    DEBUG(dbgs() << "Unable to split because one of the operands is a PHI or "
+          "chain of copies.\n");
+    NumNotSplitChainCopies++;
+    return false;
+  }
+  // Note: keep in sync with computeBranchTargetAndInversion().
+  if (CRI.MI->getOpcode() != PPC::CROR &&
+      CRI.MI->getOpcode() != PPC::CRAND &&
+      CRI.MI->getOpcode() != PPC::CRNOR &&
+      CRI.MI->getOpcode() != PPC::CRNAND &&
+      CRI.MI->getOpcode() != PPC::CRORC &&
+      CRI.MI->getOpcode() != PPC::CRANDC) {
+    DEBUG(dbgs() << "Unable to split blocks on this opcode.\n");
+    NumNotSplitWrongOpcode++;
+    return false;
+  }
+  DEBUG(dbgs() << "Splitting the following CR op:\n"; CRI.dump());
+  MachineBasicBlock::iterator Def1It = CRI.TrueDefs.first;
+  MachineBasicBlock::iterator Def2It = CRI.TrueDefs.second;
+
+  bool UsingDef1 = false;
+  MachineInstr *SplitBefore = &*Def2It;
+  for (auto E = CRI.MI->getParent()->end(); Def2It != E; ++Def2It) {
+    if (Def1It == Def2It) { // Def2 comes before Def1.
+      SplitBefore = &*Def1It;
+      UsingDef1 = true;
+      break;
+    }
+  }
+
+  DEBUG(dbgs() << "We will split the following block:\n";);
+  DEBUG(CRI.MI->getParent()->dump());
+  DEBUG(dbgs() << "Before instruction:\n"; SplitBefore->dump());
+
+  // Get the branch instruction.
+  MachineInstr *Branch =
+    MRI->use_nodbg_begin(CRI.MI->getOperand(0).getReg())->getParent();
+
+  // We want the new block to have no code in it other than the definition
+  // of the input to the CR logical and the CR logical itself. So we move
+  // those to the bottom of the block (just before the branch). Then we
+  // will split before the CR logical.
+  MachineBasicBlock *MBB = SplitBefore->getParent();
+  auto FirstTerminator = MBB->getFirstTerminator();
+  MachineBasicBlock::iterator FirstInstrToMove =
+    UsingDef1 ? CRI.TrueDefs.first : CRI.TrueDefs.second;
+  MachineBasicBlock::iterator SecondInstrToMove =
+    UsingDef1 ? CRI.CopyDefs.first : CRI.CopyDefs.second;
+
+  // The instructions that need to be moved are not guaranteed to be
+  // contiguous. Move them individually.
+  // FIXME: If one of the operands is a chain of (single use) copies, they
+  // can all be moved and we can still split.
+  MBB->splice(FirstTerminator, MBB, FirstInstrToMove);
+  if (FirstInstrToMove != SecondInstrToMove)
+    MBB->splice(FirstTerminator, MBB, SecondInstrToMove);
+  MBB->splice(FirstTerminator, MBB, CRI.MI);
+
+  unsigned Opc = CRI.MI->getOpcode();
+  bool InvertOrigBranch, InvertNewBranch, TargetIsFallThrough;
+  computeBranchTargetAndInversion(Opc, Branch->getOpcode(), UsingDef1,
+                                  InvertNewBranch, InvertOrigBranch,
+                                  TargetIsFallThrough);
+  MachineInstr *SplitCond =
+    UsingDef1 ? CRI.CopyDefs.second : CRI.CopyDefs.first;
+  DEBUG(dbgs() << "We will " <<  (InvertNewBranch ? "invert" : "copy"));
+  DEBUG(dbgs() << " the original branch and the target is the " <<
+        (TargetIsFallThrough ? "fallthrough block\n" : "orig. target block\n"));
+  DEBUG(dbgs() << "Original branch instruction: "; Branch->dump());
+  BlockSplitInfo BSI { Branch, SplitBefore, SplitCond, InvertNewBranch,
+    InvertOrigBranch, TargetIsFallThrough, MBPI, CRI.MI,
+    UsingDef1 ? CRI.CopyDefs.first : CRI.CopyDefs.second };
+  bool Changed = splitMBB(BSI);
+  // If we've split on a CR logical that is fed by a CR logical,
+  // recompute the source CR logical as it may be usable for splitting.
+  if (Changed) {
+    bool Input1CRlogical =
+      CRI.TrueDefs.first && isCRLogical(*CRI.TrueDefs.first);
+    bool Input2CRlogical =
+      CRI.TrueDefs.second && isCRLogical(*CRI.TrueDefs.second);
+    if (Input1CRlogical)
+      AllCRLogicalOps.push_back(createCRLogicalOpInfo(*CRI.TrueDefs.first));
+    if (Input2CRlogical)
+      AllCRLogicalOps.push_back(createCRLogicalOpInfo(*CRI.TrueDefs.second));
+  }
+  return Changed;
+}
+
+void PPCReduceCRLogicals::collectCRLogicals() {
+  for (MachineBasicBlock &MBB : *MF) {
+    for (MachineInstr &MI : MBB) {
+      if (isCRLogical(MI)) {
+        AllCRLogicalOps.push_back(createCRLogicalOpInfo(MI));
+        TotalCRLogicals++;
+        if (AllCRLogicalOps.back().IsNullary)
+          TotalNullaryCRLogicals++;
+        else if (AllCRLogicalOps.back().IsBinary)
+          TotalBinaryCRLogicals++;
+        else
+          TotalUnaryCRLogicals++;
+      }
+    }
+  }
+}
+
+} // end annonymous namespace
+
+INITIALIZE_PASS_BEGIN(PPCReduceCRLogicals, DEBUG_TYPE,
+                      "PowerPC Reduce CR logical Operation", false, false)
+INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
+INITIALIZE_PASS_END(PPCReduceCRLogicals, DEBUG_TYPE,
+                    "PowerPC Reduce CR logical Operation", false, false)
+
+char PPCReduceCRLogicals::ID = 0;
+FunctionPass*
+llvm::createPPCReduceCRLogicalsPass() { return new PPCReduceCRLogicals(); }

llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp

EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
                       cl::desc("Add extra TOC register dependencies"),
                       cl::init(true), cl::Hidden);
 
 static cl::opt<bool>
 EnableMachineCombinerPass("ppc-machine-combiner",
                           cl::desc("Enable the machine combiner pass"),
                           cl::init(true), cl::Hidden);
 
+static cl::opt<bool>
+  ReduceCRLogical("ppc-reduce-cr-logicals",
+                  cl::desc("Expand eligible cr-logical binary ops to branches"),
+                  cl::init(false), cl::Hidden);
 extern "C" void LLVMInitializePowerPCTarget() {
   // Register the targets
   RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
   RegisterTargetMachine<PPCTargetMachine> B(getThePPC64Target());
   RegisterTargetMachine<PPCTargetMachine> C(getThePPC64LETarget());
 
   PassRegistry &PR = *PassRegistry::getPassRegistry();
   initializePPCBoolRetToIntPass(PR);
void PPCPassConfig::addMachineSSAOptimization() {
   if (EnableBranchCoalescing && getOptLevel() != CodeGenOpt::None)
     addPass(createPPCBranchCoalescingPass());
   TargetPassConfig::addMachineSSAOptimization();
   // For little endian, remove where possible the vector swap instructions
   // introduced at code generation to normalize vector element order.
   if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
       !DisableVSXSwapRemoval)
     addPass(createPPCVSXSwapRemovalPass());
+  // Reduce the number of cr-logical ops.
+  if (ReduceCRLogical && getOptLevel() != CodeGenOpt::None)
+    addPass(createPPCReduceCRLogicalsPass());
   // Target-specific peephole cleanups performed after instruction
   // selection.
   if (!DisableMIPeephole) {
     addPass(createPPCMIPeepholePass());
     addPass(&DeadMachineInstructionElimID);
   }
 }
 

llvm/trunk/test/CodeGen/PowerPC/licm-remat.ll

-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-reduce-cr-logicals \
+; RUN:   -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
 
 ; Test case is reduced from the snappy benchmark.
 ; Verify MachineLICM will always hoist trivially rematerializable instructions even when register pressure is high.
 
 %"class.snappy::SnappyDecompressor" = type <{ %"class.snappy::Source"*, i8*, i8*, i32, i8, [5 x i8], [6 x i8] }>
 %"class.snappy::Source" = type { i32 (...)** }
 %"struct.snappy::iovec" = type { i8*, i64 }
 %"class.snappy::SnappyIOVecWriter" = type { %"struct.snappy::iovec"*, i64, i64, i64, i64, i64 }
 
 @_ZN6snappy8internalL10char_tableE = internal unnamed_addr constant [5 x i16] [i16 1, i16 2052, i16 4097, i16 8193, i16 2], align 2
 @_ZN6snappy8internalL8wordmaskE = internal unnamed_addr constant [5 x i32] [i32 0, i32 255, i32 65535, i32 16777215, i32 -1], align 4
 
 ; Function Attrs: argmemonly nounwind
 declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #2
 ; Function Attrs: argmemonly nounwind
 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32, i1) #2
 
 define linkonce_odr void @ZN6snappyDecompressor_(%"class.snappy::SnappyDecompressor"* %this, %"class.snappy::SnappyIOVecWriter"* %writer) {
 ; CHECK-LABEL: ZN6snappyDecompressor_:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK:       addis 3, 2, _ZN6snappy8internalL8wordmaskE@toc@ha
 ; CHECK-DAG:   addi 25, 3, _ZN6snappy8internalL8wordmaskE@toc@l
-; CHECK-DAG:   addis 4, 2, _ZN6snappy8internalL10char_tableE@toc@ha
-; CHECK-DAG:   addi 24, 4, _ZN6snappy8internalL10char_tableE@toc@l
+; CHECK-DAG:   addis 5, 2, _ZN6snappy8internalL10char_tableE@toc@ha
+; CHECK-DAG:   addi 24, 5, _ZN6snappy8internalL10char_tableE@toc@l
 ; CHECK:       b .LBB0_2
 ; CHECK:       .LBB0_2: # %for.cond
 ; CHECK-NOT:   addis {{[0-9]+}}, 2, _ZN6snappy8internalL8wordmaskE@toc@ha
 ; CHECK-NOT:   addis {{[0-9]+}}, 2, _ZN6snappy8internalL10char_tableE@toc@ha
 ; CHECK:       bctrl
 entry:
   %ip_limit_ = getelementptr inbounds %"class.snappy::SnappyDecompressor", %"class.snappy::SnappyDecompressor"* %this, i64 0, i32 2
   %0 = bitcast i8** %ip_limit_ to i64*

llvm/trunk/test/CodeGen/PowerPC/select-i1-vs-i1.ll

-; RUN: llc -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
+; RUN: llc -ppc-reduce-cr-logicals -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -ppc-reduce-cr-logicals -verify-machineinstrs \
+; RUN:   -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 ; FIXME: We should check the operands to the cr* logical operation itself, but
 ; unfortunately, FileCheck does not yet understand how to do arithmetic, so we
 ; can't do so without introducing a register-allocation dependency.
 
 define signext i32 @testi32slt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {

 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, float %a1, float %a2
   ret float %cond
 
 ; CHECK-LABEL: @testfloatslt
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: fmr 1, 5
 ; CHECK: blr
 }
 
 define float @testfloatult(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, float %a1, float %a2
   ret float %cond
 
 ; CHECK-LABEL: @testfloatult
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: fmr 1, 5
 ; CHECK: blr
 }
 
 define float @testfloatsle(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, float %a1, float %a2
   ret float %cond
 
 ; CHECK-LABEL: @testfloatsle
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 12, 2, .LBB[[BB]]
 ; CHECK: fmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: fmr 1, 5
 ; CHECK: blr
 }
 
 define float @testfloatule(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, float %a1, float %a2
   ret float %cond
 
 ; CHECK-LABEL: @testfloatule
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 4, 2, .LBB[[BB]]
 ; CHECK: fmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: fmr 1, 5
 ; CHECK: blr
 }
 
 define float @testfloateq(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
 entry:

 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, float %a1, float %a2
   ret float %cond
 
 ; CHECK-LABEL: @testfloatsge
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 4, 2, .LBB[[BB]]
 ; CHECK: fmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: fmr 1, 5
 ; CHECK: blr
 }
 
 define float @testfloatuge(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, float %a1, float %a2
   ret float %cond
 
 ; CHECK-LABEL: @testfloatuge
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 12, 2, .LBB[[BB]]
 ; CHECK: fmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: fmr 1, 5
 ; CHECK: blr
 }
 
 define float @testfloatsgt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, float %a1, float %a2
   ret float %cond
 
 ; CHECK-LABEL: @testfloatsgt
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: fmr 1, 5
 ; CHECK: blr
 }
 
 define float @testfloatugt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, float %a1, float %a2
   ret float %cond
 
 ; CHECK-LABEL: @testfloatugt
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: fmr 1, 5
 ; CHECK: blr
 }
 
 define float @testfloatne(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2

 entry:
   %cmp1 = fcmp oeq double %c3, %c4
   %cmp3tmp = fcmp oeq double %c1, %c2
   %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, double %a1, double %a2
   ret double %cond
 
 ; CHECK-LABEL: @testdoubleslt
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: fmr 1, 5
 ; CHECK: blr
 }
 
 define double @testdoubleult(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
 entry:
   %cmp1 = fcmp oeq double %c3, %c4
   %cmp3tmp = fcmp oeq double %c1, %c2
   %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, double %a1, double %a2
   ret double %cond
 
 ; CHECK-LABEL: @testdoubleult
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: fmr 1, 5
 ; CHECK: blr
 }
 
 define double @testdoublesle(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
 entry:
   %cmp1 = fcmp oeq double %c3, %c4
   %cmp3tmp = fcmp oeq double %c1, %c2
   %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, double %a1, double %a2
   ret double %cond
 
 ; CHECK-LABEL: @testdoublesle
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 12, 2, .LBB[[BB]]
 ; CHECK: fmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: fmr 1, 5
 ; CHECK: blr
 }
 
 define double @testdoubleule(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
 entry:
   %cmp1 = fcmp oeq double %c3, %c4
   %cmp3tmp = fcmp oeq double %c1, %c2
   %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, double %a1, double %a2
   ret double %cond
 
 ; CHECK-LABEL: @testdoubleule
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 4, 2, .LBB[[BB]]
 ; CHECK: fmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: fmr 1, 5
 ; CHECK: blr
 }
 
 define double @testdoubleeq(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
 entry:

 entry:
   %cmp1 = fcmp oeq double %c3, %c4
   %cmp3tmp = fcmp oeq double %c1, %c2
   %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, double %a1, double %a2
   ret double %cond
 
 ; CHECK-LABEL: @testdoublesge
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 4, 2, .LBB[[BB]]
 ; CHECK: fmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: fmr 1, 5
 ; CHECK: blr
 }
 
 define double @testdoubleuge(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
 entry:
   %cmp1 = fcmp oeq double %c3, %c4
   %cmp3tmp = fcmp oeq double %c1, %c2
   %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, double %a1, double %a2
   ret double %cond
 
 ; CHECK-LABEL: @testdoubleuge
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 12, 2, .LBB[[BB]]
 ; CHECK: fmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: fmr 1, 5
 ; CHECK: blr
 }
 
 define double @testdoublesgt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
 entry:
   %cmp1 = fcmp oeq double %c3, %c4
   %cmp3tmp = fcmp oeq double %c1, %c2
   %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, double %a1, double %a2
   ret double %cond
 
 ; CHECK-LABEL: @testdoublesgt
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: fmr 1, 5
 ; CHECK: blr
 }
 
 define double @testdoubleugt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
 entry:
   %cmp1 = fcmp oeq double %c3, %c4
   %cmp3tmp = fcmp oeq double %c1, %c2
   %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, double %a1, double %a2
   ret double %cond
 
 ; CHECK-LABEL: @testdoubleugt
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: fmr 1, 5
 ; CHECK: blr
 }
 
 define double @testdoublene(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
 entry:
   %cmp1 = fcmp oeq double %c3, %c4
   %cmp3tmp = fcmp oeq double %c1, %c2
entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testv4floatslt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: bclr 12, 2, 0
+; CHECK: .LBB[[BB]]:
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <4 x float> @testv4floatult(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testv4floatult
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bclr 4, 2, 0
+; CHECK: .LBB[[BB]]:
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <4 x float> @testv4floatsle(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testv4floatsle
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bclr 4, 2, 0
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bclr 12, 2, 0
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <4 x float> @testv4floatule(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testv4floatule
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bclr 12, 2, 0
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: bclr 4, 2, 0
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <4 x float> @testv4floateq(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testv4floatsge
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bclr 12, 2, 0
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: bclr 4, 2, 0
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <4 x float> @testv4floatuge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testv4floatuge
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bclr 4, 2, 0
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: bclr 12, 2, 0
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <4 x float> @testv4floatsgt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testv4floatsgt
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bclr 4, 2, 0
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <4 x float> @testv4floatugt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testv4floatugt
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bclr 12, 2, 0
+; CHECK: .LBB[[BB]]
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <4 x float> @testv4floatne(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
   ret <2 x double> %cond
 
 ; CHECK-LABEL: @testv2doubleslt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: bc 4, 2, .LBB[[BB]]
+; CHECK: .LBB[[BB]]:
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <2 x double> @testv2doubleult(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
   ret <2 x double> %cond
 
 ; CHECK-LABEL: @testv2doubleult
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: bc 12, 2, .LBB[[BB]]
+; CHECK: .LBB[[BB]]:
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <2 x double> @testv2doublesle(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
   ret <2 x double> %cond
 
 ; CHECK-LABEL: @testv2doublesle
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bclr 4, 2, 0
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: bclr 12, 2, 0
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <2 x double> @testv2doubleule(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
   ret <2 x double> %cond
 
 ; CHECK-LABEL: @testv2doubleule
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bclr 12, 2, 0
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: bclr 4, 2, 0
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <2 x double> @testv2doubleeq(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
   ret <2 x double> %cond
 
 ; CHECK-LABEL: @testv2doublesge
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bclr 12, 2, 0
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: bclr 4, 2, 0
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <2 x double> @testv2doubleuge(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
   ret <2 x double> %cond
 
 ; CHECK-LABEL: @testv2doubleuge
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bclr 4, 2, 0
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: bclr 12, 2, 0
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <2 x double> @testv2doublesgt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
   ret <2 x double> %cond
 
 ; CHECK-LABEL: @testv2doublesgt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: bc 12, 2, .LBB[[BB]]
+; CHECK: .LBB[[BB]]
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <2 x double> @testv2doubleugt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
   ret <2 x double> %cond
 
 ; CHECK-LABEL: @testv2doubleugt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: bc 4, 2, .LBB[[BB]]
+; CHECK: .LBB[[BB]]
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <2 x double> @testv2doublene(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
   ret <4 x double> %cond
 
 ; CHECK-LABEL: @testqv4doubleslt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
 
 define <4 x double> @testqv4doubleult(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
   ret <4 x double> %cond
 
 ; CHECK-LABEL: @testqv4doubleult
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
 
 define <4 x double> @testqv4doublesle(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
   ret <4 x double> %cond
 
 ; CHECK-LABEL: @testqv4doublesle
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 12, 2, .LBB[[BB]]
 ; CHECK: qvfmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
 
 define <4 x double> @testqv4doubleule(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
   ret <4 x double> %cond
 
 ; CHECK-LABEL: @testqv4doubleule
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 4, 2, .LBB[[BB]]
 ; CHECK: qvfmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
 
 define <4 x double> @testqv4doubleeq(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
 entry:
entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
   ret <4 x double> %cond
 
 ; CHECK-LABEL: @testqv4doublesge
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 4, 2, .LBB[[BB]]
 ; CHECK: qvfmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
 
 define <4 x double> @testqv4doubleuge(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
   ret <4 x double> %cond
 
 ; CHECK-LABEL: @testqv4doubleuge
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 12, 2, .LBB[[BB]]
 ; CHECK: qvfmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
 
 define <4 x double> @testqv4doublesgt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
   ret <4 x double> %cond
 
 ; CHECK-LABEL: @testqv4doublesgt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
 
 define <4 x double> @testqv4doubleugt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
   ret <4 x double> %cond
 
 ; CHECK-LABEL: @testqv4doubleugt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
 
 define <4 x double> @testqv4doublene(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testqv4floatslt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
 
 define <4 x float> @testqv4floatult(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testqv4floatult
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
 
 define <4 x float> @testqv4floatsle(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testqv4floatsle
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 12, 2, .LBB[[BB]]
 ; CHECK: qvfmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
 
 define <4 x float> @testqv4floatule(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testqv4floatule
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 4, 2, .LBB[[BB]]
 ; CHECK: qvfmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
 
 define <4 x float> @testqv4floateq(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
 entry:
entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testqv4floatsge
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 4, 2, .LBB[[BB]]
 ; CHECK: qvfmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
 
 define <4 x float> @testqv4floatuge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testqv4floatuge
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 12, 2, .LBB[[BB]]
 ; CHECK: qvfmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
 
 define <4 x float> @testqv4floatsgt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testqv4floatsgt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
 
 define <4 x float> @testqv4floatugt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testqv4floatugt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
 
 define <4 x float> @testqv4floatne(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
   ret <4 x i1> %cond
 
 ; CHECK-LABEL: @testqv4i1slt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
 
 define <4 x i1> @testqv4i1ult(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
   ret <4 x i1> %cond
 
 ; CHECK-LABEL: @testqv4i1ult
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
 
 define <4 x i1> @testqv4i1sle(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
   ret <4 x i1> %cond
 
 ; CHECK-LABEL: @testqv4i1sle
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 12, 2, .LBB[[BB]]
 ; CHECK: qvfmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
 
 define <4 x i1> @testqv4i1ule(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
   ret <4 x i1> %cond
 
 ; CHECK-LABEL: @testqv4i1ule
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 4, 2, .LBB[[BB]]
 ; CHECK: qvfmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
 
 define <4 x i1> @testqv4i1eq(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
 entry:
entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
   ret <4 x i1> %cond
 
 ; CHECK-LABEL: @testqv4i1sge
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 4, 2, .LBB[[BB]]
 ; CHECK: qvfmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
 
 define <4 x i1> @testqv4i1uge(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
   ret <4 x i1> %cond
 
 ; CHECK-LABEL: @testqv4i1uge
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 12, 2, .LBB[[BB]]
 ; CHECK: qvfmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
 
 define <4 x i1> @testqv4i1sgt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
   ret <4 x i1> %cond
 
 ; CHECK-LABEL: @testqv4i1sgt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
 
 define <4 x i1> @testqv4i1ugt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
   ret <4 x i1> %cond
 
 ; CHECK-LABEL: @testqv4i1ugt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
 
 define <4 x i1> @testqv4i1ne(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2

llvm/trunk/test/CodeGen/PowerPC/tail-dup-layout.ll

-; RUN: llc -O2 -o - %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-O2 %s
-; RUN: llc -O3 -o - %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-O3 %s
+; RUN: llc -O2 -ppc-reduce-cr-logicals -o - %s | FileCheck \
+; RUN:   --check-prefix=CHECK --check-prefix=CHECK-O2 %s
+; RUN: llc -O3 -ppc-reduce-cr-logicals -o - %s | FileCheck \
+; RUN:   --check-prefix=CHECK --check-prefix=CHECK-O3 %s
 target datalayout = "e-m:e-i64:64-n32:64"
 target triple = "powerpc64le-grtev4-linux-gnu"
 
 ; Intended layout:
 ; The chain-based outlining produces the layout
 ; test1
 ; test2
 ; test3

 ; exit
 ; The CHECK statements check for the whole string of tests and exit block,
 ; and then check that the correct test has been duplicated into the end of
 ; the optional blocks and that the optional blocks are in the correct order.
 ;CHECK-LABEL: loop_test:
 ;CHECK: add [[TAGPTRREG:[0-9]+]], 3, 4
 ;CHECK: .[[LATCHLABEL:[._0-9A-Za-z]+]]: # %for.latch
 ;CHECK: addi
-;CHECK: .[[CHECKLABEL:[._0-9A-Za-z]+]]: # %for.check
+;CHECK-O2: .[[CHECKLABEL:[._0-9A-Za-z]+]]: # %for.check
 ;CHECK: lwz [[TAGREG:[0-9]+]], 0([[TAGPTRREG]])
+;CHECK-O3: .[[CHECKLABEL:[._0-9A-Za-z]+]]: # %for.check
 ;CHECK: # %bb.{{[0-9]+}}: # %test1
 ;CHECK: andi. {{[0-9]+}}, [[TAGREG]], 1
 ;CHECK-NEXT: bc 12, 1, .[[OPT1LABEL:[._0-9A-Za-z]+]]
 ;CHECK-NEXT: # %test2
 ;CHECK: rlwinm. {{[0-9]+}}, [[TAGREG]], 0, 30, 30
 ;CHECK-NEXT: bne 0, .[[OPT2LABEL:[._0-9A-Za-z]+]]
 ;CHECK-NEXT: .[[TEST3LABEL:[._0-9A-Za-z]+]]: # %test3
 ;CHECK: rlwinm. {{[0-9]+}}, [[TAGREG]], 0, 29, 29