AMDGPU : Fix ISA Version Definitions.

[wdng]

Summary

Fix ISA Version Definitions.

[arsenm]

lib/Target/AMDGPU/AMDGPU.td

34–44

These don't match the terminology used elsewhere. I don't think anything goes slower than quarter rate. Some sources call this 1/16th, but full rate is really 1/4th

[wdng]

lib/Target/AMDGPU/AMDGPU.td

34–44

Do you mean HalfRate64Ops = 1/8 rate and quarter rate = 1/16 rate?

[arsenm]

lib/Target/AMDGPU/AMDGPU.td

34–44

I believe so. The documentation is confusing because it doesn't use a consistent terminology. Full rate is 1/4th of the wave at a time.

[wdng]

lib/Target/AMDGPU/AMDGPU.td

34–44

So any suggestions to name 1/2 rate F64? DoubleRate64Ops?

[wdng]

Add new ISA version definitions & fix incorrect ISA versions.

[wdng]

Add gfx600 and gfx601 definitions.

[kzhuravl]

lib/Target/AMDGPU/AMDGPU.td

451

gfx600/gfx601 are southern islands.

474

gfx703 is not present in docs update made by @t-tye here: D33736. So either this or the doc need to be updated.

lib/Target/AMDGPU/Processors.td

110–115

Move these next to other southern islands.

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

120

bad formatting.

[wdng]

Address code reviews.

[wdng]

Ping.

[t-tye]

lib/Target/AMDGPU/AMDGPU.td

450

This is the same as SI/tahiti so I think it should have: FeatureFastFMAF32, HalfRate64Ops

474

gfx703 was added to docs by D34016.

509–518

Add FeatureGFX9.

lib/Target/AMDGPU/Processors.td

85–97

SI and tahiti are gfx600 so need to make them have the same attributes and features:

def : ProcessorModel<"gfx600", SIFullSpeedModel,
  [FeatureISAVersion6_0_0]
>;

def : ProcessorModel<"SI", SIFullSpeedModel,
  [FeatureISAVersion6_0_0]
>;

def : ProcessorModel<"tahiti", SIFullSpeedModel,
  [FeatureISAVersion6_0_0]
>;

97–104

pitcairn/verde/oland/hainan are all gfx601 so suggest:

def : ProcessorModel<"pitcairn", SIQuarterSpeedModel, [FeatureISAVersion6_0_1]>;

def : ProcessorModel<"verde",    SIQuarterSpeedModel, [FeatureISAVersion6_0_1]>;

def : ProcessorModel<"oland",    SIQuarterSpeedModel, [FeatureISAVersion6_0_1]>;

def : ProcessorModel<"hainan",   SIQuarterSpeedModel, [FeatureISAVersion6_0_1]>;

124–125

Add:

def : ProcessorModel<"gfx702",     SIQuarterSpeedModel,
  [FeatureISAVersion7_0_1]
>;

125

Hawaii is gfx701 so make this FeatureISAVersion7_0_1.

127

kabini is gfx703 so make this FeatureISAVersion7_0_3.

130

mullins is gfx703 so make this FeatureISAVersion7_0_3.

133–136

Move this above kabini so in order.

200–215

The only feature these should have is the corresponding FeatureISAVersion9_0_n as these define the other features.

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

148–149

Is returning this default the right thing to do? Would it be better to assert since we are supposed to mark all GCN targets with their feature.

[wdng]

Address code reviews based on Tony's @t-tye comments

[t-tye]

lib/Target/AMDGPU/Processors.td

85–97

I don't think this comment as done as the source is still referring to features, see the suggested test above.

203

I think we need a GFX9 heading here to match the other sections.

//===----------------------------------------------------------------------===//
// GFX9
//===----------------------------------------------------------------------===//

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

107

To be consistent add period.

// SI.

test/MC/AMDGPU/sym_option.s

39

I think this should be 1 as hawaii is gfx701.

[wdng]

Address code reviews.

[t-tye]

LGTM

[wdng]

Modified lit tests.

[t-tye]

LGTM and address assert issue as a separate patch.

lib/Target/AMDGPU/AMDGPU.td

 >;
 
 def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
   "HalfRate64Ops",
   "true",
   "Most fp64 instructions are half rate instead of quarter"
 >;
 
 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
   "R600ALUInst",
   "false",
   "Older version of ALU instructions encoding"
 >;
 
 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
   "HasVertexCache",
   "true",
   "Specify use of dedicated vertex cache"
 >;
 
 def FeatureCaymanISA : SubtargetFeature<"caymanISA",
   "CaymanISA",
   "true",
   "Use Cayman ISA"
 >;
 
 def FeatureCFALUBug : SubtargetFeature<"cfalubug",
class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping,
                                  : SubtargetFeature <
   "isaver"#Major#"."#Minor#"."#Stepping,
   "IsaVersion",
   "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
   "Instruction set version number",
   Implies
 >;
 
+def FeatureISAVersion6_0_0 : SubtargetFeatureISAVersion <6,0,0,
+  [FeatureSouthernIslands,
+   FeatureFastFMAF32, 
+   HalfRate64Ops,
+   FeatureLDSBankCount32]>;
+
+def FeatureISAVersion6_0_1 : SubtargetFeatureISAVersion <6,0,1,
+  [FeatureSouthernIslands,
+   FeatureLDSBankCount32]>;
+   
 def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
   [FeatureSeaIslands,
    FeatureLDSBankCount32]>;
 
 def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1,
   [FeatureSeaIslands,
    HalfRate64Ops,
    FeatureLDSBankCount32,
    FeatureFastFMAF32]>;
 
 def FeatureISAVersion7_0_2 : SubtargetFeatureISAVersion <7,0,2,
   [FeatureSeaIslands,
    FeatureLDSBankCount16]>;
 
+def FeatureISAVersion7_0_3 : SubtargetFeatureISAVersion <7,0,3,
+  [FeatureSeaIslands,
+   FeatureLDSBankCount16]>;
+
 def FeatureISAVersion8_0_0 : SubtargetFeatureISAVersion <8,0,0,
   [FeatureVolcanicIslands,
    FeatureLDSBankCount32,
    FeatureSGPRInitBug]>;
 
 def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1,
   [FeatureVolcanicIslands,
    FeatureLDSBankCount32,
def FeatureISAVersion8_0_4 : SubtargetFeatureISAVersion <8,0,4,
   [FeatureVolcanicIslands,
    FeatureLDSBankCount32]>;
 
 def FeatureISAVersion8_1_0 : SubtargetFeatureISAVersion <8,1,0,
   [FeatureVolcanicIslands,
    FeatureLDSBankCount16,
    FeatureXNACK]>;
 
-def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,[]>;
-def FeatureISAVersion9_0_1 : SubtargetFeatureISAVersion <9,0,1,[]>;
+def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,
+  [FeatureGFX9,
+   FeatureLDSBankCount32]>;
+
+def FeatureISAVersion9_0_1 : SubtargetFeatureISAVersion <9,0,1,
+  [FeatureGFX9,
+   FeatureLDSBankCount32,
+   FeatureXNACK]>;
+
+def FeatureISAVersion9_0_2 : SubtargetFeatureISAVersion <9,0,2,
+  [FeatureGFX9,
+   FeatureLDSBankCount32]>;
+
+def FeatureISAVersion9_0_3 : SubtargetFeatureISAVersion <9,0,3,
+  [FeatureGFX9,
+   FeatureLDSBankCount32,
+   FeatureXNACK]>;
 
 //===----------------------------------------------------------------------===//
 // Debugger related subtarget features.
 //===----------------------------------------------------------------------===//
 
 def FeatureDebuggerInsertNops : SubtargetFeature<
   "amdgpu-debugger-insert-nops",
   "DebuggerInsertNops",

lib/Target/AMDGPU/AMDGPUSubtarget.h

enum Generation {
     SOUTHERN_ISLANDS,
     SEA_ISLANDS,
     VOLCANIC_ISLANDS,
     GFX9,
   };
 
   enum {
     ISAVersion0_0_0,
+    ISAVersion6_0_0,
+    ISAVersion6_0_1,
     ISAVersion7_0_0,
     ISAVersion7_0_1,
     ISAVersion7_0_2,
+    ISAVersion7_0_3,
     ISAVersion8_0_0,
     ISAVersion8_0_1,
     ISAVersion8_0_2,
     ISAVersion8_0_3,
     ISAVersion8_0_4,
     ISAVersion8_1_0,
     ISAVersion9_0_0,
-    ISAVersion9_0_1
+    ISAVersion9_0_1,
+    ISAVersion9_0_2,
+    ISAVersion9_0_3
   };
 
   enum TrapHandlerAbi {
     TrapHandlerAbiNone = 0,
     TrapHandlerAbiHsa = 1
   };
 
   enum TrapID {

lib/Target/AMDGPU/Processors.td

 
 def : Proc<"cayman",     R600_VLIW4_Itin,
     [FeatureNorthernIslands, FeatureFP64, FeatureCaymanISA]>;
 
 //===----------------------------------------------------------------------===//
 // Southern Islands
 //===----------------------------------------------------------------------===//
 
+def : ProcessorModel<"gfx600", SIFullSpeedModel, [FeatureISAVersion6_0_0]>;
+
 def : ProcessorModel<"SI", SIFullSpeedModel,
-  [FeatureSouthernIslands, FeatureFastFMAF32, HalfRate64Ops]
+  [FeatureSouthernIslands, FeatureFastFMAF32, HalfRate64Ops, FeatureISAVersion6_0_0]
 >;
 
 def : ProcessorModel<"tahiti", SIFullSpeedModel,
-  [FeatureSouthernIslands, FeatureFastFMAF32, HalfRate64Ops]
+  [FeatureSouthernIslands, FeatureFastFMAF32, HalfRate64Ops, FeatureISAVersion6_0_0]
+>;
+
+def : ProcessorModel<"gfx601", SIQuarterSpeedModel,
+  [FeatureISAVersion6_0_1]
 >;
 
-def : ProcessorModel<"pitcairn", SIQuarterSpeedModel, [FeatureSouthernIslands]>;
+def : ProcessorModel<"pitcairn", SIQuarterSpeedModel, [FeatureISAVersion6_0_1]>;
 
-def : ProcessorModel<"verde",    SIQuarterSpeedModel, [FeatureSouthernIslands]>;
+def : ProcessorModel<"verde",    SIQuarterSpeedModel, [FeatureISAVersion6_0_1]>;
 
-def : ProcessorModel<"oland",    SIQuarterSpeedModel, [FeatureSouthernIslands]>;
+def : ProcessorModel<"oland",    SIQuarterSpeedModel, [FeatureISAVersion6_0_1]>;
 
-def : ProcessorModel<"hainan",   SIQuarterSpeedModel, [FeatureSouthernIslands]>;
+def : ProcessorModel<"hainan",   SIQuarterSpeedModel, [FeatureISAVersion6_0_1]>;
 
 //===----------------------------------------------------------------------===//
 // Sea Islands
 //===----------------------------------------------------------------------===//
 
-def : ProcessorModel<"bonaire",    SIQuarterSpeedModel,
+def : ProcessorModel<"gfx700",     SIQuarterSpeedModel,
   [FeatureISAVersion7_0_0]
 >;
 
-def : ProcessorModel<"kabini",     SIQuarterSpeedModel,
-  [FeatureISAVersion7_0_2]
+def : ProcessorModel<"bonaire",    SIQuarterSpeedModel,
+  [FeatureISAVersion7_0_0]
 >;
 
 def : ProcessorModel<"kaveri",     SIQuarterSpeedModel,
   [FeatureISAVersion7_0_0]
 >;
 
-def : ProcessorModel<"hawaii",     SIFullSpeedModel,
+def : ProcessorModel<"gfx701",     SIFullSpeedModel,
   [FeatureISAVersion7_0_1]
 >;
 
-def : ProcessorModel<"mullins",    SIQuarterSpeedModel,
-  [FeatureISAVersion7_0_2]>;
-
-def : ProcessorModel<"gfx700",     SIQuarterSpeedModel,
-  [FeatureISAVersion7_0_0]
->;
-
-def : ProcessorModel<"gfx701",     SIFullSpeedModel,
+def : ProcessorModel<"hawaii",     SIFullSpeedModel,
   [FeatureISAVersion7_0_1]
 >;
 
 def : ProcessorModel<"gfx702",     SIQuarterSpeedModel,
   [FeatureISAVersion7_0_2]
 >;
 
+def : ProcessorModel<"gfx703",     SIQuarterSpeedModel,
+  [FeatureISAVersion7_0_3]
+>;
+
+def : ProcessorModel<"kabini",     SIQuarterSpeedModel,
+  [FeatureISAVersion7_0_3]
+>;
+
+def : ProcessorModel<"mullins",    SIQuarterSpeedModel,
+  [FeatureISAVersion7_0_3]>;
+
 //===----------------------------------------------------------------------===//
 // Volcanic Islands
 //===----------------------------------------------------------------------===//
 
 def : ProcessorModel<"tonga",   SIQuarterSpeedModel,
   [FeatureISAVersion8_0_2]
 >;
 

 def : ProcessorModel<"gfx804", SIQuarterSpeedModel,
   [FeatureISAVersion8_0_4]
 >;
 
 def : ProcessorModel<"gfx810", SIQuarterSpeedModel,
   [FeatureISAVersion8_1_0]
 >;
 
 def : ProcessorModel<"gfx900",   SIQuarterSpeedModel,
   [FeatureGFX9, FeatureISAVersion9_0_0, FeatureLDSBankCount32]
 >;
 
 def : ProcessorModel<"gfx901",   SIQuarterSpeedModel,
   [FeatureGFX9, FeatureXNACK, FeatureISAVersion9_0_1, FeatureLDSBankCount32]
 >;
+
+def : ProcessorModel<"gfx902",   SIQuarterSpeedModel,
+  [FeatureGFX9, FeatureISAVersion9_0_2, FeatureLDSBankCount32]
+>;
+
+def : ProcessorModel<"gfx903",   SIQuarterSpeedModel,
+  [FeatureGFX9, FeatureXNACK, FeatureISAVersion9_0_3, FeatureLDSBankCount32]
+>;
+

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

static cl::opt<bool> EnablePackedInlinableLiterals(
     cl::desc("Enable packed inlinable literals (v2f16, v2i16)"),
     cl::init(false));
 
 namespace AMDGPU {
 
 namespace IsaInfo {
 
 IsaVersion getIsaVersion(const FeatureBitset &Features) {
+  // SI
+  if (Features.test(FeatureISAVersion6_0_0))
+    return {6, 0, 0};
+  if (Features.test(FeatureISAVersion6_0_1))
+    return {6, 0, 1};
   // CI.
   if (Features.test(FeatureISAVersion7_0_0))
     return {7, 0, 0};
   if (Features.test(FeatureISAVersion7_0_1))
     return {7, 0, 1};
   if (Features.test(FeatureISAVersion7_0_2))
     return {7, 0, 2};
+  if (Features.test(FeatureISAVersion7_0_3))
+    return {7, 0, 3};
 
   // VI.
   if (Features.test(FeatureISAVersion8_0_0))
     return {8, 0, 0};
   if (Features.test(FeatureISAVersion8_0_1))
     return {8, 0, 1};
   if (Features.test(FeatureISAVersion8_0_2))
     return {8, 0, 2};
   if (Features.test(FeatureISAVersion8_0_3))
     return {8, 0, 3};
   if (Features.test(FeatureISAVersion8_0_4))
     return {8, 0, 4};
   if (Features.test(FeatureISAVersion8_1_0))
     return {8, 1, 0};
 
   // GFX9.
   if (Features.test(FeatureISAVersion9_0_0))
     return {9, 0, 0};
   if (Features.test(FeatureISAVersion9_0_1))
     return {9, 0, 1};
+  if (Features.test(FeatureISAVersion9_0_2))
+    return {9, 0, 2};
+  if (Features.test(FeatureISAVersion9_0_3))
+    return {9, 0, 3};
 
   if (!Features.test(FeatureGCN) || Features.test(FeatureSouthernIslands))
     return {0, 0, 0};
-  return {7, 0, 0};
+
+  assert(false && "Cannot get an ISA version.\n");
 }
 
 unsigned getWavefrontSize(const FeatureBitset &Features) {
   if (Features.test(FeatureWavefrontSize16))
     return 16;
   if (Features.test(FeatureWavefrontSize32))
     return 32;
 

test/CodeGen/AMDGPU/hsa-note-no-func.ll

+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx600 | FileCheck --check-prefix=HSA --check-prefix=HSA-SI600 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx601 | FileCheck --check-prefix=HSA --check-prefix=HSA-SI601 %s
 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx700 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI700 %s
 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx701 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI701 %s
 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx702 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI702 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx703 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI703 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=mullins | FileCheck --check-prefix=HSA --check-prefix=HSA-CI702 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=hawaii | FileCheck --check-prefix=HSA --check-prefix=HSA-CI702 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kabini | FileCheck --check-prefix=HSA --check-prefix=HSA-CI702 %s
 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck --check-prefix=HSA --check-prefix=HSA-CI700 %s
 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=-flat-for-global | FileCheck --check-prefix=HSA --check-prefix=HSA-VI801 %s
 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=tonga -mattr=-flat-for-global | FileCheck --check-prefix=HSA --check-prefix=HSA-VI802 %s
 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=-flat-for-global | FileCheck --check-prefix=HSA --check-prefix=HSA-VI803 %s
 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=polaris10 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI803 %s
 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=polaris11 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI803 %s
 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx800 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI800 %s
 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx801 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI801 %s
 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx802 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI802 %s
 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx803 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI803 %s
 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx804 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI804 %s
 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx810 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI810 %s
 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx900 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX900 %s
 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx901 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX901 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx902 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX902 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx903 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX903 %s
 
 ; HSA: .hsa_code_object_version 2,1
+; HSA-SI600: .hsa_code_object_isa 6,0,0,"AMD","AMDGPU"
+; HSA-SI601: .hsa_code_object_isa 6,0,1,"AMD","AMDGPU"
 ; HSA-CI700: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
 ; HSA-CI701: .hsa_code_object_isa 7,0,1,"AMD","AMDGPU"
 ; HSA-CI702: .hsa_code_object_isa 7,0,2,"AMD","AMDGPU"
+; HSA-CI703: .hsa_code_object_isa 7,0,3,"AMD","AMDGPU"
 ; HSA-VI800: .hsa_code_object_isa 8,0,0,"AMD","AMDGPU"
 ; HSA-VI801: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU"
 ; HSA-VI802: .hsa_code_object_isa 8,0,2,"AMD","AMDGPU"
 ; HSA-VI803: .hsa_code_object_isa 8,0,3,"AMD","AMDGPU"
 ; HSA-VI804: .hsa_code_object_isa 8,0,4,"AMD","AMDGPU"
 ; HSA-VI810: .hsa_code_object_isa 8,1,0,"AMD","AMDGPU"
 ; HSA-GFX900: .hsa_code_object_isa 9,0,0,"AMD","AMDGPU"
 ; HSA-GFX901: .hsa_code_object_isa 9,0,1,"AMD","AMDGPU"
+; HSA-GFX902: .hsa_code_object_isa 9,0,2,"AMD","AMDGPU"
+; HSA-GFX903: .hsa_code_object_isa 9,0,3,"AMD","AMDGPU"

test/MC/AMDGPU/sym_option.s

 // TONGA: .byte 0
 // FIJI: .byte 0
 // GFX804: .byte 0
 // STONEY: .byte 1
 
 .byte .option.machine_version_stepping
 // SI: .byte 0
 // BONAIRE: .byte 0
-// HAWAII: .byte 1
+// HAWAII: .byte 2
 // KABINI: .byte 2
 // ICELAND: .byte 0
 // CARRIZO: .byte 1
 // TONGA: .byte 2
 // FIJI: .byte 3
 // GFX804: .byte 4
 // STONEY: .byte 0