[globalisel] Tablegen-erate PartialMapping*/ValueMapping*/BankIDToCopyMapIdx.

[dsanders]

Summary

Note that the order of register banks in the tables swaps as a result. This has
no effect on behaviour because of the fixes in r288812. Also, a couple fields
are not controllable from the .td files because there's no variety in the
current values (NumBreakDowns of RegisterBankInfo::ValueMapping is always 1,
and StartIdx of RegisterBankInfo::PartialMapping, is always 0).

Depends on D27339

[rovka]

utils/TableGen/RegisterBankEmitter.cpp

372

This function is growing a bit long, could you split it up a bit?

386

These used to start at 1, they will start at 0 now - is this intentional?

390

Bank.hasPartialMappings()?

[dsanders]

utils/TableGen/RegisterBankEmitter.cpp

372

Ok.

386

Yes, but it might be better to leave it for a later patch. I've only got a weak argument for either value.

The argument in favour of 0 is that that's what it was before r288812. That commit changed it to 1 to demonstrate that it had caught all the places where it was either using -PMI_FirstGPR (calls FirstGPR at the time) or had forgotten to include a subtraction. Now that this has been fixed, it's getting less important as we tablegen-erate more.

The argument in favour of 1 is that there's still a couple bits that haven't been tablegen-erated yet such as the asserts in AArch64RegisterBankInfo::AArch64RegisterBankInfo().

390

Thanks. I missed this one.

[dsanders]

Update to account for Diana's comments:

• Split up emitRegisterBankInfoImplementation()
• Call Bank.hasPartialMappings() instead of repeating its implementation

[qcolombet]

Hi Daniel,

I think I already mentioned that in another review, but I expect the generation of the mappings to be part of some instruction selector tablegen backend. Indeed a mapping is bound to an instruction, not a register bank. The mappings happen to use register banks but are not derived from them, thus I don't think it makes sense to have their generation in the RegisterBankEmitter.

Cheers,
-Quentin

lib/Target/AArch64/AArch64GenRegisterBankInfo.def

73

Looks like general goodness, commit that part separately.

[dsanders]

We committed a different patch series instead.

lib/Target/AArch64/AArch64GenRegisterBankInfo.def

 
 #ifndef LLVM_BUILD_GLOBAL_ISEL
 #error "You shouldn't build this"
 #endif
 
 namespace llvm {
 namespace AArch64 {
 
-// PartialMappings.
-enum PartialMappingIdx {
-  PMI_None = -1,
-  PMI_GPR32 = 1,
-  PMI_GPR64,
-  PMI_FPR32,
-  PMI_FPR64,
-  PMI_FPR128,
-  PMI_FPR256,
-  PMI_FPR512,
-  PMI_FirstGPR = PMI_GPR32,
-  PMI_LastGPR = PMI_GPR64,
-  PMI_FirstFPR = PMI_FPR32,
-  PMI_LastFPR = PMI_FPR512,
-  PMI_Min = PMI_FirstGPR,
-};
-
 static unsigned getRegBankBaseIdxOffset(unsigned Size) {
   assert(Size && "0-sized type!!");
   // Make anything smaller than 32 gets 32
   Size = ((Size + 31) / 32) * 32;
   // 32 is 0, 64 is 1, 128 is 2, and so on.
   return Log2_32(Size) - /*Log2_32(32)=*/ 5;
 }
 
-RegisterBankInfo::PartialMapping PartMappings[] {
-  /* StartIdx, Length, RegBank */
-  // 0: GPR 32-bit value.
-  {0, 32, GPRRegBank},
-  // 1: GPR 64-bit value.
-  {0, 64, GPRRegBank},
-  // 2: FPR 32-bit value.
-  {0, 32, FPRRegBank},
-  // 3: FPR 64-bit value.
-  {0, 64, FPRRegBank},
-  // 4: FPR 128-bit value.
-  {0, 128, FPRRegBank},
-  // 5: FPR 256-bit value.
-  {0, 256, FPRRegBank},
-  // 6: FPR 512-bit value.
-  {0, 512, FPRRegBank}
-};
-
-enum ValueMappingIdx {
-  First3OpsIdx = 0,
-  Last3OpsIdx = 18,
-  DistanceBetweenRegBanks = 3,
-  FirstCrossRegCpyIdx = 21,
-  LastCrossRegCpyIdx = 27,
-  DistanceBetweenCrossRegCpy = 2
-};
-
-// ValueMappings.
-RegisterBankInfo::ValueMapping ValMappings[]{
-    /* BreakDown, NumBreakDowns */
-    // 3-operands instructions (all binary operations should end up with one of
-    // those mapping).
-    // 0: GPR 32-bit value. <-- This must match First3OpsIdx.
-    {&PartMappings[PMI_GPR32 - PMI_Min], 1},
-    {&PartMappings[PMI_GPR32 - PMI_Min], 1},
-    {&PartMappings[PMI_GPR32 - PMI_Min], 1},
-    // 3: GPR 64-bit value.
-    {&PartMappings[PMI_GPR64 - PMI_Min], 1},
-    {&PartMappings[PMI_GPR64 - PMI_Min], 1},
-    {&PartMappings[PMI_GPR64 - PMI_Min], 1},
-    // 6: FPR 32-bit value.
-    {&PartMappings[PMI_FPR32 - PMI_Min], 1},
-    {&PartMappings[PMI_FPR32 - PMI_Min], 1},
-    {&PartMappings[PMI_FPR32 - PMI_Min], 1},
-    // 9: FPR 64-bit value.
-    {&PartMappings[PMI_FPR64 - PMI_Min], 1},
-    {&PartMappings[PMI_FPR64 - PMI_Min], 1},
-    {&PartMappings[PMI_FPR64 - PMI_Min], 1},
-    // 12: FPR 128-bit value.
-    {&PartMappings[PMI_FPR128 - PMI_Min], 1},
-    {&PartMappings[PMI_FPR128 - PMI_Min], 1},
-    {&PartMappings[PMI_FPR128 - PMI_Min], 1},
-    // 15: FPR 256-bit value.
-    {&PartMappings[PMI_FPR256 - PMI_Min], 1},
-    {&PartMappings[PMI_FPR256 - PMI_Min], 1},
-    {&PartMappings[PMI_FPR256 - PMI_Min], 1},
-    // 18: FPR 512-bit value. <-- This must match Last3OpsIdx.
-    {&PartMappings[PMI_FPR512 - PMI_Min], 1},
-    {&PartMappings[PMI_FPR512 - PMI_Min], 1},
-    {&PartMappings[PMI_FPR512 - PMI_Min], 1},
-    // Cross register bank copies.
-    // 21: GPR 32-bit value to FPR 32-bit value. <-- This must match
-    //                                               FirstCrossRegCpyIdx.
-    {&PartMappings[PMI_GPR32 - PMI_Min], 1},
-    {&PartMappings[PMI_FPR32 - PMI_Min], 1},
-    // 23: GPR 64-bit value to FPR 64-bit value.
-    {&PartMappings[PMI_GPR64 - PMI_Min], 1},
-    {&PartMappings[PMI_FPR64 - PMI_Min], 1},
-    // 25: FPR 32-bit value to GPR 32-bit value.
-    {&PartMappings[PMI_FPR32 - PMI_Min], 1},
-    {&PartMappings[PMI_GPR32 - PMI_Min], 1},
-    // 27: FPR 64-bit value to GPR 64-bit value. <-- This must match
-    //                                               LastCrossRegCpyIdx.
-    {&PartMappings[PMI_FPR64 - PMI_Min], 1},
-    {&PartMappings[PMI_GPR64 - PMI_Min], 1}
-};
+extern RegisterBankInfo::ValueMapping ValMappings[];
 
 /// Get the pointer to the ValueMapping representing the RegisterBank
 /// at \p RBIdx with a size of \p Size.
 ///
 /// The returned mapping works for instructions with the same kind of
 /// operands for up to 3 operands.
 ///
 /// \pre \p RBIdx != PartialMappingIdx::None
 const RegisterBankInfo::ValueMapping *
 getValueMapping(PartialMappingIdx RBIdx, unsigned Size) {
   assert(RBIdx != PartialMappingIdx::PMI_None && "No mapping needed for that");
   unsigned ValMappingIdx = First3OpsIdx +
                            (RBIdx - AArch64::PartialMappingIdx::PMI_Min +
                             getRegBankBaseIdxOffset(Size)) *
                                ValueMappingIdx::DistanceBetweenRegBanks;
   assert(ValMappingIdx >= AArch64::First3OpsIdx &&
          ValMappingIdx <= AArch64::Last3OpsIdx && "Mapping out of bound");
 
   return &ValMappings[ValMappingIdx];
 }
 
-PartialMappingIdx BankIDToCopyMapIdx[] {
-  PMI_None, // CCR
-  PMI_FirstFPR, // FPR
-  PMI_FirstGPR, // GPR
-};
-
 /// Get the pointer to the ValueMapping of the operands of a copy
 /// instruction from the \p SrcBankID register bank to the \p DstBankID
 /// register bank with a size of \p Size.
 const RegisterBankInfo::ValueMapping *
 getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size) {
   assert(DstBankID < NumRegisterBanks && "Invalid bank ID");
   assert(SrcBankID < NumRegisterBanks && "Invalid bank ID");
   PartialMappingIdx DstRBIdx = BankIDToCopyMapIdx[DstBankID];
   PartialMappingIdx SrcRBIdx = BankIDToCopyMapIdx[SrcBankID];
   assert(DstRBIdx != PMI_None && "No such mapping");
   assert(SrcRBIdx != PMI_None && "No such mapping");
 
   if (DstRBIdx == SrcRBIdx)
     return getValueMapping(DstRBIdx, Size);
   assert(Size <= 64 && "GPR cannot handle that size");
   unsigned ValMappingIdx =
       FirstCrossRegCpyIdx +
       (DstRBIdx - PMI_Min + getRegBankBaseIdxOffset(Size)) *
           ValueMappingIdx::DistanceBetweenCrossRegCpy;
   assert(ValMappingIdx >= AArch64::FirstCrossRegCpyIdx &&
          ValMappingIdx <= AArch64::LastCrossRegCpyIdx &&
          "Mapping out of bound");
+  assert(ValMappings[ValMappingIdx].BreakDown != nullptr && "Hit an invalid copy");
   return &ValMappings[ValMappingIdx];
 }
 
 } // End AArch64 namespace.
 } // End llvm namespace.

lib/Target/AArch64/AArch64RegisterBankInfo.cpp

 #include "AArch64InstrInfo.h" // For XXXRegClassID.
 #include "llvm/CodeGen/LowLevelType.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/Target/TargetSubtargetInfo.h"
 
+#define TBLGEN_REGISTERBANKINFO_CPP_EARLY
+#include "AArch64GenRegisterBank.inc"
 // This file will be TableGen'ed at some point.
 #include "AArch64GenRegisterBankInfo.def"
 #define GET_REGBANK_IFACE_IMPL
 #include "AArch64GenRegisterBank.inc"
 
 using namespace llvm;
 
 #ifndef LLVM_BUILD_GLOBAL_ISEL

utils/TableGen/RegisterBankEmitter.cpp

PartialMappings.erase(
         std::unique(PartialMappings.begin(), PartialMappings.end()),
         PartialMappings.end());
   }
 
   bool hasPartialMappings() const {
     return partial_mappings().begin() != partial_mappings().end();
   }
 
+  bool hasPartialMapping(unsigned Size) const {
+    return std::find(partial_mappings().begin(), partial_mappings().end(),
+                     Size) != partial_mappings().end();
+  }
+
   /// This range is not valid if finalizePartialMappings() has not been
   /// called.
   iterator_range<typename PartialMappingsTy::const_iterator>
   partial_mappings() const {
     return llvm::make_range(PartialMappings.begin(), PartialMappings.end());
   }
+
+  bool operator==(const RegisterBank &Other) const {
+    return getName() == Other.getName();
+  }
 };
 
 class RegisterBankEmitter {
 private:
   RecordKeeper &Records;
   CodeGenRegBank RegisterClassHierarchy;
 
   void emitHeader(raw_ostream &OS, const StringRef TargetName,
                   const std::vector<RegisterBank> &Banks);
   void emitRegisterBankInfoPrivateMembers(raw_ostream &OS);
+  void emitPartialMappingsIdxEnum(raw_ostream &OS,
+                                  std::vector<RegisterBank> &Banks);
+  void emitPartMappingsArray(raw_ostream &OS, std::vector<RegisterBank> &Banks);
+  void emitValMappingsArrayAndIndexes(raw_ostream &OS,
+                                      std::vector<RegisterBank> &Banks);
   void
   emitRegisterBankInfoImplementation(raw_ostream &OS,
                                      const StringRef TargetName,
                                      std::vector<RegisterBank> &Banks);
 
 public:
   RegisterBankEmitter(RecordKeeper &R)
       : Records(R), RegisterClassHierarchy(Records) {}
for (RegisterBank::PartialMappingsTy::const_iterator I = Begin; I + 1 != End;
        ++I) {
     OS << Enumeration << "::" << EnumeratorPrefix << *I
        << " + 1 == " << Enumeration << "::" << EnumeratorPrefix << *(I + 1)
        << " &&\n           ";
   }
   OS << "\"" << EnumeratorPrefix << " indices not properly ordered\");\n";
 }
 
+/// Emit PartialMappingsIdx.
+void RegisterBankEmitter::emitPartialMappingsIdxEnum(
+    raw_ostream &OS, std::vector<RegisterBank> &Banks) {
+  OS << "// PartialMappings.\n"
+     << "enum PartialMappingIdx {\n"
+     << "  PMI_None = -1,\n";
+
+  for (const auto &Bank : Banks)
+    for (const auto &PartialMappingSize : Bank.partial_mappings())
+      OS << "  PMI_" << Bank.getName() << PartialMappingSize << ",\n";
+
+  const RegisterBank *FirstEmittedBank = nullptr;
+  for (const auto &Bank : Banks) {
+    if (Bank.hasPartialMappings()) {
+      if (FirstEmittedBank == nullptr)
+        FirstEmittedBank = &Bank;
+      OS << "  PMI_First" << Bank.getName() << " = PMI_" << Bank.getName()
+         << *Bank.partial_mappings().begin() << ",\n";
+      OS << "  PMI_Last" << Bank.getName() << " = PMI_" << Bank.getName()
+         << *(Bank.partial_mappings().end() - 1) << ",\n";
+    }
+  }
+  if (FirstEmittedBank)
+    OS << "  PMI_Min = PMI_First" << FirstEmittedBank->getName() << "\n";
+  OS << "};\n\n";
+}
+
+/// Emit PartMappings.
+void RegisterBankEmitter::emitPartMappingsArray(
+    raw_ostream &OS, std::vector<RegisterBank> &Banks) {
+  OS << "// { StartIdx, Length, RegBank }\n"
+     << "RegisterBankInfo::PartialMapping PartMappings[] {\n";
+  for (const auto &Bank : Banks)
+    for (const auto &Size : Bank.partial_mappings())
+      OS << "  {0, " << Size << ", " << Bank.getInstanceVarName() << "},\n";
+  OS << "};\n"
+     << "\n";
+}
+
+/// Emit ValMappings, the anonymous index representing start and end of the 3-op
+/// and cross register bank copy regions, and the BankIDToCopyMapIdx index.
+void RegisterBankEmitter::emitValMappingsArrayAndIndexes(
+    raw_ostream &OS, std::vector<RegisterBank> &Banks) {
+  std::string BankIDToCopyMapIdxEntriesStr;
+  raw_string_ostream BankIDToCopyMapIdxEntries(BankIDToCopyMapIdxEntriesStr);
+
+  std::string ValMappingIdxEnumeratorsStr;
+  raw_string_ostream ValMappingIdxEnumerators(ValMappingIdxEnumeratorsStr);
+  unsigned ValMappingIdx = 0;
+
+  OS << "RegisterBankInfo::ValueMapping ValMappings[] {\n"
+     << "  /* BreakDown, NumBreakDowns */\n"
+     << "  // 3-operands instructions (all binary operations should end up\n"
+     << "  // with one of those mappings).\n";
+  ValMappingIdxEnumerators << "  First3OpsIdx = " << ValMappingIdx << ",\n";
+  for (const auto &Bank : Banks) {
+    for (const auto &Size : Bank.partial_mappings()) {
+      OS << "  // " << Bank.getName() << Size << "\n ";
+      for (unsigned I = 0; I < 3; ++I, ++ValMappingIdx)
+        OS << " {&PartMappings[PMI_" << Bank.getName() << Size
+           << " - PMI_Min], 1},";
+      OS << "\n";
+    }
+  }
+  ValMappingIdxEnumerators << "  Last3OpsIdx = " << ValMappingIdx << ",\n";
+
+  OS << "  // Cross register bank copies.\n";
+  ValMappingIdxEnumerators << "  FirstCrossRegCpyIdx = " << ValMappingIdx
+                           << ",\n";
+  for (const auto &Bank : Banks) {
+    if (!Bank.hasPartialMappings()) {
+      BankIDToCopyMapIdxEntries << "  PMI_None,\n";
+      continue;
+    }
+
+    BankIDToCopyMapIdxEntries << "  PMI_First" << Bank.getName() << ",\n";
+
+    for (const auto &Size : Bank.partial_mappings()) {
+      for (const auto &OtherBank : Banks) {
+        if (Bank == OtherBank || !OtherBank.hasPartialMappings())
+          continue;
+
+        OS << "  // " << Bank.getName() << Size << " -> " << OtherBank.getName()
+           << Size << "\n";
+
+        if (OtherBank.hasPartialMapping(Size)) {
+          OS << "  {&PartMappings[PMI_" << Bank.getName() << Size
+             << " - PMI_Min], 1}, ";
+          OS << "{&PartMappings[PMI_" << OtherBank.getName() << Size
+             << " - PMI_Min], 1},\n";
+        } else
+          OS << "  {nullptr, 0}, {nullptr, 0},\n";
+
+        ValMappingIdx += 2;
+      }
+    }
+  }
+  ValMappingIdxEnumerators << "  LastCrossRegCpyIdx = " << ValMappingIdx
+                           << ",\n";
+
+  OS << "};\n\n";
+
+  OS << "enum ValueMappingIdx {\n"
+     << ValMappingIdxEnumerators.str() << "  DistanceBetweenRegBanks = 3,\n"
+                                          "  DistanceBetweenCrossRegCpy = 2\n"
+                                          "};\n\n";
+
+  OS << "PartialMappingIdx BankIDToCopyMapIdx[] {\n"
+     << BankIDToCopyMapIdxEntries.str() << "  PMI_None,\n"
+     << "};\n\n";
+
+}
+
 void RegisterBankEmitter::emitRegisterBankInfoImplementation(
     raw_ostream &OS, StringRef TargetName,
     std::vector<RegisterBank> &Banks) {
   // <Target>RegisterBankInfo.cpp
+  OS << "#ifdef TBLGEN_REGISTERBANKINFO_CPP_EARLY\n"
+     << "#undef TBLGEN_REGISTERBANKINFO_CPP_EARLY\n"
+     << "namespace llvm {\n"
+     << "namespace " << TargetName << " {\n";
+  emitPartialMappingsIdxEnum(OS, Banks);
+  emitPartMappingsArray(OS, Banks);
+  emitValMappingsArrayAndIndexes(OS, Banks);
+  OS << "}\n"
+     << "} // end namespace llvm\n"
+     << "#endif // TBLGEN_REGISTERBANKINFO_CPP_EARLY\n";
+
   OS << "#ifdef GET_REGBANK_IFACE_IMPL\n"
      << "#undef GET_REGBANK_IFACE_IMPL\n"
      << "namespace llvm {\n"
      << "namespace " << TargetName << " {\n";
 
   // Declare the global instance variables.
   OS << "RegisterBank NoRegisterBank;\n";
   for (const auto &Bank : Banks)
     OS << "RegisterBank " << Bank.getInstanceVarName() << ";\n";
   OS << "\n";
 
   // Declare the map of ID's to global instance variables.