[globalisel][aarch64] Replace magic numbers with corresponding enumerators in ValMappings. NFC

[qcolombet]

LGTM modulo minor nitpicks.

lib/Target/AArch64/AArch64GenRegisterBankInfo.def

30

I'd use a shorter name: MinIdx or FirstIdx

79–80

Could you clang-format those lines?

[dsanders]

lib/Target/AArch64/AArch64GenRegisterBankInfo.def

30

I was concerned about polluting the llvm::AArch64 namespace with generic-sounding identifiers. Looking at it again, this enum isn't in line with the coding standards (enumerators should have a common prefix) and fixing that would fix this problem. I think we should prefix them all with 'PMI_' to get:

PMI_None,
PMI_GPR32,
...
PMI_LastFPR = PMI_FPR512,
PMI_Min = PMI_FirstGPR

Is that ok with you?

79–80

Ok.

[dsanders]

Rebase and fix nits

lib/Target/AArch64/AArch64GenRegisterBankInfo.def

 RegisterBank FPRRegBank;
 RegisterBank CCRRegBank;
 
 RegisterBank *RegBanks[] = {&GPRRegBank, &FPRRegBank, &CCRRegBank};
 
 // PartialMappings.
 enum PartialMappingIdx {
   PMI_None = -1,
   PMI_GPR32 = 0,
   PMI_GPR64,
   PMI_FPR32,
   PMI_FPR64,
   PMI_FPR128,
   PMI_FPR256,
   PMI_FPR512,
   PMI_FirstGPR = PMI_GPR32,
   PMI_LastGPR = PMI_GPR64,
   PMI_FirstFPR = PMI_FPR32,
-  PMI_LastFPR = PMI_FPR512
+  PMI_LastFPR = PMI_FPR512,
+  PMI_Min = PMI_FirstGPR,
 };
 
 static unsigned getRegBankBaseIdxOffset(unsigned Size) {
   assert(Size && "0-sized type!!");
   // Make anything smaller than 32 gets 32
   Size = ((Size + 31) / 32) * 32;
   // 32 is 0, 64 is 1, 128 is 2, and so on.
   return Log2_32(Size) - /*Log2_32(32)=*/ 5;
enum ValueMappingIdx {
   First3OpsIdx = 0,
   Last3OpsIdx = 18,
   DistanceBetweenRegBanks = 3,
   FirstCrossRegCpyIdx = 21,
   LastCrossRegCpyIdx = 27,
   DistanceBetweenCrossRegCpy = 2
 };
 
 // ValueMappings.
-RegisterBankInfo::ValueMapping ValMappings[] {
+RegisterBankInfo::ValueMapping ValMappings[]{
     /* BreakDown, NumBreakDowns */
     // 3-operands instructions (all binary operations should end up with one of
     // those mapping).
     // 0: GPR 32-bit value. <-- This must match First3OpsIdx.
-  {&PartMappings[0], 1}, {&PartMappings[0], 1}, {&PartMappings[0], 1},
+    {&PartMappings[PMI_GPR32 - PMI_Min], 1},
+    {&PartMappings[PMI_GPR32 - PMI_Min], 1},
+    {&PartMappings[PMI_GPR32 - PMI_Min], 1},
     // 3: GPR 64-bit value.
-  {&PartMappings[1], 1}, {&PartMappings[1], 1}, {&PartMappings[1], 1},
+    {&PartMappings[PMI_GPR64 - PMI_Min], 1},
+    {&PartMappings[PMI_GPR64 - PMI_Min], 1},
+    {&PartMappings[PMI_GPR64 - PMI_Min], 1},
     // 6: FPR 32-bit value.
-  {&PartMappings[2], 1}, {&PartMappings[2], 1}, {&PartMappings[2], 1},
+    {&PartMappings[PMI_FPR32 - PMI_Min], 1},
+    {&PartMappings[PMI_FPR32 - PMI_Min], 1},
+    {&PartMappings[PMI_FPR32 - PMI_Min], 1},
     // 9: FPR 64-bit value.
-  {&PartMappings[3], 1}, {&PartMappings[3], 1}, {&PartMappings[3], 1},
+    {&PartMappings[PMI_FPR64 - PMI_Min], 1},
+    {&PartMappings[PMI_FPR64 - PMI_Min], 1},
+    {&PartMappings[PMI_FPR64 - PMI_Min], 1},
     // 12: FPR 128-bit value.
-  {&PartMappings[4], 1}, {&PartMappings[4], 1}, {&PartMappings[4], 1},
+    {&PartMappings[PMI_FPR128 - PMI_Min], 1},
+    {&PartMappings[PMI_FPR128 - PMI_Min], 1},
+    {&PartMappings[PMI_FPR128 - PMI_Min], 1},
     // 15: FPR 256-bit value.
-  {&PartMappings[5], 1}, {&PartMappings[5], 1}, {&PartMappings[5], 1},
+    {&PartMappings[PMI_FPR256 - PMI_Min], 1},
+    {&PartMappings[PMI_FPR256 - PMI_Min], 1},
+    {&PartMappings[PMI_FPR256 - PMI_Min], 1},
     // 18: FPR 512-bit value. <-- This must match Last3OpsIdx.
-  {&PartMappings[6], 1}, {&PartMappings[6], 1}, {&PartMappings[6], 1},
+    {&PartMappings[PMI_FPR512 - PMI_Min], 1},
+    {&PartMappings[PMI_FPR512 - PMI_Min], 1},
+    {&PartMappings[PMI_FPR512 - PMI_Min], 1},
     // Cross register bank copies.
-  // 21: GPR 32-bit value to FPR 32-bit value. <-- This must match FirstCrossRegCpyIdx.
-  {&PartMappings[0], 1}, {&PartMappings[2], 1},
+    // 21: GPR 32-bit value to FPR 32-bit value. <-- This must match
+    //                                               FirstCrossRegCpyIdx.
+    {&PartMappings[PMI_GPR32 - PMI_Min], 1},
+    {&PartMappings[PMI_FPR32 - PMI_Min], 1},
     // 23: GPR 64-bit value to FPR 64-bit value.
-  {&PartMappings[1], 1}, {&PartMappings[3], 1},
+    {&PartMappings[PMI_GPR64 - PMI_Min], 1},
+    {&PartMappings[PMI_FPR64 - PMI_Min], 1},
     // 25: FPR 32-bit value to GPR 32-bit value.
-  {&PartMappings[2], 1}, {&PartMappings[0], 1},
-  // 27: FPR 64-bit value to GPR 64-bit value. <-- This must match LastCrossRegCpyIdx.
-  {&PartMappings[3], 1}, {&PartMappings[1], 1}
-
+    {&PartMappings[PMI_FPR32 - PMI_Min], 1},
+    {&PartMappings[PMI_GPR32 - PMI_Min], 1},
+    // 27: FPR 64-bit value to GPR 64-bit value. <-- This must match
+    //                                               LastCrossRegCpyIdx.
+    {&PartMappings[PMI_FPR64 - PMI_Min], 1},
+    {&PartMappings[PMI_GPR64 - PMI_Min], 1}
 };
 
 /// Get the pointer to the ValueMapping representing the RegisterBank
 /// at \p RBIdx with a size of \p Size.
 ///
 /// The returned mapping works for instructions with the same kind of
 /// operands for up to 3 operands.
 ///