[AArch64LoadStoreOptimizer] Don't treat write to XZR/WZR as a clobber.

[gberry]

Summary

When searching for load/store instructions to pair/merge don't treat
writes to WZR/XZR as clobbers since they don't change the value read
from WZR/XZR (which is always 0).

[junbuml]

test/CodeGen/AArch64/ldst-opt.ll

1559

typo: pariing

1561

I cannot see difference with/without this patch in this test. It appears that there is no instruction between the two stores.

[gberry]

test/CodeGen/AArch64/ldst-opt.ll

1561

This test is sensitive to changes in instruction scheduling. I can re-write this as a MIR test that just runs the aarch64-ldst optimization to make it more robust.

[gberry]

Fix typo and update test to MIR so it isn't effected by changes in instruction scheduling.

[junbuml]

LGTM

lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

if (MO.isRegMask())
       ModifiedRegs.setBitsNotInMask(MO.getRegMask());
 
     if (!MO.isReg())
       continue;
     unsigned Reg = MO.getReg();
     if (!Reg)
       continue;
     if (MO.isDef()) {
+      // WZR/XZR are not modified even when used as a destination register.
+      if (Reg != AArch64::WZR && Reg != AArch64::XZR)
         for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
           ModifiedRegs.set(*AI);
     } else {
       assert(MO.isUse() && "Reg operand not a def and not a use?!?");
       for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
         UsedRegs.set(*AI);
     }
   }
 }
 

test/CodeGen/AArch64/ldst-opt.ll

 ; CHECK: // %entry
 ; CHECK-NEXT: movi v[[REG:[0-9]]].2d, #0000000000000000
 ; CHECK-NEXT: stp q[[REG]], q[[REG]], [x{{[0-9]+}}]
 ; CHECK-NEXT: ret
 entry:
   store <4 x double> zeroinitializer, <4 x double>* %p
   ret void
 }
+
+; Check that write of xzr doesn't inhibit pariing of xzr stores since
+; it isn't actually clobbered.
+define i1 @no-clobber-zr(i64* %p, i64 %x) nounwind {
+; CHECK-LABEL: no-clobber-zr
+; CHECK: stp xzr, xzr, [x{{[0-9]+}}]
+entry:
+  store i64 0, i64* %p
+  %cond = icmp eq i64 %x, 0
+  %p1 = getelementptr i64, i64* %p, i64 1
+  store i64 0, i64* %p1
+  ret i1 %cond
+}