[PowerPC] Add vector conversion builtins to altivec.h - LLVM portion

[nemanjai]

Summary

This adds the intrinsics required for these builtins to the PowerPC back end.

[kbarton]

LGTM

[nemanjai]

Committed revision 286596.

include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_vsx_xxleqv :
       PowerPC_VSX_Intrinsic<"xxleqv", [llvm_v4i32_ty],
                             [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
 def int_ppc_vsx_xviexpdp :
       PowerPC_VSX_Intrinsic<"xviexpdp",[llvm_v2f64_ty],
                             [llvm_v2i64_ty, llvm_v2i64_ty],[IntrNoMem]>;
 def int_ppc_vsx_xviexpsp :
       PowerPC_VSX_Intrinsic<"xviexpsp",[llvm_v4f32_ty],
                             [llvm_v4i32_ty, llvm_v4i32_ty],[IntrNoMem]>;
+def int_ppc_vsx_xvcvdpsxws :
+      PowerPC_VSX_Intrinsic<"xvcvdpsxws", [llvm_v4i32_ty],
+                            [llvm_v2f64_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvcvdpuxws :
+      PowerPC_VSX_Intrinsic<"xvcvdpuxws", [llvm_v4i32_ty],
+                            [llvm_v2f64_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvcvsxwdp :
+      PowerPC_VSX_Intrinsic<"xvcvsxwdp", [llvm_v2f64_ty],
+                            [llvm_v4i32_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvcvuxwdp :
+      PowerPC_VSX_Intrinsic<"xvcvuxwdp", [llvm_v2f64_ty],
+                            [llvm_v4i32_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvcvspdp :
+      PowerPC_VSX_Intrinsic<"xvcvspdp", [llvm_v2f64_ty],
+                            [llvm_v4f32_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvcvsxdsp :
+      PowerPC_VSX_Intrinsic<"xvcvsxdsp", [llvm_v4f32_ty],
+                            [llvm_v2i64_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvcvuxdsp :
+      PowerPC_VSX_Intrinsic<"xvcvuxdsp", [llvm_v4f32_ty],
+                            [llvm_v2i64_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvcvdpsp :
+      PowerPC_VSX_Intrinsic<"xvcvdpsp", [llvm_v4f32_ty],
+                            [llvm_v2f64_ty], [IntrNoMem]>;
 }
 
 //===----------------------------------------------------------------------===//
 // PowerPC QPX Intrinsics.
 //
 
 let TargetPrefix = "ppc" in {  // All PPC intrinsics start with "llvm.ppc.".
   /// PowerPC_QPX_Intrinsic - Base class for all QPX intrinsics.

lib/Target/PowerPC/PPCInstrVSX.td

def XSCVSXDDP : XX2Form<60, 376,
                       [(set f64:$XT, (PPCfcfid f64:$XB))]>;
   def XSCVUXDDP : XX2Form<60, 360,
                       (outs vsfrc:$XT), (ins vsfrc:$XB),
                       "xscvuxddp $XT, $XB", IIC_VecFP,
                       [(set f64:$XT, (PPCfcfidu f64:$XB))]>;
 
   def XVCVDPSP : XX2Form<60, 393,
                       (outs vsrc:$XT), (ins vsrc:$XB),
-                      "xvcvdpsp $XT, $XB", IIC_VecFP, []>;
+                      "xvcvdpsp $XT, $XB", IIC_VecFP,
+                      [(set v4f32:$XT, (int_ppc_vsx_xvcvdpsp v2f64:$XB))]>;
   def XVCVDPSXDS : XX2Form<60, 472,
                       (outs vsrc:$XT), (ins vsrc:$XB),
                       "xvcvdpsxds $XT, $XB", IIC_VecFP,
                       [(set v2i64:$XT, (fp_to_sint v2f64:$XB))]>;
   def XVCVDPSXWS : XX2Form<60, 216,
                       (outs vsrc:$XT), (ins vsrc:$XB),
-                      "xvcvdpsxws $XT, $XB", IIC_VecFP, []>;
+                      "xvcvdpsxws $XT, $XB", IIC_VecFP,
+                      [(set v4i32:$XT, (int_ppc_vsx_xvcvdpsxws v2f64:$XB))]>;
   def XVCVDPUXDS : XX2Form<60, 456,
                       (outs vsrc:$XT), (ins vsrc:$XB),
                       "xvcvdpuxds $XT, $XB", IIC_VecFP,
                       [(set v2i64:$XT, (fp_to_uint v2f64:$XB))]>;
   def XVCVDPUXWS : XX2Form<60, 200,
                       (outs vsrc:$XT), (ins vsrc:$XB),
-                      "xvcvdpuxws $XT, $XB", IIC_VecFP, []>;
+                      "xvcvdpuxws $XT, $XB", IIC_VecFP,
+                      [(set v4i32:$XT, (int_ppc_vsx_xvcvdpuxws v2f64:$XB))]>;
 
   def XVCVSPDP : XX2Form<60, 457,
                       (outs vsrc:$XT), (ins vsrc:$XB),
-                      "xvcvspdp $XT, $XB", IIC_VecFP, []>;
+                      "xvcvspdp $XT, $XB", IIC_VecFP,
+                      [(set v2f64:$XT, (int_ppc_vsx_xvcvspdp v4f32:$XB))]>;
   def XVCVSPSXDS : XX2Form<60, 408,
                       (outs vsrc:$XT), (ins vsrc:$XB),
                       "xvcvspsxds $XT, $XB", IIC_VecFP, []>;
   def XVCVSPSXWS : XX2Form<60, 152,
                       (outs vsrc:$XT), (ins vsrc:$XB),
                       "xvcvspsxws $XT, $XB", IIC_VecFP, []>;
   def XVCVSPUXDS : XX2Form<60, 392,
                       (outs vsrc:$XT), (ins vsrc:$XB),
                       "xvcvspuxds $XT, $XB", IIC_VecFP, []>;
   def XVCVSPUXWS : XX2Form<60, 136,
                       (outs vsrc:$XT), (ins vsrc:$XB),
                       "xvcvspuxws $XT, $XB", IIC_VecFP, []>;
   def XVCVSXDDP : XX2Form<60, 504,
                       (outs vsrc:$XT), (ins vsrc:$XB),
                       "xvcvsxddp $XT, $XB", IIC_VecFP,
                       [(set v2f64:$XT, (sint_to_fp v2i64:$XB))]>;
   def XVCVSXDSP : XX2Form<60, 440,
                       (outs vsrc:$XT), (ins vsrc:$XB),
-                      "xvcvsxdsp $XT, $XB", IIC_VecFP, []>;
+                      "xvcvsxdsp $XT, $XB", IIC_VecFP,
+                      [(set v4f32:$XT, (int_ppc_vsx_xvcvsxdsp v2i64:$XB))]>;
   def XVCVSXWDP : XX2Form<60, 248,
                       (outs vsrc:$XT), (ins vsrc:$XB),
-                      "xvcvsxwdp $XT, $XB", IIC_VecFP, []>;
+                      "xvcvsxwdp $XT, $XB", IIC_VecFP,
+                      [(set v2f64:$XT, (int_ppc_vsx_xvcvsxwdp v4i32:$XB))]>;
   def XVCVSXWSP : XX2Form<60, 184,
                       (outs vsrc:$XT), (ins vsrc:$XB),
                       "xvcvsxwsp $XT, $XB", IIC_VecFP,
                       [(set v4f32:$XT, (sint_to_fp v4i32:$XB))]>;
   def XVCVUXDDP : XX2Form<60, 488,
                       (outs vsrc:$XT), (ins vsrc:$XB),
                       "xvcvuxddp $XT, $XB", IIC_VecFP,
                       [(set v2f64:$XT, (uint_to_fp v2i64:$XB))]>;
   def XVCVUXDSP : XX2Form<60, 424,
                       (outs vsrc:$XT), (ins vsrc:$XB),
-                      "xvcvuxdsp $XT, $XB", IIC_VecFP, []>;
+                      "xvcvuxdsp $XT, $XB", IIC_VecFP,
+                      [(set v4f32:$XT, (int_ppc_vsx_xvcvuxdsp v2i64:$XB))]>;
   def XVCVUXWDP : XX2Form<60, 232,
                       (outs vsrc:$XT), (ins vsrc:$XB),
-                      "xvcvuxwdp $XT, $XB", IIC_VecFP, []>;
+                      "xvcvuxwdp $XT, $XB", IIC_VecFP,
+                      [(set v2f64:$XT, (int_ppc_vsx_xvcvuxwdp v4i32:$XB))]>;
   def XVCVUXWSP : XX2Form<60, 168,
                       (outs vsrc:$XT), (ins vsrc:$XB),
                       "xvcvuxwsp $XT, $XB", IIC_VecFP, []>;
 
   // Rounding Instructions
   def XSRDPI : XX2Form<60, 73,
                       (outs vsfrc:$XT), (ins vsfrc:$XB),
                       "xsrdpi $XT, $XB", IIC_VecFP,

test/CodeGen/PowerPC/builtins-ppc-elf2-abi.ll

entry:
   %0 = load <2 x double>, <2 x double>* %a.addr, align 16
   %1 = call <2 x double> @llvm.ppc.vsx.xvredp(<2 x double> %0)
   ret <2 x double> %1
 ; CHECK-LABEL: @emit_xvredp
 ; CHECK: xvredp {{[0-9]+}}, {{[0-9]+}}
 }
 
 ; Function Attrs: nounwind readnone
+define <4 x i32> @emit_xvcvdpsxws(<2 x double> %a) {
+entry:
+  %0 = tail call <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double> %a)
+  ret <4 x i32> %0
+; CHECK-LABEL: @emit_xvcvdpsxws
+; CHECK: xvcvdpsxws 34, 34
+}
+
+; Function Attrs: nounwind readnone
+define <4 x i32> @emit_xvcvdpuxws(<2 x double> %a) {
+entry:
+  %0 = tail call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double> %a)
+  ret <4 x i32> %0
+; CHECK-LABEL: @emit_xvcvdpuxws
+; CHECK: xvcvdpuxws 34, 34
+}
+
+; Function Attrs: nounwind readnone
+define <2 x double> @emit_xvcvsxwdp(<4 x i32> %a) {
+entry:
+  %0 = tail call <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32> %a)
+  ret <2 x double> %0
+; CHECK-LABEL: @emit_xvcvsxwdp
+; CHECK: xvcvsxwdp 34, 34
+}
+
+; Function Attrs: nounwind readnone
+define <2 x double> @emit_xvcvuxwdp(<4 x i32> %a) {
+entry:
+  %0 = tail call <2 x double> @llvm.ppc.vsx.xvcvuxwdp(<4 x i32> %a)
+  ret <2 x double> %0
+; CHECK-LABEL: @emit_xvcvuxwdp
+; CHECK: xvcvuxwdp 34, 34
+}
+
+; Function Attrs: nounwind readnone
+define <2 x double> @emit_xvcvspdp(<4 x float> %a) {
+entry:
+  %0 = tail call <2 x double> @llvm.ppc.vsx.xvcvspdp(<4 x float> %a)
+  ret <2 x double> %0
+; CHECK-LABEL: @emit_xvcvspdp
+; CHECK: xvcvspdp 34, 34
+}
+
+; Function Attrs: nounwind readnone
+define <4 x float> @emit_xvcvsxdsp(<2 x i64> %a) {
+entry:
+  %0 = tail call <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x i64> %a)
+  ret <4 x float> %0
+; CHECK-LABEL: @emit_xvcvsxdsp
+; CHECK: xvcvsxdsp 34, 34
+}
+
+; Function Attrs: nounwind readnone
+define <4 x float> @emit_xvcvuxdsp(<2 x i64> %a) {
+entry:
+  %0 = tail call <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x i64> %a)
+  ret <4 x float> %0
+; CHECK-LABEL: @emit_xvcvuxdsp
+; CHECK: xvcvuxdsp 34, 34
+}
+
+; Function Attrs: nounwind readnone
+define <4 x float> @emit_xvcvdpsp(<2 x double> %a) {
+entry:
+  %0 = tail call <4 x float> @llvm.ppc.vsx.xvcvdpsp(<2 x double> %a)
+  ret <4 x float> %0
+; CHECK-LABEL: @emit_xvcvdpsp
+; CHECK: xvcvdpsp 34, 34
+}
+
+; Function Attrs: nounwind readnone
+
+; Function Attrs: nounwind readnone
 declare <4 x float> @llvm.ppc.vsx.xvresp(<4 x float>)
 
 ; Function Attrs: nounwind readnone
 declare <2 x double> @llvm.ppc.vsx.xvredp(<2 x double>)
 
 ; Function Attrs: nounwind readnone
 declare <2 x double> @llvm.ceil.v2f64(<2 x double>)
 

 ; Function Attrs: nounwind readnone
 declare <4 x i32> @llvm.ppc.vsx.xvcmpgesp(<4 x float>, <4 x float>)
 
 ; Function Attrs: nounwind readnone
 declare <2 x i64> @llvm.ppc.vsx.xvcmpgtdp(<2 x double>, <2 x double>)
 
 ; Function Attrs: nounwind readnone
 declare <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.ppc.vsx.xvcvdpsp(<2 x double>) #1
+declare <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double>) #1
+declare <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>) #1
+declare <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32>) #1
+declare <2 x double> @llvm.ppc.vsx.xvcvuxwdp(<4 x i32>) #1
+declare <2 x double> @llvm.ppc.vsx.xvcvspdp(<4 x float>) #1
+declare <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x i64>) #1
+declare <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x i64>) #1