Implement vector shift builtins - llvm portion.

[jtony]

Summary

Implemented builtin signatures:

vector unsigned char vec_slv (vector unsigned char, vector unsigned char);
vector unsigned char vec_srv (vector unsigned char, vector unsigned char);

[nemanjai]

Other than the minor nit, this LGTM.

lib/Target/PowerPC/PPCInstrAltivec.td

1339

Please fix the spacing. The square bracket needs to line up to just inside the angled bracket (i.e. [ lines up with 1).
Also remove the spaces that make the pattern look out of place with respect to others. It should be:
[(set v16i8:$vD, (int_ppc_altivec_vslv v16i8:$vA, v16i8:$vB))]
Same below.

[jtony]

Fix the spacing and alignment problem in the previous patch.

[kbarton]

LGTM

[nemanjai]

Committed revision 285681.
Tony, please close this review pending no buildbot failures.

include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_altivec_vsubecuq : GCCBuiltin<"__builtin_altivec_vsubecuq">,
                         [llvm_v1i128_ty, llvm_v1i128_ty, llvm_v1i128_ty],
                         [IntrNoMem]>;
 }
 
 def int_ppc_altivec_vsl   : PowerPC_Vec_WWW_Intrinsic<"vsl">;
 def int_ppc_altivec_vslo  : PowerPC_Vec_WWW_Intrinsic<"vslo">;
 
 def int_ppc_altivec_vslb  : PowerPC_Vec_BBB_Intrinsic<"vslb">;
+def int_ppc_altivec_vslv  : PowerPC_Vec_BBB_Intrinsic<"vslv">;
+def int_ppc_altivec_vsrv  : PowerPC_Vec_BBB_Intrinsic<"vsrv">;
 def int_ppc_altivec_vslh  : PowerPC_Vec_HHH_Intrinsic<"vslh">;
 def int_ppc_altivec_vslw  : PowerPC_Vec_WWW_Intrinsic<"vslw">;
 
 // Right Shifts.
 def int_ppc_altivec_vsr   : PowerPC_Vec_WWW_Intrinsic<"vsr">;
 def int_ppc_altivec_vsro  : PowerPC_Vec_WWW_Intrinsic<"vsro">;
   
 def int_ppc_altivec_vsrb  : PowerPC_Vec_BBB_Intrinsic<"vsrb">;

lib/Target/PowerPC/PPCInstrAltivec.td

 
 // Vector Rotate Left Mask/Mask-Insert
 def VRLWNM : VX1_VT5_VA5_VB5<389, "vrlwnm", []>;
 def VRLWMI : VX1_VT5_VA5_VB5<133, "vrlwmi", []>;
 def VRLDNM : VX1_VT5_VA5_VB5<453, "vrldnm", []>;
 def VRLDMI : VX1_VT5_VA5_VB5<197, "vrldmi", []>;
 
 // Vector Shift Left/Right
-def VSLV : VX1_VT5_VA5_VB5<1860, "vslv", []>;
-def VSRV : VX1_VT5_VA5_VB5<1796, "vsrv", []>;
+def VSLV : VX1_VT5_VA5_VB5<1860, "vslv",
+                           [(set v16i8 : $vD, (int_ppc_altivec_vslv v16i8 : $vA, v16i8 : $vB))]>;
+def VSRV : VX1_VT5_VA5_VB5<1796, "vsrv",
+                           [(set v16i8 : $vD, (int_ppc_altivec_vsrv v16i8 : $vA, v16i8 : $vB))]>;
 
 // Vector Multiply-by-10 (& Write Carry) Unsigned Quadword
 def VMUL10UQ   : VXForm_BX<513, (outs vrrc:$vD), (ins vrrc:$vA),
                            "vmul10uq $vD, $vA", IIC_VecFP, []>;
 def VMUL10CUQ  : VXForm_BX<  1, (outs vrrc:$vD), (ins vrrc:$vA),
                            "vmul10cuq $vD, $vA", IIC_VecFP, []>;
 
 // Vector Multiply-by-10 Extended (& Write Carry) Unsigned Quadword

test/CodeGen/PowerPC/vsx-p9.ll

entry:
   ret <2 x double> %0
 ; CHECK-LABEL: testXVIEXPDP
 ; CHECK: xviexpdp 34, 34, 35
 ; CHECK: blr
 }
 ; Function Attrs: nounwind readnone
 declare <2 x double> @llvm.ppc.vsx.xviexpdp(<2 x i64>, <2 x i64>)
 
+define <16 x i8> @testVSLV(<16 x i8> %a, <16 x i8> %b) {
+entry:
+  %0 = tail call <16 x i8> @llvm.ppc.altivec.vslv(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %0
+; CHECK-LABEL: testVSLV
+; CHECK: vslv 2, 2, 3
+; CHECK: blr
+}
+; Function Attrs: nounwind readnone
+declare <16 x i8> @llvm.ppc.altivec.vslv(<16 x i8>, <16 x i8>)
+
+; Function Attrs: nounwind readnone
+define <16 x i8> @testVSRV(<16 x i8> %a, <16 x i8> %b) {
+entry:
+  %0 = tail call <16 x i8> @llvm.ppc.altivec.vsrv(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %0
+; CHECK-LABEL: testVSRV
+; CHECK: vsrv 2, 2, 3
+; CHECK: blr
+}
+; Function Attrs: nounwind readnone
+declare <16 x i8> @llvm.ppc.altivec.vsrv(<16 x i8>, <16 x i8>)
+
 declare void @sink(...)