This is an archive of the discontinued LLVM Phabricator instance.

Differential D25915

[PPC] add vector byte reverse functions to altivec.h
ClosedPublic

Authored by sfertile on Oct 24 2016, 11:20 AM.

Details

Reviewers
lei
echristo
syzaara
kbarton
amehsan
jtony
nemanjai
Summary

Add the following byte reverse functions in altivec.h

vector bool char vec_revb (vector bool char);
vector signed char vec_revb (vector signed char);
vector unsigned char vec_revb (vector unsigned char);
vector bool int vec_revb (vector bool int);
vector signed int vec_revb (vector signed int);
vector unsigned int vec_revb (vector unsigned int);
vector signed int128 vec_revb (vector signed int128);
vector unsigned int128 vec_revb (vector unsigned int128);
vector bool long long vec_revb (vector bool long long);
vector signed long long vec_revb (vector signed long long);
vector unsigned long long vec_revb (vector unsigned long long);
vector bool short vec_revb (vector bool short);
vector signed short vec_revb (vector signed short);
vector unsigned short vec_revb (vector unsigned short);
vector double vec_revb (vector double);
vector float vec_revb (vector float);

The return value is a vector where each element contains the corresponding byte-reversed vector element of the input vector.

Diff Detail

Repository
rL LLVM

Event Timeline

sfertile updated this revision to Diff 75614.Oct 24 2016, 11:20 AM
sfertile retitled this revision from to [PPC] add vector byte reverse functions to altivec.h.
sfertile updated this object.
sfertile added reviewers: nemanjai, kbarton, amehsan, jtony.
sfertile set the repository for this revision to rL LLVM.
sfertile added a subscriber: llvm-commits.
sfertile added a reviewer: lei.Oct 24 2016, 11:52 AM
sfertile added a reviewer: syzaara.Oct 24 2016, 11:56 AM
nemanjai edited edge metadata.Oct 25 2016, 6:27 AM

I think this patch looks fine but I'll let @kbarton review and provide approval.
BTW. you and @jtony have a conflict in the test case so the first to commit wins and the other one will have to make some changes on the commit.

test/CodeGen/builtins-ppc-altivec.c
9040

This is minor and can just be done on the commit, but I don't think this regex portion is needed. I'd just make these check lines:
//CHECK-LE: xor <16 x i8>

sfertile edited edge metadata.Oct 25 2016, 7:41 AM
sfertile added a subscriber: echristo.
nemanjai added inline comments.Oct 25 2016, 8:08 AM
test/CodeGen/builtins-ppc-altivec.c
9040

In general, a regex at the beginning or end of a line without saving the text is unnecessary.

kbarton accepted this revision.Oct 25 2016, 9:31 AM
kbarton edited edge metadata.

LGTM

This revision is now accepted and ready to land.Oct 25 2016, 9:31 AM
echristo accepted this revision.Oct 25 2016, 1:56 PM
echristo added a reviewer: echristo.
sfertile updated this revision to Diff 75932.Oct 26 2016, 12:50 PM
sfertile edited edge metadata.
sfertile removed rL LLVM as the repository for this revision.

removed the unneeded regexs in the tests.

Herald added a subscriber: mehdi_amini. · View Herald TranscriptOct 26 2016, 12:50 PM
nemanjai added a comment.Oct 26 2016, 11:34 PM

Committed revision 285268.
I've run the tests on a Big Endian machine as well. Sean, please close the review when you get a chance if there are no buildbot failures.

sfertile closed this revision.Oct 27 2016, 7:43 AM

Revision Contents

PathSize
lib/
Headers/
114 lines
test/
CodeGen/
93 lines
8 lines
32 lines

Diff 75614

lib/Headers/altivec.h

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 15,028 Lines • ▼ Show 20 Lines
static __inline__ vector unsigned long long __attribute__((__always_inline__)) static __inline__ vector unsigned long long __attribute__((__always_inline__))
vec_bperm(vector unsigned __int128 __a, vector unsigned char __b) { vec_bperm(vector unsigned __int128 __a, vector unsigned char __b) {
return __builtin_altivec_vbpermq((vector unsigned char)__a, return __builtin_altivec_vbpermq((vector unsigned char)__a,
(vector unsigned char)__b); (vector unsigned char)__b);
} }
#endif #endif
#endif #endif
static __inline__ vector bool char __ATTRS_o_ai
vec_revb(vector bool char __a) {
return __a;
}
static __inline__ vector signed char __ATTRS_o_ai
vec_revb(vector signed char __a) {
return __a;
}
static __inline__ vector unsigned char __ATTRS_o_ai
vec_revb(vector unsigned char __a) {
return __a;
}
static __inline__ vector bool short __ATTRS_o_ai
vec_revb(vector bool short __a) {
vector unsigned char __indices =
{ 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 };
return vec_perm(__a, __a, __indices);
}
static __inline__ vector signed short __ATTRS_o_ai
vec_revb(vector signed short __a) {
vector unsigned char __indices =
{ 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 };
return vec_perm(__a, __a, __indices);
}
static __inline__ vector unsigned short __ATTRS_o_ai
vec_revb(vector unsigned short __a) {
vector unsigned char __indices =
{ 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 };
return vec_perm(__a, __a, __indices);
}
static __inline__ vector bool int __ATTRS_o_ai
vec_revb(vector bool int __a) {
vector unsigned char __indices =
{ 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 };
return vec_perm(__a, __a, __indices);
}
static __inline__ vector signed int __ATTRS_o_ai
vec_revb(vector signed int __a) {
vector unsigned char __indices =
{ 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 };
return vec_perm(__a, __a, __indices);
}
static __inline__ vector unsigned int __ATTRS_o_ai
vec_revb(vector unsigned int __a) {
vector unsigned char __indices =
{ 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 };
return vec_perm(__a, __a, __indices);
}
static __inline__ vector float __ATTRS_o_ai
vec_revb(vector float __a) {
vector unsigned char __indices =
{ 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 };
return vec_perm(__a, __a, __indices);
}
#ifdef __VSX__
static __inline__ vector bool long long __ATTRS_o_ai
vec_revb(vector bool long long __a) {
vector unsigned char __indices =
{ 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 };
return vec_perm(__a, __a, __indices);
}
static __inline__ vector signed long long __ATTRS_o_ai
vec_revb(vector signed long long __a) {
vector unsigned char __indices =
{ 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 };
return vec_perm(__a, __a, __indices);
}
static __inline__ vector unsigned long long __ATTRS_o_ai
vec_revb(vector unsigned long long __a) {
vector unsigned char __indices =
{ 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 };
return vec_perm(__a, __a, __indices);
}
static __inline__ vector double __ATTRS_o_ai
vec_revb(vector double __a) {
vector unsigned char __indices =
{ 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 };
return vec_perm(__a, __a, __indices);
}
#endif /* End __VSX__ */
#if defined(__POWER8_VECTOR__) && defined(__powerpc64__)
static __inline__ vector signed __int128 __ATTRS_o_ai
vec_revb(vector signed __int128 __a) {
vector unsigned char __indices =
{ 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 };
return (vector signed __int128)vec_perm((vector signed int)__a,
(vector signed int)__a,
__indices);
}
static __inline__ vector unsigned __int128 __ATTRS_o_ai
vec_revb(vector unsigned __int128 __a) {
vector unsigned char __indices =
{ 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 };
return (vector unsigned __int128)vec_perm((vector signed int)__a,
(vector signed int)__a,
__indices);
}
#endif /* END __POWER8_VECTOR__ && __powerpc64__ */
#undef __ATTRS_o_ai #undef __ATTRS_o_ai
#endif /* __ALTIVEC_H */ #endif /* __ALTIVEC_H */

test/CodeGen/builtins-ppc-altivec.c

Show First 20 Lines • Show All 8,990 Lines • ▼ Show 20 Lines// CHECK-LE: @llvm.ppc.altivec.vcmpgtfp.p(i32 2
res_i = (vf1 <= vf2); res_i = (vf1 <= vf2);
// CHECK: @llvm.ppc.altivec.vcmpgefp.p(i32 2 // CHECK: @llvm.ppc.altivec.vcmpgefp.p(i32 2
// CHECK-LE: @llvm.ppc.altivec.vcmpgefp.p(i32 2 // CHECK-LE: @llvm.ppc.altivec.vcmpgefp.p(i32 2
res_i = (vf1 >= vf2); res_i = (vf1 >= vf2);
// CHECK: @llvm.ppc.altivec.vcmpgefp.p(i32 2 // CHECK: @llvm.ppc.altivec.vcmpgefp.p(i32 2
// CHECK-LE: @llvm.ppc.altivec.vcmpgefp.p(i32 2 // CHECK-LE: @llvm.ppc.altivec.vcmpgefp.p(i32 2
} }
/* ------------------------------ optional -------------------------------------- */
// CHECK-LABEL: define void @test8
// CHECK-LE-LABEL: define void @test8
void test8() {
res_vbc = vec_revb(vbc);
// CHECK: [[T1:%.+]] = load <16 x i8>, <16 x i8>* @vbc, align 16
// CHECK: store <16 x i8> [[T1]], <16 x i8>* [[T2:%.+]], align 16
// CHECK: [[T3:%.+]] = load <16 x i8>, <16 x i8>* [[T2]], align 16
// CHECK: store <16 x i8> [[T3]], <16 x i8>* @res_vbc, align 16
// CHECK-LE: [[T1:%.+]] = load <16 x i8>, <16 x i8>* @vbc, align 16
// CHECK-LE: store <16 x i8> [[T1]], <16 x i8>* [[T2:%.+]], align 16
// CHECK-LE: [[T3:%.+]] = load <16 x i8>, <16 x i8>* [[T2]], align 16
// CHECK-LE: store <16 x i8> [[T3]], <16 x i8>* @res_vbc, align 16
res_vsc = vec_revb(vsc);
// CHECK: [[T1:%.+]] = load <16 x i8>, <16 x i8>* @vsc, align 16
// CHECK: store <16 x i8> [[T1]], <16 x i8>* [[T2:%.+]], align 16
// CHECK: [[T3:%.+]] = load <16 x i8>, <16 x i8>* [[T2]], align 16
// CHECK: store <16 x i8> [[T3]], <16 x i8>* @res_vsc, align 16
// CHECK-LE: [[T1:%.+]] = load <16 x i8>, <16 x i8>* @vsc, align 16
// CHECK-LE: store <16 x i8> [[T1]], <16 x i8>* [[T2:%.+]], align 16
// CHECK-LE: [[T3:%.+]] = load <16 x i8>, <16 x i8>* [[T2]], align 16
// CHECK-LE: store <16 x i8> [[T3]], <16 x i8>* @res_vsc, align 16
res_vuc = vec_revb(vuc);
// CHECK: [[T1:%.+]] = load <16 x i8>, <16 x i8>* @vuc, align 16
// CHECK: store <16 x i8> [[T1]], <16 x i8>* [[T2:%.+]], align 16
// CHECK: [[T3:%.+]] = load <16 x i8>, <16 x i8>* [[T2]], align 16
// CHECK: store <16 x i8> [[T3]], <16 x i8>* @res_vuc, align 16
// CHECK-LE: [[T1:%.+]] = load <16 x i8>, <16 x i8>* @vuc, align 16
// CHECK-LE: store <16 x i8> [[T1]], <16 x i8>* [[T2:%.+]], align 16
// CHECK-LE: [[T3:%.+]] = load <16 x i8>, <16 x i8>* [[T2]], align 16
// CHECK-LE: store <16 x i8> [[T3]], <16 x i8>* @res_vuc, align 16
res_vbs = vec_revb(vbs);
// CHECK: store <16 x i8> <i8 1, i8 0, i8 3, i8 2, i8 5, i8 4, i8 7, i8 6, i8 9, i8 8, i8 11, i8 10, i8 13, i8 12, i8 15, i8 14>, <16 x i8>* {{%.+}}, align 16
// CHECK: {{%.+}} = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
// CHECK-LE: store <16 x i8> <i8 1, i8 0, i8 3, i8 2, i8 5, i8 4, i8 7, i8 6, i8 9, i8 8, i8 11, i8 10, i8 13, i8 12, i8 15, i8 14>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: store <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: {{%.+}} = xor <16 x i8>
nemanjaiUnsubmitted
Not Done
ReplyInline Actions

This is minor and can just be done on the commit, but I don't think this regex portion is needed. I'd just make these check lines:
//CHECK-LE: xor <16 x i8>

nemanjai: This is minor and can just be done on the commit, but I don't think this regex portion is…
nemanjaiUnsubmitted
Not Done
ReplyInline Actions

In general, a regex at the beginning or end of a line without saving the text is unnecessary.

nemanjai: In general, a regex at the beginning or end of a line without saving the text is unnecessary.
// CHECK-LE: {{%.+}} = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
res_vs = vec_revb(vs);
// CHECK: store <16 x i8> <i8 1, i8 0, i8 3, i8 2, i8 5, i8 4, i8 7, i8 6, i8 9, i8 8, i8 11, i8 10, i8 13, i8 12, i8 15, i8 14>, <16 x i8>* {{%.+}}, align 16
// CHECK: {{%.+}} = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
// CHECK-LE: store <16 x i8> <i8 1, i8 0, i8 3, i8 2, i8 5, i8 4, i8 7, i8 6, i8 9, i8 8, i8 11, i8 10, i8 13, i8 12, i8 15, i8 14>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: store <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: {{%.+}} = xor <16 x i8>
// CHECK-LE: {{%.+}} = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
res_vus = vec_revb(vus);
// CHECK: store <16 x i8> <i8 1, i8 0, i8 3, i8 2, i8 5, i8 4, i8 7, i8 6, i8 9, i8 8, i8 11, i8 10, i8 13, i8 12, i8 15, i8 14>, <16 x i8>* {{%.+}}, align 16
// CHECK: {{%.+}} = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
// CHECK-LE: store <16 x i8> <i8 1, i8 0, i8 3, i8 2, i8 5, i8 4, i8 7, i8 6, i8 9, i8 8, i8 11, i8 10, i8 13, i8 12, i8 15, i8 14>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: store <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: {{%.+}} = xor <16 x i8>
// CHECK-LE: {{%.+}} = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
res_vbi = vec_revb(vbi);
// CHECK: store <16 x i8> <i8 3, i8 2, i8 1, i8 0, i8 7, i8 6, i8 5, i8 4, i8 11, i8 10, i8 9, i8 8, i8 15, i8 14, i8 13, i8 12>, <16 x i8>* {{%.+}}, align 16
// CHECK: {{%.+}} = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
// CHECK-LE: {{%.+}} = load <4 x i32>, <4 x i32>* @vbi, align 16
// CHECK-LE: store <16 x i8> <i8 3, i8 2, i8 1, i8 0, i8 7, i8 6, i8 5, i8 4, i8 11, i8 10, i8 9, i8 8, i8 15, i8 14, i8 13, i8 12>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: store <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: {{%.+}} = xor <16 x i8>
// CHECK-LE: {{%.+}} = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
res_vi = vec_revb(vi);
// CHECK: store <16 x i8> <i8 3, i8 2, i8 1, i8 0, i8 7, i8 6, i8 5, i8 4, i8 11, i8 10, i8 9, i8 8, i8 15, i8 14, i8 13, i8 12>, <16 x i8>* {{%.+}}, align 16
// CHECK: {{%.+}} = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
// CHECK-LE: store <16 x i8> <i8 3, i8 2, i8 1, i8 0, i8 7, i8 6, i8 5, i8 4, i8 11, i8 10, i8 9, i8 8, i8 15, i8 14, i8 13, i8 12>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: store <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: {{%.+}} = xor <16 x i8>
// CHECK-LE: {{%.+}} = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
res_vui = vec_revb(vui);
// CHECK: store <16 x i8> <i8 3, i8 2, i8 1, i8 0, i8 7, i8 6, i8 5, i8 4, i8 11, i8 10, i8 9, i8 8, i8 15, i8 14, i8 13, i8 12>, <16 x i8>* {{%.+}}, align 16
// CHECK: {{%.+}} = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
// CHECK-LE: store <16 x i8> <i8 3, i8 2, i8 1, i8 0, i8 7, i8 6, i8 5, i8 4, i8 11, i8 10, i8 9, i8 8, i8 15, i8 14, i8 13, i8 12>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: store <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: {{%.+}} = xor <16 x i8>
// CHECK-LE: {{%.+}} = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
res_vf = vec_revb(vf);
// CHECK: store <16 x i8> <i8 3, i8 2, i8 1, i8 0, i8 7, i8 6, i8 5, i8 4, i8 11, i8 10, i8 9, i8 8, i8 15, i8 14, i8 13, i8 12>, <16 x i8>* {{%.+}}, align 16
// CHECK: {{%.+}} = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
// CHECK-LE: store <16 x i8> <i8 3, i8 2, i8 1, i8 0, i8 7, i8 6, i8 5, i8 4, i8 11, i8 10, i8 9, i8 8, i8 15, i8 14, i8 13, i8 12>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: store <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: {{%.+}} = xor <16 x i8>
// CHECK-LE: {{%.+}} = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
}

test/CodeGen/builtins-ppc-quadword.c

Show First 20 Lines • Show All 151 Lines • ▼ Show 20 Lines
// CHECK-LE: @llvm.ppc.altivec.vsubecuq // CHECK-LE: @llvm.ppc.altivec.vsubecuq
// CHECK-PPC: error: assigning to '__vector __int128' (vector of 1 '__int128' value) from incompatible type 'int' // CHECK-PPC: error: assigning to '__vector __int128' (vector of 1 '__int128' value) from incompatible type 'int'
res_vulll = vec_vsubecuq(vulll, vulll, vulll); res_vulll = vec_vsubecuq(vulll, vulll, vulll);
// CHECK: @llvm.ppc.altivec.vsubecuq // CHECK: @llvm.ppc.altivec.vsubecuq
// CHECK-LE: @llvm.ppc.altivec.vsubecuq // CHECK-LE: @llvm.ppc.altivec.vsubecuq
// CHECK-PPC: error: assigning to '__vector unsigned __int128' (vector of 1 'unsigned __int128' value) from incompatible type 'int' // CHECK-PPC: error: assigning to '__vector unsigned __int128' (vector of 1 'unsigned __int128' value) from incompatible type 'int'
res_vulll = vec_revb(vulll);
// CHECK: store <16 x i8> <i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, <16 x i8>* {{%.+}}, align 16
// CHECK: {{%.+}} = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
// CHECK-LE: store <16 x i8> <i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: store <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: {{%.+}} = xor <16 x i8>
// CHECK-LE: {{%.+}} = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
// CHECK_PPC: error: call to 'vec_revb' is ambiguous
} }

test/CodeGen/builtins-ppc-vsx.c

Show First 20 Lines • Show All 1,074 Lines • ▼ Show 20 Lines
// CHECK-LE: uitofp <2 x i64> %{{.*}} to <2 x double> // CHECK-LE: uitofp <2 x i64> %{{.*}} to <2 x double>
// CHECK-LE: fmul <2 x double> // CHECK-LE: fmul <2 x double>
res_vd = vec_ctf(vull, 31); res_vd = vec_ctf(vull, 31);
// CHECK: uitofp <2 x i64> %{{.*}} to <2 x double> // CHECK: uitofp <2 x i64> %{{.*}} to <2 x double>
// CHECK: fmul <2 x double> // CHECK: fmul <2 x double>
// CHECK-LE: uitofp <2 x i64> %{{.*}} to <2 x double> // CHECK-LE: uitofp <2 x i64> %{{.*}} to <2 x double>
// CHECK-LE: fmul <2 x double> // CHECK-LE: fmul <2 x double>
res_vbll = vec_revb(vbll);
// CHECK: store <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>, <16 x i8>* {{%.+}}, align 16
// CHECK: {{%.+}} = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
// CHECK-LE: store <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: store <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: {{%.+}} = xor <16 x i8>
// CHECK-LE: {{%.+}} = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
res_vsll = vec_revb(vsll);
// CHECK: store <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>, <16 x i8>* {{%.+}}, align 16
// CHECK: {{%.+}} = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
// CHECK-LE: store <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: store <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: {{%.+}} = xor <16 x i8>
// CHECK-LE: {{%.+}} = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
res_vull = vec_revb(vull);
// CHECK: store <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>, <16 x i8>* {{%.+}}, align 16
// CHECK: {{%.+}} = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
// CHECK-LE: store <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: store <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: {{%.+}} = xor <16 x i8>
// CHECK-LE: {{%.+}} = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
res_vd = vec_revb(vd);
// CHECK: store <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>, <16 x i8>* {{%.+}}, align 16
// CHECK: {{%.+}} = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
// CHECK-LE: store <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: store <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: {{%.+}} = xor <16 x i8>
// CHECK-LE: {{%.+}} = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
} }