AMDGPU : Add a function to enable and disable IEEEBit for SC and shader respectively.

[wdng]

Summary

Add a function to enable and disable IEEEBit for SC and shader respectively.

[kzhuravl]

lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

551–555 ↗

(On Diff #75199)

Can we change this to ProgInfo.IEEEMode = STM.enableIEEEBit(MF)?

[kzhuravl]

lib/Target/AMDGPU/AMDGPUSubtarget.h

252 ↗

(On Diff #75199)

I think this is a property of a function, and moving this function to SIMachineFunctionInfo would be better

[• tstellarAMD]

lib/Target/AMDGPU/AMDGPUSubtarget.h

252 ↗

(On Diff #75199)

My original thought was that it would be useful to have this function here in case we added a subtarget feature for setting/unsetting the ieee bit.

[kzhuravl]

lib/Target/AMDGPU/AMDGPUSubtarget.h

252 ↗

(On Diff #75199)

Ah, ok. That makes sense then.

[wdng]

Address issues based on feedback.

[wdng]

Add lit tests using the graphics calling conventions and check that IEEEBit is 0.

[kzhuravl]

LGTM

[wdng]

Thanks a lot, Tom and Konstantin!

llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
   ProgInfo.VGPRBlocks = alignTo(ProgInfo.NumVGPRsForWavesPerEU,
                                 RI->getVGPRAllocGranule());
   ProgInfo.VGPRBlocks = ProgInfo.VGPRBlocks / RI->getVGPRAllocGranule() - 1;
 
   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
   // register.
   ProgInfo.FloatMode = getFPMode(MF);
 
-  ProgInfo.IEEEMode = 0;
+  ProgInfo.IEEEMode = STM.enableIEEEBit(MF);
 
   // Make clamp modifier on NaN input returns 0.
   ProgInfo.DX10Clamp = 1;
 
   const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
   ProgInfo.ScratchSize = FrameInfo.getStackSize();
 
   ProgInfo.FlatUsed = FlatUsed;

llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h

public:
   bool unsafeDSOffsetFoldingEnabled() const {
     return EnableUnsafeDSOffsetFolding;
   }
 
   bool dumpCode() const {
     return DumpCode;
   }
 
+  bool enableIEEEBit(const MachineFunction &MF) const {
+    return AMDGPU::isCompute(MF.getFunction()->getCallingConv());
+  }
+
   /// Return the amount of LDS that can be used that will not restrict the
   /// occupancy lower than WaveCount.
   unsigned getMaxLocalMemSizeWithWaveCount(unsigned WaveCount) const;
 
   /// Inverse of getMaxLocalMemWithWaveCount. Return the maximum wavecount if
   /// the given LDS memory size is the only constraint.
   unsigned getOccupancyWithLocalMemSize(uint32_t Bytes) const;
 

llvm/trunk/test/CodeGen/AMDGPU/default-fp-mode.ll

 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
 
 ; GCN-LABEL: {{^}}test_default_si:
 ; GCN: FloatMode: 192
-; GCN: IeeeMode: 0
+; GCN: IeeeMode: 1
 define void @test_default_si(float addrspace(1)* %out0, double addrspace(1)* %out1) #0 {
   store float 0.0, float addrspace(1)* %out0
   store double 0.0, double addrspace(1)* %out1
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_default_vi:
 ; GCN: FloatMode: 192
-; GCN: IeeeMode: 0
+; GCN: IeeeMode: 1
 define void @test_default_vi(float addrspace(1)* %out0, double addrspace(1)* %out1) #1 {
   store float 0.0, float addrspace(1)* %out0
   store double 0.0, double addrspace(1)* %out1
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_f64_denormals:
 ; GCN: FloatMode: 192
-; GCN: IeeeMode: 0
+; GCN: IeeeMode: 1
 define void @test_f64_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #2 {
   store float 0.0, float addrspace(1)* %out0
   store double 0.0, double addrspace(1)* %out1
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_f32_denormals:
 ; GCNL: FloatMode: 48
-; GCN: IeeeMode: 0
+; GCN: IeeeMode: 1
 define void @test_f32_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #3 {
   store float 0.0, float addrspace(1)* %out0
   store double 0.0, double addrspace(1)* %out1
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_f32_f64_denormals:
 ; GCN: FloatMode: 240
-; GCN: IeeeMode: 0
+; GCN: IeeeMode: 1
 define void @test_f32_f64_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #4 {
   store float 0.0, float addrspace(1)* %out0
   store double 0.0, double addrspace(1)* %out1
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_no_denormals
 ; GCN: FloatMode: 0
-; GCN: IeeeMode: 0
+; GCN: IeeeMode: 1
 define void @test_no_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #5 {
   store float 0.0, float addrspace(1)* %out0
   store double 0.0, double addrspace(1)* %out1
   ret void
 }
 
+; GCN-LABEL: {{^}}kill_gs_const:
+; GCN: IeeeMode: 0
+define amdgpu_gs void @kill_gs_const() {
+main_body:
+  %0 = icmp ule i32 0, 3
+  %1 = select i1 %0, float 1.000000e+00, float -1.000000e+00
+  call void @llvm.AMDGPU.kill(float %1)
+  %2 = icmp ule i32 3, 0
+  %3 = select i1 %2, float 1.000000e+00, float -1.000000e+00
+  call void @llvm.AMDGPU.kill(float %3)
+  ret void
+}
+
+; GCN-LABEL: {{^}}kill_vcc_implicit_def:
+; GCN: IeeeMode: 0
+define amdgpu_ps void @kill_vcc_implicit_def([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) {
+entry:
+  %tmp0 = fcmp olt float %13, 0.0
+  call void @llvm.AMDGPU.kill(float %14)
+  %tmp1 = select i1 %tmp0, float 1.0, float 0.0
+  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 1, i32 1, float %tmp1, float %tmp1, float %tmp1, float %tmp1)
+  ret void
+}
+
+
+declare void @llvm.AMDGPU.kill(float)
+declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
+
 attributes #0 = { nounwind "target-cpu"="tahiti" }
 attributes #1 = { nounwind "target-cpu"="fiji" }
 attributes #2 = { nounwind "target-features"="+fp64-denormals" }
 attributes #3 = { nounwind "target-features"="+fp32-denormals" }
 attributes #4 = { nounwind "target-features"="+fp32-denormals,+fp64-denormals" }
 attributes #5 = { nounwind "target-features"="-fp32-denormals,-fp64-denormals" }

llvm/trunk/test/CodeGen/AMDGPU/hsa-fp-mode.ll

 ; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
 
 ; GCN-LABEL: {{^}}test_default_ci:
 ; GCN: float_mode = 192
 ; GCN: enable_dx10_clamp = 1
-; GCN: enable_ieee_mode = 0
+; GCN: enable_ieee_mode = 1
 define void @test_default_ci(float addrspace(1)* %out0, double addrspace(1)* %out1) #0 {
   store float 0.0, float addrspace(1)* %out0
   store double 0.0, double addrspace(1)* %out1
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_default_vi:
 ; GCN: float_mode = 192
 ; GCN: enable_dx10_clamp = 1
-; GCN: enable_ieee_mode = 0
+; GCN: enable_ieee_mode = 1
 define void @test_default_vi(float addrspace(1)* %out0, double addrspace(1)* %out1) #1 {
   store float 0.0, float addrspace(1)* %out0
   store double 0.0, double addrspace(1)* %out1
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_f64_denormals:
 ; GCN: float_mode = 192
 ; GCN: enable_dx10_clamp = 1
-; GCN: enable_ieee_mode = 0
+; GCN: enable_ieee_mode = 1
 define void @test_f64_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #2 {
   store float 0.0, float addrspace(1)* %out0
   store double 0.0, double addrspace(1)* %out1
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_f32_denormals:
 ; GCN: float_mode = 48
 ; GCN: enable_dx10_clamp = 1
-; GCN: enable_ieee_mode = 0
+; GCN: enable_ieee_mode = 1
 define void @test_f32_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #3 {
   store float 0.0, float addrspace(1)* %out0
   store double 0.0, double addrspace(1)* %out1
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_f32_f64_denormals:
 ; GCN: float_mode = 240
 ; GCN: enable_dx10_clamp = 1
-; GCN: enable_ieee_mode = 0
+; GCN: enable_ieee_mode = 1
 define void @test_f32_f64_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #4 {
   store float 0.0, float addrspace(1)* %out0
   store double 0.0, double addrspace(1)* %out1
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_no_denormals:
 ; GCN: float_mode = 0
 ; GCN: enable_dx10_clamp = 1
-; GCN: enable_ieee_mode = 0
+; GCN: enable_ieee_mode = 1
 define void @test_no_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #5 {
   store float 0.0, float addrspace(1)* %out0
   store double 0.0, double addrspace(1)* %out1
   ret void
 }
 
 attributes #0 = { nounwind "target-cpu"="kaveri" }
 attributes #1 = { nounwind "target-cpu"="fiji" }
 attributes #2 = { nounwind "target-features"="-fp32-denormals,+fp64-denormals" }
 attributes #3 = { nounwind "target-features"="+fp32-denormals,-fp64-denormals" }
 attributes #4 = { nounwind "target-features"="+fp32-denormals,+fp64-denormals" }
 attributes #5 = { nounwind "target-features"="-fp32-denormals,-fp64-denormals" }