[ARM] Add Cortex-R52 target to LLVM

[javed.absar]

Summary

This patch adds Cortex-R52, the new ARM real-time processor, to LLVM. Cortex-R52 implements the ARMv8-R architecture. I have submitted a corresponding patch for review to clang , for clang related changes (and tests).

[rengolin]

include/llvm/Support/ARMTargetParser.def

99

Are this all minimum requirements? Or just some common implementation?

226

is CRC guaranteed to be in every R52?

lib/Support/TargetParser.cpp

726

Merge with AK_ARMV7R case

lib/Target/ARM/ARM.td

484

Same question here about minimum support.

[rengolin]

include/llvm/Support/ARMTargetParser.def

226

Shouldn't R52 be the default CPU (false -> true), given it's the only entry for ARMv8R?

[jmolloy]

include/llvm/Support/ARMTargetParser.def

98

OK, it took me a while to get to the bottom of this list and I had to grep through a lot of pre-alpha unreleased documentation so I'll try to explain my reasoning:

• AEK_SEC - *INCORRECT* - I think this means TrustZone and ARMv8-R does not have TrustZone.
• AEK_MP - Multiprocessing extensions - Mandatory
• AEK_VIRT - Virtualization extensions - My reading is that this is mandatory although I can't find that definitively stated anywhere as yet.
• AEK_HWDIVARM | AEK_HWDIV - UDIV/SDIV in A32/T32 modes - These are transitively manadatory because of AEK_VIRT (see ARMv7AR ARMARM 4.4.4 "ARMv7 implementation requirements and options for the divide instructions")
• AEK_DSP - Required in ARMv8-A, and not explicitly mentioned otherwise.
• AEK_CRC - Required.

226

I don't think you should mention CRC here because it's no longer an optional extension, it's mandatory.

lib/Target/ARM/ARM.td

482

I agree with all of these except this. Why does ARMv8-R have this but ARMv8-A does not?

820

Because ARMv8-R mandates HWDiv and HWDivARM, I don't think these are required here.

[javed.absar]

Revised based on comments from Renato and James. Thanks to both for the review and feedback.

[jmolloy]

include/llvm/Support/ARMTargetParser.def

98

You removed AEK_DSP - I think it is still required here.

lib/Target/ARM/ARM.td

486

What about FeatureDSP?

[javed.absar]

Added back AEK_DSP/FeatureDSP. It was a mistake to remove it seems to be indeed required.

[jmolloy]

LGTM

[Eugene.Zelenko]

Committed in rL283542. Please specify "Differential revision: <URL>" as last line of commit message.

include/llvm/ADT/Triple.h

enum ArchType {
     LastArchType = renderscript64
   };
   enum SubArchType {
     NoSubArch,
 
     ARMSubArch_v8_2a,
     ARMSubArch_v8_1a,
     ARMSubArch_v8,
+    ARMSubArch_v8r,
     ARMSubArch_v8m_baseline,
     ARMSubArch_v8m_mainline,
     ARMSubArch_v7,
     ARMSubArch_v7em,
     ARMSubArch_v7m,
     ARMSubArch_v7s,
     ARMSubArch_v7k,
     ARMSubArch_v6,

include/llvm/Support/ARMBuildAttributes.h

enum CPUArch {
   v6KZ     = 7,   // e.g. ARM1176JZ_S
   v6T2     = 8,   // e.g. ARM1156T2_S
   v6K      = 9,   // e.g. ARM1176JZ_S
   v7       = 10,  // e.g. Cortex A8, Cortex M3
   v6_M     = 11,  // e.g. Cortex M1
   v6S_M    = 12,  // v6_M with the System extensions
   v7E_M    = 13,  // v7_M with DSP extensions
   v8_A     = 14,  // v8_A AArch32
+  v8_R     = 15,  // e.g. Cortex R52
   v8_M_Base= 16,  // v8_M_Base AArch32
   v8_M_Main= 17,  // v8_M_Main AArch32
 };
 
 enum CPUArchProfile {               // (=7), uleb128
   Not_Applicable          = 0,      // pre v7, or cross-profile code
   ApplicationProfile      = (0x41), // 'A' (e.g. for Cortex A8)
   RealTimeProfile         = (0x52), // 'R' (e.g. for Cortex R4)

include/llvm/Support/ARMTargetParser.def

 ARM_ARCH("armv8.1-a", AK_ARMV8_1A, "8.1-A", "v8.1a",
          ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
          (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
           ARM::AEK_HWDIV | ARM::AEK_DSP | ARM::AEK_CRC))
 ARM_ARCH("armv8.2-a", AK_ARMV8_2A, "8.2-A", "v8.2a",
          ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
          (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
           ARM::AEK_HWDIV | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS))
+ARM_ARCH("armv8-r", AK_ARMV8R, "8-R", "v8r", ARMBuildAttrs::CPUArch::v8_R,
+          FK_NEON_FP_ARMV8,
+          (ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIV |
+           ARM::AEK_CRC))
 ARM_ARCH("armv8-m.base", AK_ARMV8MBaseline, "8-M.Baseline", "v8m.base",
           ARMBuildAttrs::CPUArch::v8_M_Base, FK_NONE, ARM::AEK_HWDIV)
 ARM_ARCH("armv8-m.main", AK_ARMV8MMainline, "8-M.Mainline", "v8m.main",
           ARMBuildAttrs::CPUArch::v8_M_Main, FK_FPV5_D16, ARM::AEK_HWDIV)
 // Non-standard Arch names.
 ARM_ARCH("iwmmxt", AK_IWMMXT, "iwmmxt", "", ARMBuildAttrs::CPUArch::v5TE,
           FK_NONE, ARM::AEK_NONE)
 ARM_ARCH("iwmmxt2", AK_IWMMXT2, "iwmmxt2", "", ARMBuildAttrs::CPUArch::v5TE,
ARM_CPU_NAME("krait", AK_ARMV7A, FK_NEON_VFPV4, false,
              (ARM::AEK_HWDIVARM | ARM::AEK_HWDIV))
 ARM_CPU_NAME("cortex-r4", AK_ARMV7R, FK_NONE, true, ARM::AEK_NONE)
 ARM_CPU_NAME("cortex-r4f", AK_ARMV7R, FK_VFPV3_D16, false, ARM::AEK_NONE)
 ARM_CPU_NAME("cortex-r5", AK_ARMV7R, FK_VFPV3_D16, false,
              (ARM::AEK_MP | ARM::AEK_HWDIVARM))
 ARM_CPU_NAME("cortex-r7", AK_ARMV7R, FK_VFPV3_D16_FP16, false,
              (ARM::AEK_MP | ARM::AEK_HWDIVARM))
 ARM_CPU_NAME("cortex-r8", AK_ARMV7R, FK_VFPV3_D16_FP16, false,
              (ARM::AEK_MP | ARM::AEK_HWDIVARM))
+ARM_CPU_NAME("cortex-r52", AK_ARMV8R, FK_NEON_FP_ARMV8, true, ARM::AEK_NONE)
 ARM_CPU_NAME("sc300", AK_ARMV7M, FK_NONE, false, ARM::AEK_NONE)
 ARM_CPU_NAME("cortex-m3", AK_ARMV7M, FK_NONE, true, ARM::AEK_NONE)
 ARM_CPU_NAME("cortex-m4", AK_ARMV7EM, FK_FPV4_SP_D16, true, ARM::AEK_NONE)
 ARM_CPU_NAME("cortex-m7", AK_ARMV7EM, FK_FPV5_D16, false, ARM::AEK_NONE)
 ARM_CPU_NAME("cortex-a32", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
 ARM_CPU_NAME("cortex-a35", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
 ARM_CPU_NAME("cortex-a53", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, true, ARM::AEK_CRC)
 ARM_CPU_NAME("cortex-a57", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)

lib/Support/TargetParser.cpp

return StringSwitch<StringRef>(Arch)
       .Cases("v6z", "v6zk", "v6kz")
       .Cases("v7", "v7a", "v7hl", "v7l", "v7-a")
       .Case("v7r", "v7-r")
       .Case("v7m", "v7-m")
       .Case("v7em", "v7e-m")
       .Cases("v8", "v8a", "aarch64", "arm64", "v8-a")
       .Case("v8.1a", "v8.1-a")
       .Case("v8.2a", "v8.2-a")
+      .Case("v8r", "v8-r")
       .Case("v8m.base", "v8-m.base")
       .Case("v8m.main", "v8-m.main")
       .Default(Arch);
 }
 
 // MArch is expected to be of the form (arm|thumb)?(eb)?(v.+)?(eb)?, but
 // (iwmmxt|xscale)(eb)? is also permitted. If the former, return
 // "v.+", if the latter, return unmodified string, minus 'eb'.
unsigned llvm::ARM::parseArchProfile(StringRef Arch) {
   switch (parseArch(Arch)) {
   case ARM::AK_ARMV6M:
   case ARM::AK_ARMV7M:
   case ARM::AK_ARMV7EM:
   case ARM::AK_ARMV8MMainline:
   case ARM::AK_ARMV8MBaseline:
     return ARM::PK_M;
   case ARM::AK_ARMV7R:
+  case ARM::AK_ARMV8R:
     return ARM::PK_R;
   case ARM::AK_ARMV7A:
   case ARM::AK_ARMV7K:
   case ARM::AK_ARMV8A:
   case ARM::AK_ARMV8_1A:
   case ARM::AK_ARMV8_2A:
     return ARM::PK_A;
   }
   return ARM::PK_INVALID;
unsigned llvm::ARM::parseArchVersion(StringRef Arch) {
   case ARM::AK_ARMV7M:
   case ARM::AK_ARMV7S:
   case ARM::AK_ARMV7EM:
   case ARM::AK_ARMV7K:
     return 7;
   case ARM::AK_ARMV8A:
   case ARM::AK_ARMV8_1A:
   case ARM::AK_ARMV8_2A:
+  case ARM::AK_ARMV8R:
   case ARM::AK_ARMV8MBaseline:
   case ARM::AK_ARMV8MMainline:
     return 8;
   }
   return 0;
 }
 
 StringRef llvm::AArch64::getCanonicalArchName(StringRef Arch) {

lib/Support/Triple.cpp

static Triple::SubArchType parseSubArch(StringRef SubArchName) {
   case ARM::AK_ARMV7EM:
     return Triple::ARMSubArch_v7em;
   case ARM::AK_ARMV8A:
     return Triple::ARMSubArch_v8;
   case ARM::AK_ARMV8_1A:
     return Triple::ARMSubArch_v8_1a;
   case ARM::AK_ARMV8_2A:
     return Triple::ARMSubArch_v8_2a;
+  case ARM::AK_ARMV8R:
+    return Triple::ARMSubArch_v8r;
   case ARM::AK_ARMV8MBaseline:
     return Triple::ARMSubArch_v8m_baseline;
   case ARM::AK_ARMV8MMainline:
     return Triple::ARMSubArch_v8m_mainline;
   default:
     return Triple::NoSubArch;
   }
 }

lib/Target/ARM/ARM.td

def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
                                     "Samsung Exynos-M1 processors", []>;
 
 def ProcR4      : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
                                    "Cortex-R4 ARM processors", []>;
 def ProcR5      : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
                                    "Cortex-R5 ARM processors", []>;
 def ProcR7      : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
                                    "Cortex-R7 ARM processors", []>;
+def ProcR52     : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52",
+                                   "Cortex-R52 ARM processors", []>;
 
 def ProcM3      : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3",
                                    "Cortex-M3 ARM processors", []>;
 
 //===----------------------------------------------------------------------===//
 // ARM schedules.
 //
 
def ARMv82a   : Architecture<"armv8.2-a", "ARMv82a",  [HasV8_2aOps,
                                                        FeatureDSP,
                                                        FeatureTrustZone,
                                                        FeatureMP,
                                                        FeatureVirtualization,
                                                        FeatureCrypto,
                                                        FeatureCRC,
                                                        FeatureRAS]>;
 
+def ARMv8r    : Architecture<"armv8-r",   "ARMv8r",   [HasV8Ops,
+                                                       FeatureRClass,
+                                                       FeatureDB,
+                                                       FeatureHWDiv,
+                                                       FeatureHWDivARM,
+                                                       FeatureT2XtPk,
+                                                       FeatureCRC,
+                                                       FeatureMP,
+                                                       FeatureVirtualization,
+                                                       FeatureFPARMv8,
+                                                       FeatureNEON]>;
+
 def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
                                                       [HasV8MBaselineOps,
                                                        FeatureNoARM,
                                                        FeatureDB,
                                                        FeatureHWDiv,
                                                        FeatureV7Clrex,
                                                        Feature8MSecExt,
                                                        FeatureAcquireRelease,
def : ProcNoItin<"exynos-m1",                           [ARMv8a, ProcExynosM1,
                                                          FeatureCrypto,
                                                          FeatureCRC]>;
 
 def : ProcNoItin<"exynos-m2",                           [ARMv8a, ProcExynosM1,
                                                          FeatureHWDiv,
                                                          FeatureHWDivARM,
                                                          FeatureCrypto,
                                                          FeatureCRC]>;
 
+def : ProcNoItin<"cortex-r52",                          [ARMv8r, ProcR52]>;
+
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//
 
 include "ARMRegisterInfo.td"
 
 include "ARMCallingConv.td"
 

lib/Target/ARM/ARMAsmPrinter.cpp

 // to appear in the .ARM.attributes section in ELF.
 // Instead of subclassing the MCELFStreamer, we do the work here.
 
 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
                                             const ARMSubtarget *Subtarget) {
   if (CPU == "xscale")
     return ARMBuildAttrs::v5TEJ;
 
-  if (Subtarget->hasV8Ops())
+  if (Subtarget->hasV8Ops()) {
+    if (Subtarget->isRClass())
+      return ARMBuildAttrs::v8_R;
     return ARMBuildAttrs::v8_A;
-  else if (Subtarget->hasV8MMainlineOps())
+  } else if (Subtarget->hasV8MMainlineOps())
     return ARMBuildAttrs::v8_M_Main;
   else if (Subtarget->hasV7Ops()) {
     if (Subtarget->isMClass() && Subtarget->hasDSP())
       return ARMBuildAttrs::v7E_M;
     return ARMBuildAttrs::v7;
   } else if (Subtarget->hasV6T2Ops())
     return ARMBuildAttrs::v6T2;
   else if (Subtarget->hasV8MBaselineOps())

lib/Target/ARM/ARMSubtarget.h

 class StringRef;
 class TargetOptions;
 class ARMBaseTargetMachine;
 
 class ARMSubtarget : public ARMGenSubtargetInfo {
 protected:
   enum ARMProcFamilyEnum {
     Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15,
-    CortexA17, CortexR4, CortexR4F, CortexR5, CortexR7, CortexM3,
+    CortexA17, CortexR4, CortexR4F, CortexR5, CortexR7, CortexR52, CortexM3,
     CortexA32, CortexA35, CortexA53, CortexA57, CortexA72, CortexA73,
     Krait, Swift, ExynosM1
   };
   enum ARMProcClassEnum {
     None, AClass, RClass, MClass
   };
   enum ARMArchEnum {
     ARMv2, ARMv2a, ARMv3, ARMv3m, ARMv4, ARMv4t, ARMv5, ARMv5t, ARMv5te,
     ARMv5tej, ARMv6, ARMv6k, ARMv6kz, ARMv6t2, ARMv6m, ARMv6sm, ARMv7a, ARMv7r,
-    ARMv7m, ARMv7em, ARMv8a, ARMv81a, ARMv82a, ARMv8mMainline, ARMv8mBaseline
+    ARMv7m, ARMv7em, ARMv8a, ARMv81a, ARMv82a, ARMv8mMainline, ARMv8mBaseline,
+    ARMv8r
   };
 
 public:
   /// What kind of timing do load multiple/store multiple instructions have.
   enum ARMLdStMultipleTiming {
     /// Can load/store 2 registers/cycle.
     DoubleIssue,
     /// Can load/store 2 registers/cycle, but needs an extra cycle if the access

test/CodeGen/ARM/build-attributes.ll

 ; RUN: llc < %s -mtriple=thumb-none-linux-gnueabi -mcpu=cortex-m0 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
 ; RUN: llc < %s -mtriple=thumb-none-linux-gnueabi -mattr=+strict-align -mcpu=cortex-m0 | FileCheck %s --check-prefix=STRICT-ALIGN
 ; RUN: llc < %s -mtriple=thumbv6m-none-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
 ; RUN: llc < %s -mtriple=thumb-none-linux-gnueabi -mcpu=cortex-m0 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
 ; ARMv5
 ; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi -mcpu=arm1022e | FileCheck %s --check-prefix=NO-STRICT-ALIGN
 ; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi -mcpu=arm1022e -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
 
+; ARMv8-R
+; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-r52 -mattr=-vfp2,-fp16 | FileCheck %s --check-prefix=ARMv8R --check-prefix=ARMv8R-NOFPU
+; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-r52 -mattr=-neon,+fp-only-sp,+d16 | FileCheck %s --check-prefix=ARMv8R --check-prefix=ARMv8R-SP
+; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-r52 | FileCheck %s --check-prefix=ARMv8R --check-prefix=ARMv8R-NEON
+
 ; XSCALE:      .eabi_attribute 6, 5
 ; XSCALE:      .eabi_attribute 8, 1
 ; XSCALE:      .eabi_attribute 9, 1
 
 ; DYN-ROUNDING: .eabi_attribute 19, 1
 
 ; V6:   .eabi_attribute 6, 6
 ; V6:   .eabi_attribute 8, 1

 ; RELOC-RWPI:      .eabi_attribute 17, 1
 ; RELOC-ROPI-RWPI: .eabi_attribute 15, 2
 ; RELOC-ROPI-RWPI: .eabi_attribute 16, 1
 ; RELOC-ROPI-RWPI:  .eabi_attribute 17, 1
 
 ; PCS-R9-USE:  .eabi_attribute 14, 0
 ; PCS-R9-RESERVE:  .eabi_attribute 14, 3
 
+; ARMv8R: .eabi_attribute 67, "2.09"      @ Tag_conformance
+; ARMv8R: .eabi_attribute 6, 15   @ Tag_CPU_arch
+; ARMv8R: .eabi_attribute 7, 82   @ Tag_CPU_arch_profile
+; ARMv8R: .eabi_attribute 8, 1    @ Tag_ARM_ISA_use
+; ARMv8R: .eabi_attribute 9, 2    @ Tag_THUMB_ISA_use
+; ARMv8R-NOFPU-NOT: .fpu
+; ARMv8R-NOFPU-NOT: .eabi_attribute 12
+; ARMv8R-SP: .fpu fpv5-sp-d16
+; ARMv8R-SP-NOT: .eabi_attribute 12
+; ARMv8R-NEON: .fpu    neon-fp-armv8
+; ARMv8R-NEON: .eabi_attribute 12, 3   @ Tag_Advanced_SIMD_arch
+; ARMv8R: .eabi_attribute 17, 1   @ Tag_ABI_PCS_GOT_use
+; ARMv8R: .eabi_attribute 20, 1   @ Tag_ABI_FP_denormal
+; ARMv8R: .eabi_attribute 21, 1   @ Tag_ABI_FP_exceptions
+; ARMv8R: .eabi_attribute 23, 3   @ Tag_ABI_FP_number_model
+; ARMv8R: .eabi_attribute 34, 1   @ Tag_CPU_unaligned_access
+; ARMv8R: .eabi_attribute 24, 1   @ Tag_ABI_align_needed
+; ARMv8R: .eabi_attribute 25, 1   @ Tag_ABI_align_preserved
+; ARMv8R-NOFPU-NOT: .eabi_attribute 27
+; ARMv8R-SP: .eabi_attribute 27, 1   @ Tag_ABI_HardFP_use
+; ARMv8R-NEON-NOT: .eabi_attribute 27
+; ARMv8R-NOFPU-NOT: .eabi_attribute 36
+; ARMv8R-SP: .eabi_attribute 36, 1   @ Tag_FP_HP_extension
+; ARMv8R-NEON: .eabi_attribute 36, 1   @ Tag_FP_HP_extension
+; ARMv8R: .eabi_attribute 38, 1   @ Tag_ABI_FP_16bit_format
+; ARMv8R: .eabi_attribute 42, 1   @ Tag_MPextension_use
+; ARMv8R: .eabi_attribute 14, 0   @ Tag_ABI_PCS_R9_use
+; ARMv8R: .eabi_attribute 68, 2   @ Tag_Virtualization_use
+
 define i32 @f(i64 %z) {
     ret i32 0
 }

unittests/Support/TargetParserTest.cpp

const char *CPU[] = {
       "arm1156t2-s",   "arm1156t2f-s",  "cortex-m0",   "cortex-m0plus",
       "cortex-m1",     "sc000",         "cortex-a5",   "cortex-a7",
       "cortex-a8",     "cortex-a9",     "cortex-a12",  "cortex-a15",
       "cortex-a17",    "krait",         "cortex-r4",   "cortex-r4f",
       "cortex-r5",     "cortex-r7",     "cortex-r8",   "sc300",
       "cortex-m3",     "cortex-m4",     "cortex-m7",   "cortex-a32",
       "cortex-a35",    "cortex-a53",    "cortex-a57",  "cortex-a72",
       "cortex-a73",    "cyclone",       "exynos-m1",   "exynos-m2",   
-      "iwmmxt",        "xscale",        "swift"};
+      "iwmmxt",        "xscale",        "swift",       "cortex-r52"};
 
   for (const auto &ARMCPUName : kARMCPUNames) {
     if (contains(CPU, ARMCPUName.Name))
       EXPECT_NE(ARM::AK_INVALID, ARM::parseCPUArch(ARMCPUName.Name));
     else
       EXPECT_EQ(ARM::AK_INVALID, ARM::parseCPUArch(ARMCPUName.Name));
   }
 }
 
 TEST(TargetParserTest, ARMparseArchEndianAndISA) {
   const char *Arch[] = {
       "v2",    "v2a",    "v3",    "v3m",  "v4",   "v4t",  "v5",    "v5t",
       "v5e",   "v5te",   "v5tej", "v6",   "v6j",  "v6k",  "v6hl",  "v6t2",
       "v6kz",  "v6z",    "v6zk",  "v6-m", "v6m",  "v6sm", "v6s-m", "v7-a",
       "v7",    "v7a",    "v7hl",  "v7l",  "v7-r", "v7r",  "v7-m",  "v7m",
       "v7k",   "v7s",    "v7e-m", "v7em", "v8-a", "v8",   "v8a",   "v8.1-a",
-      "v8.1a", "v8.2-a", "v8.2a"};
+      "v8.1a", "v8.2-a", "v8.2a", "v8-r"};
 
   for (unsigned i = 0; i < array_lengthof(Arch); i++) {
     std::string arm_1 = "armeb" + (std::string)(Arch[i]);
     std::string arm_2 = "arm" + (std::string)(Arch[i]) + "eb";
     std::string arm_3 = "arm" + (std::string)(Arch[i]);
     std::string thumb_1 = "thumbeb" + (std::string)(Arch[i]);
     std::string thumb_2 = "thumb" + (std::string)(Arch[i]) + "eb";
     std::string thumb_3 = "thumb" + (std::string)(Arch[i]);