NFC: The Cost Model specialization

[avt77]

Summary

The current Cost Model implementation is very inaccurate and has to be updated, improved, re-implemented to be able to take into account the concrete CPU models and the concrete targets where this Cost Model is being used. For example, the Latency Cost Model should be differ from Code Size Cost Model, etc.
This patch is the first step to launch the developing and implementation of a new Cost Model generation.

[RKSimon]

lib/Target/X86/X86TargetTransformInfo.cpp

16

following

20

Is it worth actually including a table showing the equivalences?

Subtarget.hasSSE42() - Nehalem (or better)
Subtarget.hasSSE41() - Penryn (or better)
Subtarget.hasSSE3() - Pentium4 / Athlon64 (or better)

22

Change this part to a TODO?

[avt77]

NFC updated accordingly to Simon Pilgrim suggestions.

[RKSimon]

LGTM - does anyone else have any issue with making this explicit to help standardize cost values?

lib/Target/X86/X86TargetTransformInfo.cpp

26

AVX - Sandy Bridge / Jaguar

34

Pentium2 didn't support SSE instructions

[mkuper]

LGTM.

Regarding the TODO - if you're planning on starting work on this anytime soon, I feel it'd be a good idea to send an RFC about this to llvm-dev.
Having the cost model specialized for different targets seems like a very large change, and we probably need wider discussion of what exactly this'll look like.

[avt77]

About TODO: of course we're going to prepare RFC for public discussions before real start of work.

lib/Target/X86/X86TargetTransformInfo.cpp

 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 /// This file implements a TargetTransformInfo analysis pass specific to the
 /// X86 target machine. It uses the target's detailed information to provide
 /// more precise answers to certain TTI queries, while letting the target
 /// independent and default TTI implementations handle the rest.
 ///
 //===----------------------------------------------------------------------===//
+/// About Cost Model numbers used below it's necessary to say the following:
+/// the numbers correspond to some "generic" X86 CPU instead of usage of
+/// concrete CPU model. Usually the numbers correspond to CPU where the feature
+/// apeared at the first time. For example, if we do Subtarget.hasSSE42() in
+/// the lookups below the cost is based on Nehalem as that was the first CPU
+/// to support that feature level and thus has most likely the worst case cost.
+/// Some examples of other technologies/CPUs:
+///   SSE 3   - Pentium4 / Athlon64
+///   SSE 4.1 - Penryn
+///   SSE 4.2 - Nehalem
+///   AVX     - Sandy Bridge
+///   AVX2    - Haswell
+///   AVX-512 - Xeon Phi / Skylake
+/// And some examples of instruction target dependent costs (latency)
+///                   divss     sqrtss          rsqrtss
+///   AMD K7            11-16     19              3
+///   Piledriver        9-24      13-15           5
+///   Jaguar            14        16              2
+///   Pentium II,III    18        30              2
+///   Nehalem           7-14      7-18            3
+///   Haswell           10-13     11              5
+/// TODO: Develop and implement  the target dependent cost model and
+/// specialize cost numbers for different Cost Model Targets such as throughput,
+/// code size, latency and uop count.
+//===----------------------------------------------------------------------===//
 
 #include "X86TargetTransformInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/CodeGen/BasicTTIImpl.h"
 #include "llvm/IR/IntrinsicInst.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Target/CostTable.h"
 #include "llvm/Target/TargetLowering.h"