[AMDGPU] add s_incperflevel/s_decperflevel intrinsics

[vpykhtin]

Summary

This change adds s_incperflevel/s_decperflevel intrinsics to AMDGPU backend. These instructions along with using SQ_PERF_SEL_USER_LEVEL/SQ_PERF_SEL_ACCUM_PREV counters allows to measure average time spent in some section of kernel code.

[arsenm]

LGTM with nits

lib/Target/AMDGPU/SIInstructions.td

520 ↗

(On Diff #68542)

Previous line

527 ↗

(On Diff #68542)

Previous line

test/CodeGen/AMDGPU/llvm.amdgcn.s.decperflevel.ll

1 ↗

(On Diff #68542)

Should also have a VI run line

test/CodeGen/AMDGPU/llvm.amdgcn.s.incperflevel.ll

1 ↗

(On Diff #68542)

Ditto

llvm/trunk/include/llvm/IR/IntrinsicsAMDGPU.td

def int_amdgcn_s_memtime :
   GCCBuiltin<"__builtin_amdgcn_s_memtime">,
   Intrinsic<[llvm_i64_ty], [], []>;
 
 def int_amdgcn_s_sleep :
   GCCBuiltin<"__builtin_amdgcn_s_sleep">,
   Intrinsic<[], [llvm_i32_ty], []> {
 }
 
+def int_amdgcn_s_incperflevel :
+  GCCBuiltin<"__builtin_amdgcn_s_incperflevel">,
+  Intrinsic<[], [llvm_i32_ty], []> {
+}
+
+def int_amdgcn_s_decperflevel :
+  GCCBuiltin<"__builtin_amdgcn_s_decperflevel">,
+  Intrinsic<[], [llvm_i32_ty], []> {
+}
+
 def int_amdgcn_s_getreg :
   GCCBuiltin<"__builtin_amdgcn_s_getreg">,
   Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrReadMem]>;
 
 // __builtin_amdgcn_interp_p1 <i>, <attr_chan>, <attr>, <m0>
 def int_amdgcn_interp_p1 :
   GCCBuiltin<"__builtin_amdgcn_interp_p1">,
   Intrinsic<[llvm_float_ty],

llvm/trunk/lib/Target/AMDGPU/SIInstructions.td

let Uses = [EXEC, M0] in {
   >;
 } // End Uses = [EXEC, M0]
 
 def S_SENDMSGHALT : SOPP <0x00000011, (ins SendMsgImm:$simm16), "s_sendmsghalt $simm16">;
 def S_TRAP : SOPP <0x00000012, (ins i16imm:$simm16), "s_trap $simm16">;
 def S_ICACHE_INV : SOPP <0x00000013, (ins), "s_icache_inv"> {
   let simm16 = 0;
 }
-def S_INCPERFLEVEL : SOPP <0x00000014, (ins i16imm:$simm16), "s_incperflevel $simm16">;
-def S_DECPERFLEVEL : SOPP <0x00000015, (ins i16imm:$simm16), "s_decperflevel $simm16">;
+def S_INCPERFLEVEL : SOPP <0x00000014, (ins i32imm:$simm16), "s_incperflevel $simm16", 
+  [(int_amdgcn_s_incperflevel SIMM16bit:$simm16)]> {
+  let hasSideEffects = 1;
+  let mayLoad = 1;
+  let mayStore = 1;
+}
+def S_DECPERFLEVEL : SOPP <0x00000015, (ins i32imm:$simm16), "s_decperflevel $simm16",
+  [(int_amdgcn_s_decperflevel SIMM16bit:$simm16)]> {
+  let hasSideEffects = 1;
+  let mayLoad = 1;
+  let mayStore = 1;
+}
 def S_TTRACEDATA : SOPP <0x00000016, (ins), "s_ttracedata"> {
   let simm16 = 0;
 }
 } // End hasSideEffects
 
 //===----------------------------------------------------------------------===//
 // VOPC Instructions
 //===----------------------------------------------------------------------===//

llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.s.decperflevel.ll

+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+declare void @llvm.amdgcn.s.decperflevel(i32) #0
+
+; GCN-LABEL: {{^}}test_s_decperflevel:
+; GCN: s_decperflevel 0{{$}}
+; GCN: s_decperflevel 1{{$}}
+; GCN: s_decperflevel 2{{$}}
+; GCN: s_decperflevel 3{{$}}
+; GCN: s_decperflevel 4{{$}}
+; GCN: s_decperflevel 5{{$}}
+; GCN: s_decperflevel 6{{$}}
+; GCN: s_decperflevel 7{{$}}
+; GCN: s_decperflevel 8{{$}}
+; GCN: s_decperflevel 9{{$}}
+; GCN: s_decperflevel 10{{$}}
+; GCN: s_decperflevel 11{{$}}
+; GCN: s_decperflevel 12{{$}}
+; GCN: s_decperflevel 13{{$}}
+; GCN: s_decperflevel 14{{$}}
+; GCN: s_decperflevel 15{{$}}
+define void @test_s_decperflevel(i32 %x) #0 {
+  call void @llvm.amdgcn.s.decperflevel(i32 0)
+  call void @llvm.amdgcn.s.decperflevel(i32 1)
+  call void @llvm.amdgcn.s.decperflevel(i32 2)
+  call void @llvm.amdgcn.s.decperflevel(i32 3)
+  call void @llvm.amdgcn.s.decperflevel(i32 4)
+  call void @llvm.amdgcn.s.decperflevel(i32 5)
+  call void @llvm.amdgcn.s.decperflevel(i32 6)
+  call void @llvm.amdgcn.s.decperflevel(i32 7)
+  call void @llvm.amdgcn.s.decperflevel(i32 8)
+  call void @llvm.amdgcn.s.decperflevel(i32 9)
+  call void @llvm.amdgcn.s.decperflevel(i32 10)
+  call void @llvm.amdgcn.s.decperflevel(i32 11)
+  call void @llvm.amdgcn.s.decperflevel(i32 12)
+  call void @llvm.amdgcn.s.decperflevel(i32 13)
+  call void @llvm.amdgcn.s.decperflevel(i32 14)
+  call void @llvm.amdgcn.s.decperflevel(i32 15)
+  ret void
+}
+
+attributes #0 = { nounwind }

llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.s.incperflevel.ll

+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+declare void @llvm.amdgcn.s.incperflevel(i32) #0
+
+; GCN-LABEL: {{^}}test_s_incperflevel:
+; GCN: s_incperflevel 0{{$}}
+; GCN: s_incperflevel 1{{$}}
+; GCN: s_incperflevel 2{{$}}
+; GCN: s_incperflevel 3{{$}}
+; GCN: s_incperflevel 4{{$}}
+; GCN: s_incperflevel 5{{$}}
+; GCN: s_incperflevel 6{{$}}
+; GCN: s_incperflevel 7{{$}}
+; GCN: s_incperflevel 8{{$}}
+; GCN: s_incperflevel 9{{$}}
+; GCN: s_incperflevel 10{{$}}
+; GCN: s_incperflevel 11{{$}}
+; GCN: s_incperflevel 12{{$}}
+; GCN: s_incperflevel 13{{$}}
+; GCN: s_incperflevel 14{{$}}
+; GCN: s_incperflevel 15{{$}}
+define void @test_s_incperflevel(i32 %x) #0 {
+  call void @llvm.amdgcn.s.incperflevel(i32 0)
+  call void @llvm.amdgcn.s.incperflevel(i32 1)
+  call void @llvm.amdgcn.s.incperflevel(i32 2)
+  call void @llvm.amdgcn.s.incperflevel(i32 3)
+  call void @llvm.amdgcn.s.incperflevel(i32 4)
+  call void @llvm.amdgcn.s.incperflevel(i32 5)
+  call void @llvm.amdgcn.s.incperflevel(i32 6)
+  call void @llvm.amdgcn.s.incperflevel(i32 7)
+  call void @llvm.amdgcn.s.incperflevel(i32 8)
+  call void @llvm.amdgcn.s.incperflevel(i32 9)
+  call void @llvm.amdgcn.s.incperflevel(i32 10)
+  call void @llvm.amdgcn.s.incperflevel(i32 11)
+  call void @llvm.amdgcn.s.incperflevel(i32 12)
+  call void @llvm.amdgcn.s.incperflevel(i32 13)
+  call void @llvm.amdgcn.s.incperflevel(i32 14)
+  call void @llvm.amdgcn.s.incperflevel(i32 15)
+  ret void
+}
+
+attributes #0 = { nounwind }