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committedAug 18, 2016
[AMDGPU] add s_incperflevel/s_decperflevel intrinsics.
Differential revision: https://reviews.llvm.org/D23666 llvm-svn: 279106
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4 files changed

+108
-2
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4 files changed

+108
-2
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‎llvm/include/llvm/IR/IntrinsicsAMDGPU.td

+10
Original file line numberDiff line numberDiff line change
@@ -457,6 +457,16 @@ def int_amdgcn_s_sleep :
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Intrinsic<[], [llvm_i32_ty], []> {
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}
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def int_amdgcn_s_incperflevel :
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GCCBuiltin<"__builtin_amdgcn_s_incperflevel">,
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Intrinsic<[], [llvm_i32_ty], []> {
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}
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def int_amdgcn_s_decperflevel :
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GCCBuiltin<"__builtin_amdgcn_s_decperflevel">,
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Intrinsic<[], [llvm_i32_ty], []> {
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}
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def int_amdgcn_s_getreg :
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GCCBuiltin<"__builtin_amdgcn_s_getreg">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrReadMem]>;

‎llvm/lib/Target/AMDGPU/SIInstructions.td

+12-2
Original file line numberDiff line numberDiff line change
@@ -515,8 +515,18 @@ def S_TRAP : SOPP <0x00000012, (ins i16imm:$simm16), "s_trap $simm16">;
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def S_ICACHE_INV : SOPP <0x00000013, (ins), "s_icache_inv"> {
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let simm16 = 0;
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}
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def S_INCPERFLEVEL : SOPP <0x00000014, (ins i16imm:$simm16), "s_incperflevel $simm16">;
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def S_DECPERFLEVEL : SOPP <0x00000015, (ins i16imm:$simm16), "s_decperflevel $simm16">;
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def S_INCPERFLEVEL : SOPP <0x00000014, (ins i32imm:$simm16), "s_incperflevel $simm16",
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[(int_amdgcn_s_incperflevel SIMM16bit:$simm16)]> {
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let hasSideEffects = 1;
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let mayLoad = 1;
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let mayStore = 1;
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}
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def S_DECPERFLEVEL : SOPP <0x00000015, (ins i32imm:$simm16), "s_decperflevel $simm16",
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[(int_amdgcn_s_decperflevel SIMM16bit:$simm16)]> {
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let hasSideEffects = 1;
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let mayLoad = 1;
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let mayStore = 1;
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}
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def S_TTRACEDATA : SOPP <0x00000016, (ins), "s_ttracedata"> {
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let simm16 = 0;
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}
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@@ -0,0 +1,43 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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declare void @llvm.amdgcn.s.decperflevel(i32) #0
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; GCN-LABEL: {{^}}test_s_decperflevel:
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; GCN: s_decperflevel 0{{$}}
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; GCN: s_decperflevel 1{{$}}
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; GCN: s_decperflevel 2{{$}}
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; GCN: s_decperflevel 3{{$}}
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; GCN: s_decperflevel 4{{$}}
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; GCN: s_decperflevel 5{{$}}
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; GCN: s_decperflevel 6{{$}}
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; GCN: s_decperflevel 7{{$}}
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; GCN: s_decperflevel 8{{$}}
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; GCN: s_decperflevel 9{{$}}
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; GCN: s_decperflevel 10{{$}}
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; GCN: s_decperflevel 11{{$}}
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; GCN: s_decperflevel 12{{$}}
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; GCN: s_decperflevel 13{{$}}
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; GCN: s_decperflevel 14{{$}}
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; GCN: s_decperflevel 15{{$}}
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define void @test_s_decperflevel(i32 %x) #0 {
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call void @llvm.amdgcn.s.decperflevel(i32 0)
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call void @llvm.amdgcn.s.decperflevel(i32 1)
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call void @llvm.amdgcn.s.decperflevel(i32 2)
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call void @llvm.amdgcn.s.decperflevel(i32 3)
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call void @llvm.amdgcn.s.decperflevel(i32 4)
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call void @llvm.amdgcn.s.decperflevel(i32 5)
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call void @llvm.amdgcn.s.decperflevel(i32 6)
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call void @llvm.amdgcn.s.decperflevel(i32 7)
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call void @llvm.amdgcn.s.decperflevel(i32 8)
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call void @llvm.amdgcn.s.decperflevel(i32 9)
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call void @llvm.amdgcn.s.decperflevel(i32 10)
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call void @llvm.amdgcn.s.decperflevel(i32 11)
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call void @llvm.amdgcn.s.decperflevel(i32 12)
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call void @llvm.amdgcn.s.decperflevel(i32 13)
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call void @llvm.amdgcn.s.decperflevel(i32 14)
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call void @llvm.amdgcn.s.decperflevel(i32 15)
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ret void
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}
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attributes #0 = { nounwind }
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@@ -0,0 +1,43 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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declare void @llvm.amdgcn.s.incperflevel(i32) #0
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; GCN-LABEL: {{^}}test_s_incperflevel:
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; GCN: s_incperflevel 0{{$}}
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; GCN: s_incperflevel 1{{$}}
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; GCN: s_incperflevel 2{{$}}
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; GCN: s_incperflevel 3{{$}}
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; GCN: s_incperflevel 4{{$}}
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; GCN: s_incperflevel 5{{$}}
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; GCN: s_incperflevel 6{{$}}
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; GCN: s_incperflevel 7{{$}}
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; GCN: s_incperflevel 8{{$}}
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; GCN: s_incperflevel 9{{$}}
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; GCN: s_incperflevel 10{{$}}
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; GCN: s_incperflevel 11{{$}}
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; GCN: s_incperflevel 12{{$}}
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; GCN: s_incperflevel 13{{$}}
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; GCN: s_incperflevel 14{{$}}
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; GCN: s_incperflevel 15{{$}}
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define void @test_s_incperflevel(i32 %x) #0 {
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call void @llvm.amdgcn.s.incperflevel(i32 0)
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call void @llvm.amdgcn.s.incperflevel(i32 1)
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call void @llvm.amdgcn.s.incperflevel(i32 2)
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call void @llvm.amdgcn.s.incperflevel(i32 3)
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call void @llvm.amdgcn.s.incperflevel(i32 4)
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call void @llvm.amdgcn.s.incperflevel(i32 5)
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call void @llvm.amdgcn.s.incperflevel(i32 6)
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call void @llvm.amdgcn.s.incperflevel(i32 7)
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call void @llvm.amdgcn.s.incperflevel(i32 8)
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call void @llvm.amdgcn.s.incperflevel(i32 9)
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call void @llvm.amdgcn.s.incperflevel(i32 10)
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call void @llvm.amdgcn.s.incperflevel(i32 11)
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call void @llvm.amdgcn.s.incperflevel(i32 12)
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call void @llvm.amdgcn.s.incperflevel(i32 13)
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call void @llvm.amdgcn.s.incperflevel(i32 14)
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call void @llvm.amdgcn.s.incperflevel(i32 15)
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ret void
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}
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attributes #0 = { nounwind }

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