[mips] N64 static relocation model support

[sdardis]

Summary

This patch makes one change to GOT handling and two changes to N64's
relocation model handling. Furthermore, the jumptable encodings have
been corrected for static N64.

Big GOT handling is now done via a new SDNode MipsGotHi - this node is
unconditionally lowered to an lui instruction.

The first change to N64's relocation handling is the lifting of the
restriction that N64 always uses PIC. Now it possible to target static
environments.

The second change adds support for 64 bit symbols and enables them by
default. Previously N64 had patterns for sym32 mode only. In this mode all
symbols are assumed to have 32 bit addresses. sym32 mode support
is selectable with attribute 'sym32'. A follow on patch for clang will
add the necessary frontend parameter.

[sdardis]

It appears clang already defaults to abicalls mode for mips / mips64. I'll correct the summary.

[seanbruno]

Hmmm ... FreeBSD builds for MIPS64 do *not* like this very much.

I've posted the error files here:
https://people.freebsd.org/~sbruno/base64_5570de.tgz

Assertion failed: (isImm() && "Wrong MachineOperand accessor"), function getImm, file /home/sbruno/clang/llvm/include/llvm/CodeGen/MachineOperand.h, line 420.
clang-3.9: error: unable to execute command: Abort trap (core dumped)
clang-3.9: error: clang frontend command failed due to signal (use -v to see invocation)
clang version 4.0.0 (trunk 279404)
Target: mips64-unknown-freebsd12.0
Thread model: posix
InstalledDir: /home/sbruno/clang/build/bin
clang-3.9: note: diagnostic msg: PLEASE submit a bug report to http://llvm.org/bugs/ and include the crash backtrace, preprocessed source, and associated run script.
clang-3.9: note: diagnostic msg:

---

PLEASE ATTACH THE FOLLOWING FILES TO THE BUG REPORT:
Preprocessed source(s) and associated run script(s) are located at:
clang-3.9: note: diagnostic msg: /tmp/base64-5570de.c
clang-3.9: note: diagnostic msg: /tmp/base64-5570de.sh
clang-3.9: note: diagnostic msg:

[sdardis]

Thanks for the report. I suspected that there may still be some assumptions of N64 => position independent. I'll try to get back to this patch but I'm a bit swamped at the moment.

[sdardis]

Looking at this, it's MipsSEDAGToDAGISel::replaceUsesWithZeroReg making an unguarded assumption that an instruction such as daddiu $X, $zero always has an immediate for its third operand (natural counting). The test case supplied has a global address instead of an immediate, triggering the failure.

[sdardis]

Harden replaceUsesWithZeroReg to avoid assumptions.

[sdardis]

Note, that new version doesn't generate the same relocations as Gcc. I'm currently tracking that issue down.

[sdardis]

Mark objects that use -mno-abicalls as non-pic.

[seanbruno]

Not sure if you want to change this at all. This is the first time I've been able to get a FreeBSD MALTA64 kernel to boot in QEMU. :-)

% qemu-system-mips64 -m 512M -M malta -kernel /var/tmp/mips.mips64/home/sbruno/mips64-clang/sys/MALTA64/kernel -hda ./mips64_clang.img -nographic
WARNING: Image format was not specified for './mips64_clang.img' and probing guessed raw.
         Automatically detecting the format is dangerous for raw images, write operations on block 0 will be restricted.
         Specify the 'raw' format explicitly to remove the restrictions.
entry: platform_start()
cmd line: /var/tmp/mips.mips64/home/sbruno/mips64-clang/sys/MALTA64/kernel  
envp:
        memsize = 268435456
        ememsize = 536870912
        modetty0 = 38400n8r
memsize = 268435456 (0x10000000)
ememsize = 536870912
Cache info:
  icache is virtual
  picache_stride    = 8192
  picache_loopcount = 4
  pdcache_stride    = 4096
  pdcache_loopcount = 8
cpu0: MIPS Technologies processor v160.130
  MMU: Standard TLB, 48 entries (4K 16K 64K 256K 1M 16M 64M 256M pg sizes)
  L1 i-cache: 4 ways of 256 sets, 32 bytes per line
  L1 d-cache: 4 ways of 256 sets, 32 bytes per line
  L2 cache: disabled
  Config1=0xdea3519b<PerfCount,WatchRegs,EJTAG,FPU>
  Config2=0x80000000
Physical memory chunk(s):
0x71e000 - 0xfffffff, 260972544 bytes (63714 pages)
0x90000000 - 0x9fffffff, 268435456 bytes (65536 pages)
Maxmem is 0xa0000000
KDB: debugger backends: ddb
KDB: current backend: ddb
Copyright (c) 1992-2016 The FreeBSD Project.
Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994
        The Regents of the University of California. All rights reserved.
FreeBSD is a registered trademark of The FreeBSD Foundation.
FreeBSD 12.0-CURRENT #5 r304849:304856: Fri Aug 26 20:21:52 UTC 2016
    [e-mail]:/var/tmp/mips.mips64/home/sbruno/mips64-clang/sys/MALTA64 mips
clang version 4.0.0 (trunk 279820)
Preloaded elf kernel "kernel" at 0xffffffff80711d70.
real memory  = 536870912 (524288K bytes)
Physical memory chunk(s):
0x0083b000 - 0x0fffffff, 259805184 bytes (63429 pages)
0x90000000 - 0x9f2e0fff, 254676992 bytes (62177 pages)
avail memory = 511922176 (488MB)
Trap cause = 4 (address error (load or I-fetch) - kernel mode)
[ thread pid 0 tid 100000 ]
Stopped at      vm_object_allocate+0x68:        ld      at,-3088(at)
db> bt
Tracing pid 0 tid 100000 td 0xffffffff80719fd0
db_trace_thread+80 (?,?,?,?) ra ffffffff80162af0 sp 9800000000737130 sz 416
ffffffff80162968+188 (?,?,?,?) ra ffffffff80162488 sp 98000000007372d0 sz 64
ffffffff80162100+388 (?,?,?,?) ra ffffffff801620c4 sp 9800000000737310 sz 224
db_command_loop+dc (?,?,?,?) ra ffffffff80167804 sp 98000000007373f0 sz 48
ffffffff80167648+1bc (?,?,?,?) ra ffffffff803713ec sp 9800000000737420 sz 816
kdb_trap+1cc (?,?,?,?) ra ffffffff8059635c sp 9800000000737750 sz 80
ffffffff8059621c+140 (?,?,?,?) ra 0 sp 98000000007377a0 sz 0
pid 0
db>

[seanbruno]

Are you folks ready for this to land? It sure is a huge improvement from my perspective.

[seanbruno]

I seem to get one reject from this patch:

./test/CodeGen/Mips/fcopysign-f32-f64.ll.rej

@@ -38,8 +38,8 @@
 
 ; 64-DAG: mfc1    $[[MFC:[0-9]+]], $f13
 ; 64-DAG: srl     $[[SRL:[0-9]+]], $[[MFC:[0-9]+]], 31
-; 64:     dsll    $[[DSLL:[0-9]+]], $[[SRL]], 63
 ; 64-DAG: daddiu  $[[R1:[0-9]+]], $zero, 1
+; 64:     dsll    $[[DSLL:[0-9]+]], $[[SRL]], 63
 ; 64-DAG: dsll    $[[R2:[0-9]+]], $[[R1]], 63
 ; 64-DAG: daddiu  $[[R3:[0-9]+]], $[[R2]], -1
 ; 64-DAG: dmfc1   $[[R0:[0-9]+]], ${{.*}}

[seanbruno]

The code that is changing seems to apply fine, but three of the test files now fail to apply cleanly:

./test/CodeGen/Mips/fcopysign-f32-f64.ll.rej
./test/CodeGen/Mips/llvm-ir/call.ll.rej
./test/CodeGen/Mips/tailcall/tailcall.ll.rej

[sdardis]

Ping and rebase. Dropped the changes to the ELF header flags. Those will be handled in a separate patch.

[seanbruno]

I get one reject with this review that I'm unsure how to resolve at the moment

% cat ./lib/Target/Mips/MipsISelLowering.cpp.rej
@@ -1699,7 +1702,7 @@
       MachinePointerInfo::getJumpTable(DAG.getMachineFunction()), MemVT);
   Chain = Addr.getValue(1);

-  if (isPositionIndependent() || ABI.IsN64()) {
+  if (isPositionIndependent()) {
     // For PIC, the sequence is:
     // BRIND(load(Jumptable + index) + RelocBase)
     // RelocBase can be JumpTable, GOT or some sort of global base.

[sdardis]

That reject can be handled by removing the || ABI.IsN64() I believe. I'll take a look in a bit.

[joerg]

LowerBR_JT no longer exists. The relevant codegen is always position-independent now, but using generic logic.

[sdardis]

Rebase and ping.

[joerg]

lib/Target/Mips/MipsISelLowering.cpp

3708

Please leave this alone. The trade-off is intentional and should stay. If anything, it should be further refined to default to EK_GPRel32BlockAddress, but it should certainly not use absolute labels.

[sdardis]

Update jump table encodings, add comment about size.

[zoran.jovanovic]

LGTM with a few nits.

lib/Target/Mips/Mips64InstrInfo.td

515

Nit: Is this definition necessary?
If it is needed for micromips pre-r6 than it can be moved to MicroMipsInstrInfo.td.

lib/Target/Mips/MipsAsmPrinter.cpp

707

Is this condition also affected by the change?

test/CodeGen/Mips/blockaddr.ll

38

Nit: Tab between mnemonic and operands description should be replaced with spaces.

[sdardis]

Updated to reflect reviewer's comments. Also removed assumption that N64 uses relative jump tables exclusively.

[sdardis]

@seanbruno Want to give this a try?

lib/Target/Mips/Mips64InstrInfo.td

515

It's not. It's covered by the multiclass below.

lib/Target/Mips/MipsAsmPrinter.cpp

707

Good catch. It requires !isPositionIndependant() && STI.hasSym32(), as pic0 only applies when symbols are 32 bit according to GCC.

[sdardis]

I need to refine the logic a bit further after some testing due to interactions with the CPIC ABI extension and the -mabicalls option.

[seanbruno]

I shouldn't see errors like this right? I didn't see any change before/after this patch to resolve this:

numa_setaffinity.pico: In function `err':
(.text+0x18): relocation truncated to fit: R_MIPS_PC16 against `__cerror'
numa_getaffinity.pico: In function `err':
(.text+0x18): relocation truncated to fit: R_MIPS_PC16 against `__cerror'
procctl.pico: In function `err':
(.text+0x18): relocation truncated to fit: R_MIPS_PC16 against `__cerror'
aio_mlock.pico: In function `err':
(.text+0x18): relocation truncated to fit: R_MIPS_PC16 against `__cerror'
chflagsat.pico: In function `err':
(.text+0x18): relocation truncated to fit: R_MIPS_PC16 against `__cerror'
connectat.pico: In function `err':
(.text+0x18): relocation truncated to fit: R_MIPS_PC16 against `__cerror'

[sdardis]

Are you seeing the warning message "warning: linking PIC files with non-PIC files" as well? I have a WIP clang patch that is probably required.

[seanbruno]

In D23652#650270, @sdardis wrote:

Are you seeing the warning message "warning: linking PIC files with non-PIC files" as well? I have a WIP clang patch that is probably required.

No. It looks like I need a temporary hack for now. There are plans on doing something different in the near future.

https://github.com/freebsd/freebsd/commit/e865e40a09cffd0b5a00952bef6457115d581f3c

[sdardis]

That quick hack is a bit broad, but thanks for pointing that out, as I've found that current macro isn't shared across OSes, and there's another macro __mips_abicalls which LLVM should define but doesn't.

[seanbruno]

In D23652#650270, @sdardis wrote:

Are you seeing the warning message "warning: linking PIC files with non-PIC files" as well? I have a WIP clang patch that is probably required.

Ah, I finally did hit this, do you want me to test something or other?

--- adjkerntz.full ---
/home/sbruno/clang/build/bin/clang -Wno-typedef-redefinition -Wno-pointer-sign -Wno-expansion-to-defined -Wno-address-of-packed-member -target mips64-unknown-freebsd12.0 --sysroot=/var/tmp/sbru
no/mips.mips64/home/sbruno/mips64-clang/tmp -B/var/tmp/sbruno/mips.mips64/home/sbruno/mips64-clang/tmp/usr/bin -O -pipe -G0 -EB -msoft-float -g -std=gnu99 -Wsystem-headers -Wall -Wno-format-y2k
 -W -Wno-unused-parameter -Wstrict-prototypes -Wmissing-prototypes -Wpointer-arith -Wreturn-type -Wcast-qual -Wwrite-strings -Wswitch -Wshadow -Wunused-parameter -Wcast-align -Wchar-subscripts
-Winline -Wnested-externs -Wredundant-decls -Wold-style-definition -Wno-pointer-sign -Wmissing-variable-declarations -Wthread-safety -Wno-empty-body -Wno-string-plus-int -Wno-unused-const-varia
ble -Qunused-arguments  -EB -o adjkerntz.full adjkerntz.o
/var/tmp/sbruno/mips.mips64/home/sbruno/mips64-clang/tmp/usr/bin/ld: /var/tmp/sbruno/mips.mips64/home/sbruno/mips64-clang/tmp/usr/lib/libgcc_s.so: warning: linking PIC files with non-PIC files
/var/tmp/sbruno/mips.mips64/home/sbruno/mips64-clang/tmp/usr/lib/crt1.o: In function `__start':
/home/sbruno/mips64-clang/lib/csu/mips/crt1.c:(.text+0x10c): relocation truncated to fit: R_MIPS_26 against `atexit@@FBSD_1.0'
/home/sbruno/mips64-clang/lib/csu/mips/crt1.c:(.text+0x11c): relocation truncated to fit: R_MIPS_26 against `_init_tls@@FBSD_1.0'
/home/sbruno/mips64-clang/lib/csu/mips/crt1.c:(.text+0x158): relocation truncated to fit: R_MIPS_26 against `atexit@@FBSD_1.0'
/home/sbruno/mips64-clang/lib/csu/mips/crt1.c:(.text+0x2cc): relocation truncated to fit: R_MIPS_26 against `exit@@FBSD_1.0'
adjkerntz.o: In function `main':
/home/sbruno/mips64-clang/sbin/adjkerntz/adjkerntz.c:94: relocation truncated to fit: R_MIPS_26 against `getopt@@FBSD_1.0'
/home/sbruno/mips64-clang/sbin/adjkerntz/adjkerntz.c:94: relocation truncated to fit: R_MIPS_26 against `getopt@@FBSD_1.0'
/home/sbruno/mips64-clang/sbin/adjkerntz/adjkerntz.c:94: relocation truncated to fit: R_MIPS_26 against `getopt@@FBSD_1.0'
/home/sbruno/mips64-clang/sbin/adjkerntz/adjkerntz.c:115: relocation truncated to fit: R_MIPS_26 against `access@@FBSD_1.0'
/home/sbruno/mips64-clang/sbin/adjkerntz/adjkerntz.c:121: relocation truncated to fit: R_MIPS_26 against `sigemptyset@@FBSD_1.0'
/home/sbruno/mips64-clang/sbin/adjkerntz/adjkerntz.c:122: relocation truncated to fit: R_MIPS_26 against `sigemptyset@@FBSD_1.0'
/home/sbruno/mips64-clang/sbin/adjkerntz/adjkerntz.c:123: additional relocation overflows omitted from the output
clang-4.0: error: linker command failed with exit code 1 (use -v to see invocation)
*** [adjkerntz.full] Error code 1

[sdardis]

Not right now regarding additional testing. This patch requires some more changes. I'll repost this patch once I've produced a testsuite clean run. The clang patch for handling will follow shortly afterwards, along with a patch for defining the appropriate macros for -mabicalls.

I believe once all three are posted we'd be in a better position to take stock of the situation.

test/CodeGen/Mips/tailcall/tailcall.ll

318

Note to self: this should be PIC64:

[sdardis]

Cleaned up a broken test, and fixed the flags in the elf header when doing CPIC/PIC or static.

When the N64 abi is used with the static relocation model and symbols are 64 bit, we always enable the 'noabicalls' feature. This matches GCC's output.

[seanbruno]

Retested and it looks good over here in FreeBSD land.

lib/Target/Mips/MicroMips64r6InstrInfo.td

 defm : MaterializeImms<i64, ZERO_64, DADDIU_MM64R6, LUi64, ORi64>;
 
 //===----------------------------------------------------------------------===//
 //
 // Arbitrary patterns that map to one or more instructions
 //
 //===----------------------------------------------------------------------===//
 
-def : MipsPat<(MipsLo tglobaladdr:$in),
-              (DADDIU_MM64R6 ZERO_64, tglobaladdr:$in)>, ISA_MICROMIPS64R6;
-def : MipsPat<(MipsLo tblockaddress:$in),
-              (DADDIU_MM64R6 ZERO_64, tblockaddress:$in)>, ISA_MICROMIPS64R6;
-def : MipsPat<(MipsLo tjumptable:$in),
-              (DADDIU_MM64R6 ZERO_64, tjumptable:$in)>, ISA_MICROMIPS64R6;
-def : MipsPat<(MipsLo tconstpool:$in),
-              (DADDIU_MM64R6 ZERO_64, tconstpool:$in)>, ISA_MICROMIPS64R6;
-def : MipsPat<(MipsLo tglobaltlsaddr:$in),
-              (DADDIU_MM64R6 ZERO_64, tglobaltlsaddr:$in)>, ISA_MICROMIPS64R6;
-def : MipsPat<(MipsLo texternalsym:$in),
-              (DADDIU_MM64R6 ZERO_64, texternalsym:$in)>, ISA_MICROMIPS64R6;
-
-def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)),
-              (DADDIU_MM64R6 GPR64:$hi, tglobaladdr:$lo)>, ISA_MICROMIPS64R6;
-def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)),
-              (DADDIU_MM64R6 GPR64:$hi, tblockaddress:$lo)>, ISA_MICROMIPS64R6;
-def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)),
-              (DADDIU_MM64R6 GPR64:$hi, tjumptable:$lo)>, ISA_MICROMIPS64R6;
-def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)),
-              (DADDIU_MM64R6 GPR64:$hi, tconstpool:$lo)>, ISA_MICROMIPS64R6;
-def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)),
-              (DADDIU_MM64R6 GPR64:$hi, tglobaltlsaddr:$lo)>, ISA_MICROMIPS64R6;
+defm : MipsHiLoRelocs<LUi64, DADDIU_MM64R6, ZERO_64, GPR64Opnd>, SYM_32,
+                      ISA_MICROMIPS64R6;
+
+defm : MipsHighestHigherHiLoRelocs<LUi64, DADDIU_MM64R6>, SYM_64,
+                                   ISA_MICROMIPS64R6;
 
 def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),
               (DADDU_MM64R6 GPR64:$lhs, GPR64:$rhs)>, ISA_MICROMIPS64R6;
 def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm),
               (DADDIU_MM64R6 GPR64:$lhs, imm:$imm)>, ISA_MICROMIPS64R6;
 
 
 def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))),

lib/Target/Mips/Mips.td

 def FeatureMips64r5    : SubtargetFeature<"mips64r5", "MipsArchVersion",
                                 "Mips64r5", "Mips64r5 ISA Support",
                                 [FeatureMips64r3, FeatureMips32r5]>;
 def FeatureMips64r6    : SubtargetFeature<"mips64r6", "MipsArchVersion",
                                 "Mips64r6",
                                 "Mips64r6 ISA Support [experimental]",
                                 [FeatureMips32r6, FeatureMips64r5,
                                  FeatureNaN2008]>;
+def FeatureSym32       : SubtargetFeature<"sym32", "HasSym32", "true",
+                                          "Symbols are 32 bit on Mips64">;
 
 def FeatureMips16  : SubtargetFeature<"mips16", "InMips16Mode", "true",
                                       "Mips16 mode">;
 
 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
 def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
                                     "Mips DSP-R2 ASE", [FeatureDSP]>;
 def FeatureDSPR3

lib/Target/Mips/Mips64InstrInfo.td

def : MipsPat<(i64 immZExt32:$imm),
                      (LO16 imm:$imm))>;
 
 // extended loads
 def : MipsPat<(i64 (extloadi1  addr:$src)), (LB64 addr:$src)>;
 def : MipsPat<(i64 (extloadi8  addr:$src)), (LB64 addr:$src)>;
 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
 
+def : MipsPat<(MipsJmpLink (i64 texternalsym:$dst)),
+              (JAL texternalsym:$dst)>;
+
 // hi/lo relocs
-def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
-def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
-def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
-def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
-def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
-def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
-
-let AdditionalPredicates = [NotInMicroMips] in {
-  def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
-  def : MipsPat<(MipsLo tblockaddress:$in),
-                (DADDiu ZERO_64, tblockaddress:$in)>;
-  def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
-  def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
-  def : MipsPat<(MipsLo tglobaltlsaddr:$in),
-                (DADDiu ZERO_64, tglobaltlsaddr:$in)>;
-  def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
-
-  def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)),
-                (DADDiu GPR64:$hi, tglobaladdr:$lo)>;
-  def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)),
-                (DADDiu GPR64:$hi, tblockaddress:$lo)>;
-  def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)),
-                (DADDiu GPR64:$hi, tjumptable:$lo)>;
-  def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)),
-                (DADDiu GPR64:$hi, tconstpool:$lo)>;
-  def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)),
-                (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>;
+let AdditionalPredicates = [NotInMicroMips] in
+defm : MipsHiLoRelocs<LUi64, DADDiu, ZERO_64, GPR64Opnd>, SYM_32;
+
+def : MipsPat<(MipsGotHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
+def : MipsPat<(MipsGotHi texternalsym:$in), (LUi64 texternalsym:$in)>;
+
+multiclass MipsHighestHigherHiLoRelocs<Instruction Lui, Instruction Daddiu> {
+  def : MipsPat<(MipsJmpLink (i64 texternalsym:$dst)),
+                (JAL texternalsym:$dst)>;
+  def : MipsPat<(MipsHighest (i64 tglobaladdr:$in)),
+                (Lui tglobaladdr:$in)>;
+  def : MipsPat<(MipsHighest (i64 tblockaddress:$in)),
+                (Lui tblockaddress:$in)>;
+  def : MipsPat<(MipsHighest (i64 tjumptable:$in)),
+                (Lui tjumptable:$in)>;
+  def : MipsPat<(MipsHighest (i64 tconstpool:$in)),
+                (Lui tconstpool:$in)>;
+  def : MipsPat<(MipsHighest (i64 tglobaltlsaddr:$in)),
+                (Lui tglobaltlsaddr:$in)>;
+  def : MipsPat<(MipsHighest (i64 texternalsym:$in)),
+                (Lui texternalsym:$in)>;
+
+  def : MipsPat<(MipsHigher (i64 tglobaladdr:$in)),
+                (Daddiu ZERO_64, tglobaladdr:$in)>;
+  def : MipsPat<(MipsHigher (i64 tblockaddress:$in)),
+                (Daddiu ZERO_64, tblockaddress:$in)>;
+  def : MipsPat<(MipsHigher (i64 tjumptable:$in)),
+                (Daddiu ZERO_64, tjumptable:$in)>;
+  def : MipsPat<(MipsHigher (i64 tconstpool:$in)),
+                (Daddiu ZERO_64, tconstpool:$in)>;
+  def : MipsPat<(MipsHigher (i64 tglobaltlsaddr:$in)),
+                (Daddiu ZERO_64, tglobaltlsaddr:$in)>;
+  def : MipsPat<(MipsHigher (i64 texternalsym:$in)),
+                (Daddiu ZERO_64, texternalsym:$in)>;
+
+  def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tglobaladdr:$lo))),
+                (Daddiu GPR64:$hi, tglobaladdr:$lo)>;
+  def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tblockaddress:$lo))),
+                (Daddiu GPR64:$hi, tblockaddress:$lo)>;
+  def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tjumptable:$lo))),
+                (Daddiu GPR64:$hi, tjumptable:$lo)>;
+  def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tconstpool:$lo))),
+                (Daddiu GPR64:$hi, tconstpool:$lo)>;
+  def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tglobaltlsaddr:$lo))),
+                (Daddiu GPR64:$hi, tglobaltlsaddr:$lo)>;
+
+  def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tglobaladdr:$lo))),
+                (Daddiu GPR64:$hi, tglobaladdr:$lo)>;
+  def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tblockaddress:$lo))),
+                (Daddiu GPR64:$hi, tblockaddress:$lo)>;
+  def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tjumptable:$lo))),
+                (Daddiu GPR64:$hi, tjumptable:$lo)>;
+  def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tconstpool:$lo))),
+                (Daddiu GPR64:$hi, tconstpool:$lo)>;
+  def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tglobaltlsaddr:$lo))),
+                (Daddiu GPR64:$hi, tglobaltlsaddr:$lo)>;
+
+  def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaladdr:$lo))),
+                (Daddiu GPR64:$hi, tglobaladdr:$lo)>;
+  def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tblockaddress:$lo))),
+                (Daddiu GPR64:$hi, tblockaddress:$lo)>;
+  def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tjumptable:$lo))),
+                (Daddiu GPR64:$hi, tjumptable:$lo)>;
+  def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tconstpool:$lo))),
+                (Daddiu GPR64:$hi, tconstpool:$lo)>;
+  def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaltlsaddr:$lo))),
+                (Daddiu GPR64:$hi, tglobaltlsaddr:$lo)>;
+
+}
+
+// highest/higher/hi/lo relocs
+let AdditionalPredicates = [NotInMicroMips] in
+defm : MipsHighestHigherHiLoRelocs<LUi64, DADDiu>, SYM_64;
 
-  def : WrapperPat<tglobaladdr, DADDiu, GPR64>;
-  def : WrapperPat<tconstpool, DADDiu, GPR64>;
-  def : WrapperPat<texternalsym, DADDiu, GPR64>;
-  def : WrapperPat<tblockaddress, DADDiu, GPR64>;
-  def : WrapperPat<tjumptable, DADDiu, GPR64>;
-  def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>;
-}
+
 
 defm : BrcondPats<GPR64, BEQ64, BEQ, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
                   ZERO_64>;
 def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
               (BLEZ64 i64:$lhs, bb:$dst)>;
 def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
               (BGEZ64 i64:$lhs, bb:$dst)>;
 

lib/Target/Mips/MipsAsmPrinter.cpp

if (MO.getTargetFlags())
     closeP = true;
 
   switch(MO.getTargetFlags()) {
   case MipsII::MO_GPREL:    O << "%gp_rel("; break;
   case MipsII::MO_GOT_CALL: O << "%call16("; break;
   case MipsII::MO_GOT:      O << "%got(";    break;
   case MipsII::MO_ABS_HI:   O << "%hi(";     break;
   case MipsII::MO_ABS_LO:   O << "%lo(";     break;
+  case MipsII::MO_HIGHER:   O << "%higher("; break;
+  case MipsII::MO_HIGHEST:  O << "%highest(("; break;
   case MipsII::MO_TLSGD:    O << "%tlsgd(";  break;
   case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
   case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
   case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
   case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
   case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
   case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
   case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
   bool IsABICalls = STI.isABICalls();
   const MipsABIInfo &ABI = MTM.getABI();
   if (IsABICalls) {
     TS.emitDirectiveAbiCalls();
     // FIXME: This condition should be a lot more complicated that it is here.
     //        Ideally it should test for properties of the ABI and not the ABI
     //        itself.
     //        For the moment, I'm only correcting enough to make MIPS-IV work.
     if (!isPositionIndependent() && !ABI.IsN64())
       TS.emitDirectiveOptionPic0();
   }
 
   // Tell the assembler which ABI we are using
   std::string SectionName = std::string(".mdebug.") + getCurrentABIString();
   OutStreamer->SwitchSection(
       OutContext.getELFSection(SectionName, ELF::SHT_PROGBITS, 0));
 

lib/Target/Mips/MipsISelLowering.h

enum NodeType : unsigned {
       FIRST_NUMBER = ISD::BUILTIN_OP_END,
 
       // Jump and link (call)
       JmpLink,
 
       // Tail call
       TailCall,
 
-      // Get the Higher 16 bits from a 32-bit immediate
+      // Get the Highest (63-48) 16 bits from a 64-bit immediate
+      Highest,
+
+      // Get the Higher (47-32) 16 bits from a 64-bit immediate
+      Higher,
+
+      // Get the High 16 bits from a 32/64-bit immediate
       // No relation with Mips Hi register
       Hi,
 
-      // Get the Lower 16 bits from a 32-bit immediate
+      // Get the Lower 16 bits from a 32/64-bit immediate
       // No relation with Mips Lo register
       Lo,
 
+      // Get the High 16 bits from a 32 bit immediate for accessing the GOT.
+      GotHi,
+
       // Handle gp_rel (small data/bss sections) relocation.
       GPRel,
 
       // Thread Pointer
       ThreadPointer,
 
       // Floating Point Branch Conditional
       FPBrcond,
protected:
     // computing a global symbol's address in large-GOT mode:
     //
     // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
     template <class NodeTy>
     SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty,
                                   SelectionDAG &DAG, unsigned HiFlag,
                                   unsigned LoFlag, SDValue Chain,
                                   const MachinePointerInfo &PtrInfo) const {
-      SDValue Hi =
-          DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(N, Ty, DAG, HiFlag));
+      SDValue Hi = DAG.getNode(MipsISD::GotHi, DL, Ty,
+                               getTargetNode(N, Ty, DAG, HiFlag));
       Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
       SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
                                     getTargetNode(N, Ty, DAG, LoFlag));
       return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo);
     }
 
     // This method creates the following nodes, which are necessary for
     // computing a symbol's address in non-PIC mode:
     //
     // (add %hi(sym), %lo(sym))
+    //
+    // This method covers O32, N32 and N64 in sym32 mode.
     template <class NodeTy>
     SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty,
                           SelectionDAG &DAG) const {
       SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
       SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
       return DAG.getNode(ISD::ADD, DL, Ty,
                          DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
                          DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
-    }
 
-    // This method creates the following nodes, which are necessary for
+   // computing a symbol's address in non-PIC mode for N64.
+   //
+   // (add (shl (add (shl (add %highest(sym), %higher(sim)), 16), %high(sym)),
+   //            16), %lo(%sym))
+   //
+   // FIXME: This method is not efficent for (microMIPS)MIPS64R6.
+   template <class NodeTy>
+   SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty,
+                          SelectionDAG &DAG) const {
+      SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
+      SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
+
+      SDValue Highest =
+          DAG.getNode(MipsISD::Highest, DL, Ty,
+                      getTargetNode(N, Ty, DAG, MipsII::MO_HIGHEST));
+      SDValue Higher = getTargetNode(N, Ty, DAG, MipsII::MO_HIGHER);
+      SDValue HigherPart =
+          DAG.getNode(ISD::ADD, DL, Ty, Highest,
+                      DAG.getNode(MipsISD::Higher, DL, Ty, Higher));
+      SDValue Cst = DAG.getConstant(16, DL, MVT::i32);
+      SDValue Shift = DAG.getNode(ISD::SHL, DL, Ty, HigherPart, Cst);
+      SDValue Add = DAG.getNode(ISD::ADD, DL, Ty, Shift,
+                                DAG.getNode(MipsISD::Hi, DL, Ty, Hi));
+      SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst);
+
+      return DAG.getNode(ISD::ADD, DL, Ty, Shift2,
+                         DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
+   }
+
+    // This method creates the following nodes, which are necessary for
     // computing a symbol's address using gp-relative addressing:
     //
     // (add $gp, %gp_rel(sym))
     template <class NodeTy>
     SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty,
                          SelectionDAG &DAG) const {
       assert(Ty == MVT::i32);
       SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);

lib/Target/Mips/MipsISelLowering.cpp

return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
                                    N->getOffset(), Flag);
 }
 
 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch ((MipsISD::NodeType)Opcode) {
   case MipsISD::FIRST_NUMBER:      break;
   case MipsISD::JmpLink:           return "MipsISD::JmpLink";
   case MipsISD::TailCall:          return "MipsISD::TailCall";
+  case MipsISD::Highest:           return "MipsISD::Highest";
+  case MipsISD::Higher:            return "MipsISD::Higher";
   case MipsISD::Hi:                return "MipsISD::Hi";
   case MipsISD::Lo:                return "MipsISD::Lo";
+  case MipsISD::GotHi:             return "MipsISD::GotHi";
   case MipsISD::GPRel:             return "MipsISD::GPRel";
   case MipsISD::ThreadPointer:     return "MipsISD::ThreadPointer";
   case MipsISD::Ret:               return "MipsISD::Ret";
   case MipsISD::ERet:              return "MipsISD::ERet";
   case MipsISD::EH_RETURN:         return "MipsISD::EH_RETURN";
   case MipsISD::FPBrcond:          return "MipsISD::FPBrcond";
   case MipsISD::FPCmp:             return "MipsISD::FPCmp";
   case MipsISD::CMovFP_T:          return "MipsISD::CMovFP_T";
SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
   SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
 
   EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
   Addr = DAG.getExtLoad(
       ISD::SEXTLOAD, DL, PTy, Chain, Addr,
       MachinePointerInfo::getJumpTable(DAG.getMachineFunction()), MemVT);
   Chain = Addr.getValue(1);
 
-  if (isPositionIndependent() || ABI.IsN64()) {
+  if (isPositionIndependent()) {
     // For PIC, the sequence is:
     // BRIND(load(Jumptable + index) + RelocBase)
     // RelocBase can be JumpTable, GOT or some sort of global base.
     Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr,
                        getPICJumpTableRelocBase(Table, DAG));
   }
 
   return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr);

 }
 
 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
                                                SelectionDAG &DAG) const {
   EVT Ty = Op.getValueType();
   GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
   const GlobalValue *GV = N->getGlobal();
 
-  if (!isPositionIndependent() && !ABI.IsN64()) {
+  if (!isPositionIndependent()) {
     const MipsTargetObjectFile *TLOF =
         static_cast<const MipsTargetObjectFile *>(
             getTargetMachine().getObjFileLowering());
     if (TLOF->IsGlobalInSmallSection(GV, getTargetMachine()))
       // %gp_rel relocation
       return getAddrGPRel(N, SDLoc(N), Ty, DAG);
 
-    // %hi/%lo relocation
-    return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
+    return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
+                                : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
   }
 
   // Every other architecture would use shouldAssumeDSOLocal in here, but
   // mips is special.
   // * In PIC code mips requires got loads even for local statics!
   // * To save on got entries, for local statics the got entry contains the
   //   page and an additional add instruction takes care of the low bits.
   // * It is legal to access a hidden symbol with a non hidden undefined,
return getAddrGlobal(
       DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction()));
 }
 
 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
                                               SelectionDAG &DAG) const {
   BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
   EVT Ty = Op.getValueType();
 
-  if (!isPositionIndependent() && !ABI.IsN64())
-    return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
+  if (!isPositionIndependent())
+    return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
+                                : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
 
   return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
 }
 
 SDValue MipsTargetLowering::
 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
 {
   // If the relocation model is PIC, use the General Dynamic TLS Model or

 }
 
 SDValue MipsTargetLowering::
 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
 {
   JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
   EVT Ty = Op.getValueType();
 
-  if (!isPositionIndependent() && !ABI.IsN64())
-    return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
+  if (!isPositionIndependent())
+    return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
+                                : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
 
   return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
 }
 
 SDValue MipsTargetLowering::
 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
 {
   ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
   EVT Ty = Op.getValueType();
 
-  if (!isPositionIndependent() && !ABI.IsN64()) {
+  if (!isPositionIndependent()) {
     const MipsTargetObjectFile *TLOF =
         static_cast<const MipsTargetObjectFile *>(
             getTargetMachine().getObjFileLowering());
 
     if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(),
                                        getTargetMachine()))
       // %gp_rel relocation
       return getAddrGPRel(N, SDLoc(N), Ty, DAG);
 
-    return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
+    return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
+                                : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
   }
 
-  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
 }
 
 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
   MachineFunction &MF = DAG.getMachineFunction();
   MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
 
   SDLoc DL(Op);
   SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
   // Transform all store nodes into one single node because all store
   // nodes are independent of each other.
   if (!MemOpChains.empty())
     Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
 
   // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
   // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
   // node so that legalize doesn't hack it.
-  bool IsPICCall = (ABI.IsN64() || IsPIC); // true if calls are translated to
-                                           // jalr $25
+
   bool GlobalOrExternal = false, InternalLinkage = false, IsCallReloc = false;
   SDValue CalleeLo;
   EVT Ty = Callee.getValueType();
 
   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
-    if (IsPICCall) {
+    if (IsPIC) {
       const GlobalValue *Val = G->getGlobal();
       InternalLinkage = Val->hasInternalLinkage();
 
       if (InternalLinkage)
         Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64());
       else if (LargeGOT) {
         Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16,
                                        MipsII::MO_CALL_LO16, Chain,
                                        FuncInfo->callPtrInfo(Val));
         IsCallReloc = true;
       } else {
         Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
                                FuncInfo->callPtrInfo(Val));
         IsCallReloc = true;
       }
     } else
       Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL,
                                           getPointerTy(DAG.getDataLayout()), 0,
                                           MipsII::MO_NO_FLAG);
     GlobalOrExternal = true;
   }
   else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
     const char *Sym = S->getSymbol();
 
-    if (!ABI.IsN64() && !IsPIC) // !N64 && static
+    if (!IsPIC) // static
       Callee = DAG.getTargetExternalSymbol(
           Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG);
     else if (LargeGOT) {
       Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16,
                                      MipsII::MO_CALL_LO16, Chain,
                                      FuncInfo->callPtrInfo(Sym));
       IsCallReloc = true;
-    } else { // N64 || PIC
+    } else { // PIC
       Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
                              FuncInfo->callPtrInfo(Sym));
       IsCallReloc = true;
     }
 
     GlobalOrExternal = true;
   }
 
   SmallVector<SDValue, 8> Ops(1, Chain);
   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
 
-  getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage,
+  getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage,
               IsCallReloc, CLI, Callee, Chain);
 
   if (IsTailCall)
     return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
 
   Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
   SDValue InFlag = Chain.getValue(1);
 
bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
   if (VT != MVT::f32 && VT != MVT::f64)
     return false;
   if (Imm.isNegZero())
     return false;
   return Imm.isZero();
 }
 
 unsigned MipsTargetLowering::getJumpTableEncoding() const {
-  if (ABI.IsN64())
+  if (ABI.IsN64() && isPositionIndependent())
     return MachineJumpTableInfo::EK_GPRel64BlockAddress;
 
   return TargetLowering::getJumpTableEncoding();
 }
 
 bool MipsTargetLowering::useSoftFloat() const {
   return Subtarget.useSoftFloat();
 }

lib/Target/Mips/MipsInstrInfo.td

 
 // Tail call
 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
                           [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
 
 // Hi and Lo nodes are used to handle global addresses. Used on
 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
 // static model. (nothing to do with Mips Registers Hi and Lo)
+
+// Hi is the odd node out, on MIPS64 it can expand to either daddiu when
+// using static relocations eith 64 bit symbols, or lui when using 32 bit
+// symbols.
+def MipsHigher : SDNode<"MipsISD::Higher", SDTIntUnaryOp>;
+def MipsHighest : SDNode<"MipsISD::Highest", SDTIntUnaryOp>;
 def MipsHi    : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
 def MipsLo    : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
+
 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
 
+// Hi node for accessing the GOT.
+def MipsGotHi : SDNode<"MipsISD::GotHi", SDTIntUnaryOp>;
+
 // TlsGd node is used to handle General Dynamic TLS
 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
 
 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
 def MipsTprelHi    : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
 def MipsTprelLo    : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
 
 // Thread pointer

 def HasMicroMips32r6 : Predicate<"Subtarget->inMicroMips32r6Mode()">,
                        AssemblerPredicate<"FeatureMicroMips,FeatureMips32r6">;
 def HasMicroMips64r6 : Predicate<"Subtarget->inMicroMips64r6Mode()">,
                        AssemblerPredicate<"FeatureMicroMips,FeatureMips64r6">;
 def InMips16Mode :    Predicate<"Subtarget->inMips16Mode()">,
                       AssemblerPredicate<"FeatureMips16">;
 def HasCnMips    :    Predicate<"Subtarget->hasCnMips()">,
                       AssemblerPredicate<"FeatureCnMips">;
+def IsSym32     :     Predicate<"Subtarget->HasSym32()">,
+                      AssemblerPredicate<"FeatureSym32">;
+def IsSym64     :     Predicate<"!Subtarget->HasSym32()">,
+                      AssemblerPredicate<"!FeatureSym32">;
 def RelocNotPIC :     Predicate<"!TM.isPositionIndependent()">;
 def RelocPIC    :     Predicate<"TM.isPositionIndependent()">;
 def NoNaNsFPMath :    Predicate<"TM.Options.NoNaNsFPMath">;
 def HasStdEnc :       Predicate<"Subtarget->hasStandardEncoding()">,
                       AssemblerPredicate<"!FeatureMips16">;
 def NotDSP :          Predicate<"!Subtarget->hasDSP()">;
 def InMicroMips    :  Predicate<"Subtarget->inMicroMipsMode()">,
                       AssemblerPredicate<"FeatureMicroMips">;

 
 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
 
 class PTR_32 { list<Predicate> PTRPredicates = [IsPTR32bit]; }
 class PTR_64 { list<Predicate> PTRPredicates = [IsPTR64bit]; }
 
 //===----------------------------------------------------------------------===//
+// Mips Symbol size adjectives.
+// They are mutally exculsive.
+//===----------------------------------------------------------------------===//
+
+class SYM_32 { list<Predicate> SYMPredicates = [IsSym32]; }
+class SYM_64 { list<Predicate> SYMPredicates = [IsSym64]; }
+
+//===----------------------------------------------------------------------===//
 // Mips ISA/ASE membership and instruction group membership adjectives.
 // They are mutually exclusive.
 //===----------------------------------------------------------------------===//
 
 // FIXME: I'd prefer to use additive predicates to build the instruction sets
 //        but we are short on assembler feature bits at the moment. Using a
 //        subtractive predicate will hopefully keep us under the 32 predicate
 //        limit long enough to develop an alternative way to handle P1||P2

 //              (JALR GPR32:$dst)>;
 
 // Tail call
 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
               (TAILCALL tglobaladdr:$dst)>;
 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
               (TAILCALL texternalsym:$dst)>;
 // hi/lo relocs
-def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
-def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
-def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
-def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
-def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
-def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
-
-def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
-def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
-def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
-def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
-def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
-def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
-
-def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
-              (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
-def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
-              (ADDiu GPR32:$hi, tblockaddress:$lo)>;
-def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
-              (ADDiu GPR32:$hi, tjumptable:$lo)>;
-def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
-              (ADDiu GPR32:$hi, tconstpool:$lo)>;
-def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
-              (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
+multiclass MipsHiLoRelocs<Instruction Lui, Instruction Addiu,
+                          Register ZeroReg, RegisterOperand GPROpnd> {
+  def : MipsPat<(MipsHi tglobaladdr:$in), (Lui tglobaladdr:$in)>;
+  def : MipsPat<(MipsHi tblockaddress:$in), (Lui tblockaddress:$in)>;
+  def : MipsPat<(MipsHi tjumptable:$in), (Lui tjumptable:$in)>;
+  def : MipsPat<(MipsHi tconstpool:$in), (Lui tconstpool:$in)>;
+  def : MipsPat<(MipsHi tglobaltlsaddr:$in), (Lui tglobaltlsaddr:$in)>;
+  def : MipsPat<(MipsHi texternalsym:$in), (Lui texternalsym:$in)>;
+
+  def : MipsPat<(MipsLo tglobaladdr:$in), (Addiu ZeroReg, tglobaladdr:$in)>;
+  def : MipsPat<(MipsLo tblockaddress:$in),
+                (Addiu ZeroReg, tblockaddress:$in)>;
+  def : MipsPat<(MipsLo tjumptable:$in), (Addiu ZeroReg, tjumptable:$in)>;
+  def : MipsPat<(MipsLo tconstpool:$in), (Addiu ZeroReg, tconstpool:$in)>;
+  def : MipsPat<(MipsLo tglobaltlsaddr:$in),
+                (Addiu ZeroReg, tglobaltlsaddr:$in)>;
+  def : MipsPat<(MipsLo texternalsym:$in), (Addiu ZeroReg, texternalsym:$in)>;
+
+  def : MipsPat<(add GPROpnd:$hi, (MipsLo tglobaladdr:$lo)),
+              (Addiu GPROpnd:$hi, tglobaladdr:$lo)>;
+  def : MipsPat<(add GPROpnd:$hi, (MipsLo tblockaddress:$lo)),
+              (Addiu GPROpnd:$hi, tblockaddress:$lo)>;
+  def : MipsPat<(add GPROpnd:$hi, (MipsLo tjumptable:$lo)),
+              (Addiu GPROpnd:$hi, tjumptable:$lo)>;
+  def : MipsPat<(add GPROpnd:$hi, (MipsLo tconstpool:$lo)),
+              (Addiu GPROpnd:$hi, tconstpool:$lo)>;
+  def : MipsPat<(add GPROpnd:$hi, (MipsLo tglobaltlsaddr:$lo)),
+              (Addiu GPROpnd:$hi, tglobaltlsaddr:$lo)>;
+}
+
+defm : MipsHiLoRelocs<LUi, ADDiu, ZERO, GPR32Opnd>;
+
+def : MipsPat<(MipsGotHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
+def : MipsPat<(MipsGotHi texternalsym:$in), (LUi texternalsym:$in)>;
 
 // gp_rel relocs
 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
               (ADDiu GPR32:$gp, tglobaladdr:$in)>;
 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
               (ADDiu GPR32:$gp, tconstpool:$in)>;
 
 // wrapper_pic

lib/Target/Mips/MipsSEISelDAGToDAG.cpp

 
 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
                                                 const MachineInstr& MI) {
   unsigned DstReg = 0, ZeroReg = 0;
 
   // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
   if ((MI.getOpcode() == Mips::ADDiu) &&
       (MI.getOperand(1).getReg() == Mips::ZERO) &&
+      (MI.getOperand(2).isImm()) &&
       (MI.getOperand(2).getImm() == 0)) {
     DstReg = MI.getOperand(0).getReg();
     ZeroReg = Mips::ZERO;
   } else if ((MI.getOpcode() == Mips::DADDiu) &&
              (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
+             (MI.getOperand(2).isImm()) &&
              (MI.getOperand(2).getImm() == 0)) {
     DstReg = MI.getOperand(0).getReg();
     ZeroReg = Mips::ZERO_64;
   }
 
   if (!DstReg)
     return false;
 

lib/Target/Mips/MipsSubtarget.h

class MipsSubtarget : public MipsGenSubtargetInfo {
   bool Os16;
 
   // HasMSA -- supports MSA ASE.
   bool HasMSA;
 
   // UseTCCInDIV -- Enables the use of trapping in the assembler.
   bool UseTCCInDIV;
 
+  // Sym32 -- On Mips64 symbols are 32 bits.
+  bool HasSym32;
+
   // HasEVA -- supports EVA ASE.
   bool HasEVA;
 
   InstrItineraryData InstrItins;
 
   // We can override the determination of whether we are in mips16 mode
   // as from the command line
   enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
public:
   bool useOddSPReg() const { return UseOddSPReg; }
   bool noOddSPReg() const { return !UseOddSPReg; }
   bool isNaN2008() const { return IsNaN2008bit; }
   bool isGP64bit() const { return IsGP64bit; }
   bool isGP32bit() const { return !IsGP64bit; }
   unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
   bool isPTR64bit() const { return IsPTR64bit; }
   bool isPTR32bit() const { return !IsPTR64bit; }
+  bool hasSym32() const {
+    return (HasSym32 && isABI_N64()) || isABI_N32() || isABI_O32();
+  }
   bool isSingleFloat() const { return IsSingleFloat; }
   bool hasVFPU() const { return HasVFPU; }
   bool inMips16Mode() const { return InMips16Mode; }
   bool inMips16ModeDefault() const {
     return InMips16Mode;
   }
   // Hard float for mips16 means essentially to compile as soft float
   // but to use a runtime library for soft float that is written with

test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll

 ; STATIC-O32: lui  $[[R0:[0-9]+]], %hi($CPI0_0)
 ; STATIC-O32: lwc1 $f0, %lo($CPI0_0)($[[R0]])
 ; PIC-N32: lw  $[[R0:[0-9]+]], %got_page(.LCPI0_0)
 ; PIC-N32: lwc1 $f0, %got_ofst(.LCPI0_0)($[[R0]])
 ; STATIC-N32: lui  $[[R0:[0-9]+]], %hi(.LCPI0_0)
 ; STATIC-N32: lwc1 $f0, %lo(.LCPI0_0)($[[R0]])
 ; PIC-N64: ld  $[[R0:[0-9]+]], %got_page(.LCPI0_0)
 ; PIC-N64: lwc1 $f0, %got_ofst(.LCPI0_0)($[[R0]])
-; STATIC-N64: ld  $[[R0:[0-9]+]], %got_page(.LCPI0_0)
-; STATIC-N64: lwc1 $f0, %got_ofst(.LCPI0_0)($[[R0]])
+; STATIC-N64: lui  $[[R0:[0-9]+]], %highest(.LCPI0_0)
+; STATIC-N64: lwc1 $f0, %lo(.LCPI0_0)($[[R0]])
   ret float 0x400B333340000000
 }

test/CodeGen/Mips/2010-07-20-Switch.ll

 ; RUN: llc < %s -march=mips -relocation-model=static | \
 ; RUN: FileCheck %s -check-prefix=STATIC-O32 
 ; RUN: llc < %s -march=mips -relocation-model=pic | \
 ; RUN: FileCheck %s -check-prefix=PIC-O32 
 ; RUN: llc < %s -march=mips64 -relocation-model=pic -mcpu=mips4 | \
-; RUN:     FileCheck %s -check-prefix=N64
+; RUN:     FileCheck %s -check-prefix=PIC-N64
 ; RUN: llc < %s -march=mips64 -relocation-model=static -mcpu=mips4 | \
-; RUN:     FileCheck %s -check-prefix=N64
+; RUN:     FileCheck %s -check-prefix=STATIC-N64
 ; RUN: llc < %s -march=mips64 -relocation-model=pic -mcpu=mips64 | \
-; RUN:     FileCheck %s -check-prefix=N64
+; RUN:     FileCheck %s -check-prefix=PIC-N64
 ; RUN: llc < %s -march=mips64 -relocation-model=static -mcpu=mips64 | \
-; RUN:     FileCheck %s -check-prefix=N64
+; RUN:     FileCheck %s -check-prefix=STATIC-N64
 
 define i32 @main() nounwind readnone {
 entry:
   %x = alloca i32, align 4                        ; <i32*> [#uses=2]
   store volatile i32 2, i32* %x, align 4
   %0 = load volatile i32, i32* %x, align 4             ; <i32> [#uses=1]
 ; STATIC-O32: sll $[[R0:[0-9]+]], ${{[0-9]+}}, 2
 ; STATIC-O32: lui $[[R1:[0-9]+]], %hi($JTI0_0)
 ; STATIC-O32: addu $[[R2:[0-9]+]], $[[R0]], $[[R1]]
 ; STATIC-O32: lw $[[R3:[0-9]+]], %lo($JTI0_0)($[[R2]])
+
 ; PIC-O32: sll $[[R0:[0-9]+]], ${{[0-9]+}}, 2
 ; PIC-O32: lw $[[R1:[0-9]+]], %got($JTI0_0)
 ; PIC-O32: addu $[[R2:[0-9]+]], $[[R0]], $[[R1]]
 ; PIC-O32: lw $[[R4:[0-9]+]], %lo($JTI0_0)($[[R2]])
 ; PIC-O32: addu $[[R5:[0-9]+]], $[[R4:[0-9]+]]
 ; PIC-O32: jr  $[[R5]]
-; N64: dsll $[[R0:[0-9]+]], ${{[0-9]+}}, 3
-; N64: ld $[[R1:[0-9]+]], %got_page(.LJTI0_0)
-; N64: daddu $[[R2:[0-9]+]], $[[R0:[0-9]+]], $[[R1]]
-; N64: ld $[[R4:[0-9]+]], %got_ofst(.LJTI0_0)($[[R2]])
-; N64: daddu $[[R5:[0-9]+]], $[[R4:[0-9]+]]
-; N64: jr  $[[R5]]
+
+; STATIC-N64: mflo $[[R0:[0-9]]]
+; STATIC-N64: lui $[[R1:[0-9]]], %highest(.LJTI0_0)
+; STATIC-N64: daddiu $[[R2:[0-9]]], $[[R1]], %higher(.LJTI0_0)
+; STATIC-N64: dsll $[[R3:[0-9]]], $[[R2]], 16
+; STATIC-N64: daddiu $[[R4:[0-9]]], $[[R3]], %hi(.LJTI0_0)
+; STATIC-N64: dsll $[[R5:[0-9]]], $[[R4]], 16
+; STATIC-N64: daddu $[[R6:[0-9]]], $[[R0]], $[[R4]]
+; STATIC-N64: ld ${{[0-9]+}}, %lo(.LJTI0_0)($[[R6]])
+
+; PIC-N64: dsll $[[R0:[0-9]+]], ${{[0-9]+}}, 32
+; PIC-N64: ld $[[R1:[0-9]+]], %got_page(.LJTI0_0)
+; PIC-N64: daddu $[[R2:[0-9]+]], $[[R0:[0-9]+]], $[[R1]]
+; PIC-N64: ld $[[R4:[0-9]+]], %got_ofst(.LJTI0_0)($[[R2]])
+; PIC-N64: daddu $[[R5:[0-9]+]], $[[R4:[0-9]+]]
+; PIC-N64: jr  $[[R5]]
   switch i32 %0, label %bb4 [
     i32 0, label %bb5
     i32 1, label %bb1
     i32 2, label %bb2
     i32 3, label %bb3
   ]
 
 bb1:                                              ; preds = %entry

 ; STATIC-O32: .4byte
 ; STATIC-O32: .4byte
 ; STATIC-O32: .4byte
 ; STATIC-O32: .4byte
 ; PIC-O32: .p2align  2
 ; PIC-O32: $JTI0_0:
 ; PIC-O32: .gpword
 ; PIC-O32: .gpword
-; PIC-O32: .gpword 
-; PIC-O32: .gpword 
-; N64: .p2align  3
-; N64: .LJTI0_0:
-; N64: .gpdword
-; N64: .gpdword
-; N64: .gpdword 
-; N64: .gpdword 
+; PIC-O32: .gpword
+; PIC-O32: .gpword
+; STATIC-N64: .p2align  3
+; STATIC-N64: LJTI0_0:
+; STATIC-N64: .8byte
+; STATIC-N64: .8byte
+; STATIC-N64: .8byte
+; STATIC-N64: .8byte
+;; PIC-N64: .p2align  3
+; PIC-N64: .LJTI0_0:
+; PIC-N64: .gpdword
+; PIC-N64: .gpdword
+; PIC-N64: .gpdword
+; PIC-N64: .gpdword
 

test/CodeGen/Mips/blockaddr.ll

 ; STATIC-N32: lui  $[[R2:[0-9]+]], %hi(.Ltmp[[T2:[0-9]+]])
 ; STATIC-N32: addiu ${{[0-9]+}}, $[[R2]], %lo(.Ltmp[[T2]])
 ; STATIC-N32: lui   $[[R3:[0-9]+]], %hi(.Ltmp[[T3:[0-9]+]])
 ; STATIC-N32: addiu ${{[0-9]+}}, $[[R3]], %lo(.Ltmp[[T3]])
 ; PIC-N64: ld  $[[R0:[0-9]+]], %got_page(.Ltmp[[T0:[0-9]+]])
 ; PIC-N64: daddiu ${{[0-9]+}}, $[[R0]], %got_ofst(.Ltmp[[T0]])
 ; PIC-N64: ld  $[[R1:[0-9]+]], %got_page(.Ltmp[[T1:[0-9]+]])
 ; PIC-N64: daddiu ${{[0-9]+}}, $[[R1]], %got_ofst(.Ltmp[[T1]])
-; STATIC-N64: ld  $[[R2:[0-9]+]], %got_page(.Ltmp[[T2:[0-9]+]])
-; STATIC-N64: daddiu ${{[0-9]+}}, $[[R2]], %got_ofst(.Ltmp[[T2]])
-; STATIC-N64: ld  $[[R3:[0-9]+]], %got_page(.Ltmp[[T3:[0-9]+]])
-; STATIC-N64: daddiu ${{[0-9]+}}, $[[R3]], %got_ofst(.Ltmp[[T3]])
+
+; STATIC-N64: lui $[[R0:[0-9]]], %highest(.Ltmp[[L0:[0-9]]])
+; STATIC-N64: daddiu  $[[R1:[0-9]]], $[[R0]], %higher(.Ltmp[[L0]])
+; STATIC-N64: dsll  $[[R2:[0-9]]], $[[R1]], 16
+; STATIC-N64: daddiu  $[[R3:[0-9]]], $[[R2]], %hi(.Ltmp[[L0]])
+; STATIC-N64: dsll  $[[R4:[0-9]]], $[[R3]], 16
+; STATIC-N64: daddiu  $[[R5:[0-9]]], $[[R4]], %lo(.Ltmp[[L0]])
+
 ; STATIC-MIPS16-1: .ent f
 ; STATIC-MIPS16-2: .ent f
 ; STATIC-MIPS16-1: li  $[[R1_16:[0-9]+]], %hi($tmp[[TI_16:[0-9]+]])
 ; STATIC-MIPS16-1: sll ${{[0-9]+}},  $[[R1_16]], 16
 ; STATIC-MIPS16-2: li  ${{[0-9]+}}, %lo($tmp{{[0-9]+}})
 ; STATIC-MIPS16-1: jal  dummy
 ; STATIC-MIPS16-2: jal  dummy
 

test/CodeGen/Mips/cconv/arguments-float.ll

entry:
         store volatile double %i, double* %8
         ret void
 }
 
 ; ALL-LABEL: double_args:
 ; We won't test the way the global address is calculated in this test. This is
 ; just to get the register number for the other checks.
 ; SYM32-DAG:           addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles)
-; SYM64-DAG:           ld [[R2:\$[0-9]]], %got_disp(doubles)(
+; SYM64-DAG:           daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(doubles)
 
 ; The first four arguments are the same in O32/N32/N64.
 ; The first argument is floating point but soft-float is enabled so floating
 ; point registers are not used.
 ; O32-DAG:           sw $4, 8([[R2]])
 ; O32-DAG:           sw $5, 12([[R2]])
 ; NEW-DAG:           sd $4, 8([[R2]])
 
entry:
         store volatile float %j, float* %9
         ret void
 }
 
 ; ALL-LABEL: float_args:
 ; We won't test the way the global address is calculated in this test. This is
 ; just to get the register number for the other checks.
 ; SYM32-DAG:           addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(floats)
-; SYM64-DAG:           ld [[R2:\$[0-9]]], %got_disp(floats)(
+; SYM64-DAG:           daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(floats)
 
 ; The first four arguments are the same in O32/N32/N64.
 ; The first argument is floating point but soft-float is enabled so floating
 ; point registers are not used.
 ; MD00305 and GCC disagree on this one. MD00305 says that floats are treated
 ; as 8-byte aligned and occupy two slots on O32. GCC is treating them as 4-byte
 ; aligned and occupying one slot. We'll use GCC's definition.
 ; ALL-DAG:           sw $4, 4([[R2]])
entry:
         %1 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 1
         store volatile double %b, double* %1
         ret void
 }
 
 ; ALL-LABEL: double_arg2:
 ; We won't test the way the global address is calculated in this test. This is
 ; just to get the register number for the other checks.
-; SYM32-DAG:           addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
-; SYM64-DAG:           ld [[R1:\$[0-9]]], %got_disp(bytes)(
-; SYM32-DAG:           addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles)
-; SYM64-DAG:           ld [[R2:\$[0-9]]], %got_disp(doubles)(
+; SYM32-DAG:           addiu  [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
+; SYM64-DAG:           daddiu [[R1:\$[0-9]]], ${{[0-9]+}}, %lo(bytes)
+; SYM32-DAG:           addiu  [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles)
+; SYM64-DAG:           daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(doubles)
 
 ; The first four arguments are the same in O32/N32/N64.
 ; The first argument isn't floating point so floating point registers are not
 ; used.
 ; The second slot is insufficiently aligned for double on O32 so it is skipped.
 ; Also, double occupies two slots on O32 and only one for N32/N64.
 ; ALL-DAG:           sb $4, 1([[R1]])
 ; O32-DAG:           sw $6, 8([[R2]])
 ; O32-DAG:           sw $7, 12([[R2]])
 ; NEW-DAG:           sd $5, 8([[R2]])
 
 define void @float_arg2(i8 signext %a, float %b) nounwind {
 entry:
         %0 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 1
         store volatile i8 %a, i8* %0
         %1 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 1
         store volatile float %b, float* %1
         ret void
 }
 
 ; ALL-LABEL: float_arg2:
 ; We won't test the way the global address is calculated in this test. This is
 ; just to get the register number for the other checks.
-; SYM32-DAG:           addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
-; SYM64-DAG:           ld [[R1:\$[0-9]]], %got_disp(bytes)(
-; SYM32-DAG:           addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(floats)
-; SYM64-DAG:           ld [[R2:\$[0-9]]], %got_disp(floats)(
+; SYM32-DAG:    addiu  [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
+; SYM64-DAG:    daddiu [[R1:\$[0-9]]], ${{[0-9]+}}, %lo(bytes)
+; SYM32-DAG:    addiu  [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(floats)
+; SYM64-DAG:    daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(floats)
+
 
 ; The first four arguments are the same in O32/N32/N64.
 ; The first argument isn't floating point so floating point registers are not
 ; used.
 ; MD00305 and GCC disagree on this one. MD00305 says that floats are treated
 ; as 8-byte aligned and occupy two slots on O32. GCC is treating them as 4-byte
 ; aligned and occupying one slot. We'll use GCC's definition.
 ; ALL-DAG:           sb $4, 1([[R1]])
 ; ALL-DAG:           sw $5, 4([[R2]])

test/CodeGen/Mips/cconv/arguments-fp128.ll

entry:
         store volatile fp128 %e, fp128* %4
         ret void
 }
 
 ; ALL-LABEL: ldouble_args:
 ; We won't test the way the global address is calculated in this test. This is
 ; just to get the register number for the other checks.
 ; SYM32-DAG:           addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(ldoubles)
-; SYM64-DAG:           ld [[R2:\$[0-9]]], %got_disp(ldoubles)(
+; SYM64-DAG:           daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(ldoubles)
 
 ; The first four arguments are the same in N32/N64.
 ; The first argument is floating point but soft-float is enabled so floating
 ; point registers are not used.
 ; ALL-DAG:           sd $4, 16([[R2]])
 ; ALL-DAG:           sd $5, 24([[R2]])
 ; ALL-DAG:           sd $6, 32([[R2]])
 ; ALL-DAG:           sd $7, 40([[R2]])

test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll

entry:
         call void @llvm.va_end(i8* %ap2)
         ret void
 }
 
 ; ALL-LABEL: double_args:
 ; We won't test the way the global address is calculated in this test. This is
 ; just to get the register number for the other checks.
 ; SYM32-DAG:         addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles)
-; SYM64-DAG:         ld [[R2:\$[0-9]]], %got_disp(doubles)(
+; SYM64-DAG:         daddiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles)
 
 ; O32 forbids using floating point registers for the non-variable portion.
 ; N32/N64 allow it.
 ; O32BE-DAG:         mtc1 $5, [[FTMP1:\$f[0-9]*[02468]+]]
 ; O32BE-DAG:         mtc1 $4, [[FTMP2:\$f[0-9]*[13579]+]]
 ; O32LE-DAG:         mtc1 $4, [[FTMP1:\$f[0-9]*[02468]+]]
 ; O32LE-DAG:         mtc1 $5, [[FTMP2:\$f[0-9]*[13579]+]]
 ; O32-DAG:           sdc1 [[FTMP1]], 8([[R2]])
entry:
         call void @llvm.va_end(i8* %ap2)
         ret void
 }
 
 ; ALL-LABEL: float_args:
 ; We won't test the way the global address is calculated in this test. This is
 ; just to get the register number for the other checks.
 ; SYM32-DAG:         addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(floats)
-; SYM64-DAG:         ld [[R2:\$[0-9]]], %got_disp(floats)(
+; SYM64-DAG:         daddiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(floats)
 
 ; The first four arguments are the same in O32/N32/N64.
 ; The non-variable portion should be unaffected.
 ; O32-DAG:           sw $4, 4([[R2]])
 ; NEW-DAG:           swc1 $f12, 4([[R2]])
 
 ; The varargs portion is dumped to stack
 ; O32-DAG:           sw $5, 12($sp)

test/CodeGen/Mips/cconv/arguments-hard-float.ll

entry:
         store volatile double %i, double* %8
         ret void
 }
 
 ; ALL-LABEL: double_args:
 ; We won't test the way the global address is calculated in this test. This is
 ; just to get the register number for the other checks.
 ; SYM32-DAG:           addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles)
-; SYM64-DAG:           ld [[R2:\$[0-9]]], %got_disp(doubles)(
+; SYM64-DAG:           daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(doubles)
 
 ; The first argument is floating point so floating point registers are used.
 ; The first argument is the same for O32/N32/N64 but the second argument differs
 ; by register
 ; ALL-DAG:           sdc1 $f12, 8([[R2]])
 ; O32-DAG:           sdc1 $f14, 16([[R2]])
 ; NEW-DAG:           sdc1 $f13, 16([[R2]])
 
entry:
         %8 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 9
         store volatile float %i, float* %8
         ret void
 }
 
 ; ALL-LABEL: float_args:
 ; We won't test the way the global address is calculated in this test. This is
 ; just to get the register number for the other checks.
-; SYM32-DAG:           addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(floats)
-; SYM64-DAG:           ld [[R1:\$[0-9]]], %got_disp(floats)(
+; SYM32-DAG:           addiu  [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(floats)
+; SYM64-DAG:           daddiu [[R1:\$[0-9]]], ${{[0-9]+}}, %lo(floats)
 
 ; The first argument is floating point so floating point registers are used.
 ; The first argument is the same for O32/N32/N64 but the second argument differs
 ; by register
 ; ALL-DAG:           swc1 $f12, 4([[R1]])
 ; O32-DAG:           swc1 $f14, 8([[R1]])
 ; NEW-DAG:           swc1 $f13, 8([[R1]])
 
entry:
         store volatile double %b, double* %1
         ret void
 }
 
 ; ALL-LABEL: double_arg2:
 ; We won't test the way the global address is calculated in this test. This is
 ; just to get the register number for the other checks.
 ; SYM32-DAG:           addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
-; SYM64-DAG:           ld [[R1:\$[0-9]]], %got_disp(bytes)(
+; SYM64-DAG:           daddiu [[R1:\$[0-9]]], ${{[0-9]+}}, %lo(bytes)
 ; SYM32-DAG:           addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles)
-; SYM64-DAG:           ld [[R2:\$[0-9]]], %got_disp(doubles)(
+; SYM64-DAG:           daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(doubles)
 
 ; The first argument is the same in O32/N32/N64.
 ; ALL-DAG:           sb $4, 1([[R1]])
 
 ; The first argument isn't floating point so floating point registers are not
 ; used in O32, but N32/N64 will still use them.
 ; The second slot is insufficiently aligned for double on O32 so it is skipped.
 ; Also, double occupies two slots on O32 and only one for N32/N64.
entry:
         store volatile float %b, float* %1
         ret void
 }
 
 ; ALL-LABEL: float_arg2:
 ; We won't test the way the global address is calculated in this test. This is
 ; just to get the register number for the other checks.
 ; SYM32-DAG:           addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
-; SYM64-DAG:           ld [[R1:\$[0-9]]], %got_disp(bytes)(
+; SYM64-DAG:           daddiu [[R1:\$[0-9]]], ${{[0-9]+}}, %lo(bytes)
 ; SYM32-DAG:           addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(floats)
-; SYM64-DAG:           ld [[R2:\$[0-9]]], %got_disp(floats)(
+; SYM64-DAG:           daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(floats)
 
 ; The first argument is the same in O32/N32/N64.
 ; ALL-DAG:           sb $4, 1([[R1]])
 
 ; The first argument isn't floating point so floating point registers are not
 ; used in O32, but N32/N64 will still use them.
 ; MD00305 and GCC disagree on this one. MD00305 says that floats are treated
 ; as 8-byte aligned and occupy two slots on O32. GCC is treating them as 4-byte
 ; aligned and occupying one slot. We'll use GCC's definition.
 ; O32-DAG:           sw $5, 4([[R2]])
 ; NEW-DAG:           swc1 $f13, 4([[R2]])

test/CodeGen/Mips/cconv/arguments-hard-fp128.ll

entry:
         store volatile fp128 %e, fp128* %4
         ret void
 }
 
 ; ALL-LABEL: ldouble_args:
 ; We won't test the way the global address is calculated in this test. This is
 ; just to get the register number for the other checks.
 ; SYM32-DAG:           addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(ldoubles)
-; SYM64-DAG:           ld [[R2:\$[0-9]]], %got_disp(ldoubles)(
+; SYM64-DAG:           daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(ldoubles)
 
 ; The first four arguments are the same in N32/N64.
 ; ALL-DAG:           sdc1 $f12, 16([[R2]])
 ; ALL-DAG:           sdc1 $f13, 24([[R2]])
 ; ALL-DAG:           sdc1 $f14, 32([[R2]])
 ; ALL-DAG:           sdc1 $f15, 40([[R2]])
 ; ALL-DAG:           sdc1 $f16, 48([[R2]])
 ; ALL-DAG:           sdc1 $f17, 56([[R2]])
 ; ALL-DAG:           sdc1 $f18, 64([[R2]])
 ; ALL-DAG:           sdc1 $f19, 72([[R2]])
 
 ; N32/N64 have run out of registers and starts using the stack too
 ; ALL-DAG:           ld [[R3:\$[0-9]+]], 0($sp)
 ; ALL-DAG:           ld [[R4:\$[0-9]+]], 8($sp)
 ; ALL-DAG:           sd [[R3]], 80([[R2]])
 ; ALL-DAG:           sd [[R4]], 88([[R2]])

test/CodeGen/Mips/cconv/arguments-struct.ll

store i8 %a, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @bytes, i32 0, i32 1)
         ret void
 }
 
 ; ALL-LABEL: s_i8:
 
 ; SYM32-DAG:   lui   [[PTR_HI:\$[0-9]+]], %hi(bytes)
 ; SYM32-DAG:   addiu [[PTR:\$[0-9]+]], [[PTR_HI]], %lo(bytes)
 
-; SYM64-DAG:   ld    [[PTR:\$[0-9]+]], %got_disp(bytes)(
+; SYM64-DAG:   addiu [[PTR:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
 
 ; O32-BE-DAG:  srl [[ARG:\$[0-9]+]], $4, 24
 ; O32-BE-DAG:  sb  [[ARG]], 1([[PTR]])
 
 ; O32-LE-DAG:  sb  $4, 1([[PTR]])
 
 ; NEW-BE-DAG:  dsrl [[ARG:\$[0-9]+]], $4, 56
 ; NEW-BE-DAG:  sb   [[ARG]], 1([[PTR]])
 
 ; NEW-LE-DAG:  sb   $4, 1([[PTR]])

test/CodeGen/Mips/cconv/arguments-varargs-small-structs-byte.ll

entry:
   store %struct.SmallStruct_8b* %ss, %struct.SmallStruct_8b** %ss.addr, align 8
   %0 = load %struct.SmallStruct_8b*, %struct.SmallStruct_8b** %ss.addr, align 8
   %1 = bitcast %struct.SmallStruct_8b* %0 to { i64 }*
   %2 = getelementptr { i64 }, { i64 }* %1, i32 0, i32 0
   %3 = load i64, i64* %2, align 1
   call void (i8*, ...) @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i64 inreg %3)
   ret void
  ; CHECK-LABEL: smallStruct_8b:
+ ; Check that the structure is not shifted before the pointer to str is loaded.
  ; CHECK-NOT: dsll
+ ; CHECK: lui
 }
 
 define void @smallStruct_9b(%struct.SmallStruct_9b* %ss) #0 {
 entry:
   %ss.addr = alloca %struct.SmallStruct_9b*, align 8
   %.coerce = alloca { i64, i8 }
   store %struct.SmallStruct_9b* %ss, %struct.SmallStruct_9b** %ss.addr, align 8
   %0 = load %struct.SmallStruct_9b*, %struct.SmallStruct_9b** %ss.addr, align 8

test/CodeGen/Mips/cconv/arguments-varargs-small-structs-combinations.ll

entry:
   %0 = load %struct.SmallStruct_1b1i*, %struct.SmallStruct_1b1i** %ss.addr, align 8
   %1 = bitcast %struct.SmallStruct_1b1i* %0 to { i64 }*
   %2 = getelementptr { i64 }, { i64 }* %1, i32 0, i32 0
   %3 = load i64, i64* %2, align 1
   call void (i8*, ...) @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i64 inreg %3)
   ret void
  ; CHECK-LABEL: smallStruct_1b1i:
  ; CHECK-NOT: dsll
+ ; CHECK: lui
 }
 
 define void @smallStruct_1b1s1b(%struct.SmallStruct_1b1s1b* %ss) #0 {
 entry:
   %ss.addr = alloca %struct.SmallStruct_1b1s1b*, align 8
   %.coerce = alloca { i48 }
   store %struct.SmallStruct_1b1s1b* %ss, %struct.SmallStruct_1b1s1b** %ss.addr, align 8
   %0 = load %struct.SmallStruct_1b1s1b*, %struct.SmallStruct_1b1s1b** %ss.addr, align 8
entry:
   %0 = load %struct.SmallStruct_1s1i*, %struct.SmallStruct_1s1i** %ss.addr, align 8
   %1 = bitcast %struct.SmallStruct_1s1i* %0 to { i64 }*
   %2 = getelementptr { i64 }, { i64 }* %1, i32 0, i32 0
   %3 = load i64, i64* %2, align 1
   call void (i8*, ...) @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i64 inreg %3)
   ret void
  ; CHECK-LABEL: smallStruct_1s1i:
  ; CHECK-NOT: dsll
+ ; CHECK: lui
 }
 
 define void @smallStruct_3b1s(%struct.SmallStruct_3b1s* %ss) #0 {
 entry:
   %ss.addr = alloca %struct.SmallStruct_3b1s*, align 8
   %.coerce = alloca { i48 }
   store %struct.SmallStruct_3b1s* %ss, %struct.SmallStruct_3b1s** %ss.addr, align 8
   %0 = load %struct.SmallStruct_3b1s*, %struct.SmallStruct_3b1s** %ss.addr, align 8

test/CodeGen/Mips/cconv/arguments-varargs.ll

 ; NEW-LE-DAG:    lw [[ARG1:\$[0-9]+]], 0([[VA]])
 ; NEW-BE-DAG:    lw [[ARG1:\$[0-9]+]], 4([[VA]])
 
 ; Copy the arg to the global
 ; O32-DAG:       addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords)
 
 ; N32-DAG:       addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords)
 
-; N64-DAG:       ld [[GV:\$[0-9]+]], %got_disp(hwords)(
+; N64-DAG:       daddiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords)
 
 ; ALL-DAG:       sh [[ARG1]], 2([[GV]])
 
 ; ALL: teqi $zero, 2
 
 ; Increment [[VA]] again.
 ; O32-DAG:       lw [[VA:\$[0-9]+]], 0([[SP]])
 ; O32-DAG:       addiu [[VA2:\$[0-9]+]], [[VA]], 4

 ; NEW-LE-DAG:    lw [[ARG1:\$[0-9]+]], 0([[VA]])
 ; NEW-BE-DAG:    lw [[ARG1:\$[0-9]+]], 4([[VA]])
 
 ; Copy the arg to the global
 ; O32-DAG:       addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words)
 
 ; N32-DAG:       addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words)
 
-; N64-DAG:       ld [[GV:\$[0-9]+]], %got_disp(words)(
+; N64-DAG:       daddiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words)
 
 ; ALL-DAG:       sw [[ARG1]], 4([[GV]])
 
 ; ALL: teqi $zero, 2
 
 ; Increment [[VA]] again.
 ; O32-DAG:       lw [[VA:\$[0-9]+]], 0([[SP]])
 ; O32-DAG:       addiu [[VA2:\$[0-9]+]], [[VA]], 4

 ; O32-DAG:       sw [[ARG1]], 8([[GV]])
 ; O32-DAG:       lw [[VA:\$[0-9]+]], 0([[SP]])
 ; O32-DAG:       addiu [[VA2:\$[0-9]+]], [[VA]], 4
 ; O32-DAG:       sw [[VA2]], 0([[SP]])
 ; O32-DAG:       lw [[ARG1:\$[0-9]+]], 0([[VA]])
 ; O32-DAG:       sw [[ARG1]], 12([[GV]])
 
 ; N32-DAG:       addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)
-; N64-DAG:       ld [[GV:\$[0-9]+]], %got_disp(dwords)(
+; N64-DAG:       daddiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)
 ; NEW-DAG:       ld [[ARG1:\$[0-9]+]], 0([[VA]])
 ; NEW-DAG:       sd [[ARG1]], 8([[GV]])
 
 ; ALL: teqi $zero, 2
 
 ; Increment [[VA]] again.
 ; FIXME: We're still aligned from the last one but CodeGen doesn't spot that.
 ; O32:           lw [[VA:\$[0-9]+]], 0([[SP]])

 ; NEW-LE-DAG:    lw [[ARG1:\$[0-9]+]], 0([[VA]])
 ; NEW-BE-DAG:    lw [[ARG1:\$[0-9]+]], 4([[VA]])
 
 ; Copy the arg to the global
 ; O32-DAG:       addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords)
 
 ; N32-DAG:       addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords)
 
-; N64-DAG:       ld [[GV:\$[0-9]+]], %got_disp(hwords)(
+; N64-DAG:       daddiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords)
 
 ; ALL-DAG:       sh [[ARG1]], 2([[GV]])
 
 ; ALL: teqi $zero, 2
 
 ; Increment [[VA]] again.
 ; O32-DAG:       lw [[VA:\$[0-9]+]], 0([[SP]])
 ; O32-DAG:       addiu [[VA2:\$[0-9]+]], [[VA]], 4

 ; NEW-LE-DAG:    lw [[ARG1:\$[0-9]+]], 0([[VA]])
 ; NEW-BE-DAG:    lw [[ARG1:\$[0-9]+]], 4([[VA]])
 
 ; Copy the arg to the global
 ; O32-DAG:       addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words)
 
 ; N32-DAG:       addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words)
 
-; N64-DAG:       ld [[GV:\$[0-9]+]], %got_disp(words)(
+; N64-DAG:       daddiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words)
 
 ; ALL-DAG:       sw [[ARG1]], 4([[GV]])
 
 ; ALL: teqi $zero, 2
 
 ; Increment [[VA]] again.
 ; O32-DAG:       lw [[VA:\$[0-9]+]], 0([[SP]])
 ; O32-DAG:       addiu [[VA2:\$[0-9]+]], [[VA]], 4

 ; O32-DAG:       sw [[ARG1]], 8([[GV]])
 ; O32-DAG:       lw [[VA:\$[0-9]+]], 0([[SP]])
 ; O32-DAG:       addiu [[VA2:\$[0-9]+]], [[VA]], 4
 ; O32-DAG:       sw [[VA2]], 0([[SP]])
 ; O32-DAG:       lw [[ARG1:\$[0-9]+]], 0([[VA]])
 ; O32-DAG:       sw [[ARG1]], 12([[GV]])
 
 ; N32-DAG:       addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)
-; N64-DAG:       ld [[GV:\$[0-9]+]], %got_disp(dwords)(
+; N64-DAG:       daddiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)
 ; NEW-DAG:       ld [[ARG1:\$[0-9]+]], 0([[VA]])
 ; NEW-DAG:       sd [[ARG1]], 8([[GV]])
 
 ; ALL: teqi $zero, 2
 
 ; Increment [[VA]] again.
 ; FIXME: We're still aligned from the last one but CodeGen doesn't spot that.
 ; O32:           lw [[VA:\$[0-9]+]], 0([[SP]])

 ; NEW-LE-DAG:    lw [[ARG1:\$[0-9]+]], 0([[VA]])
 ; NEW-BE-DAG:    lw [[ARG1:\$[0-9]+]], 4([[VA]])
 
 ; Copy the arg to the global
 ; O32-DAG:       addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords)
 
 ; N32-DAG:       addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords)
 
-; N64-DAG:       ld [[GV:\$[0-9]+]], %got_disp(hwords)(
+; N64-DAG:       daddiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords)
 
 ; ALL-DAG:       sh [[ARG1]], 2([[GV]])
 
 ; ALL: teqi $zero, 2
 
 ; Increment [[VA]] again.
 ; O32-DAG:       lw [[VA:\$[0-9]+]], 0([[SP]])
 ; O32-DAG:       addiu [[VA2:\$[0-9]+]], [[VA]], 4

 ; NEW-LE-DAG:    lw [[ARG1:\$[0-9]+]], 0([[VA]])
 ; NEW-BE-DAG:    lw [[ARG1:\$[0-9]+]], 4([[VA]])
 
 ; Copy the arg to the global
 ; O32-DAG:       addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words)
 
 ; N32-DAG:       addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words)
 
-; N64-DAG:       ld [[GV:\$[0-9]+]], %got_disp(words)(
+; N64-DAG:       daddiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words)
 
 ; ALL-DAG:       sw [[ARG1]], 4([[GV]])
 
 ; ALL: teqi $zero, 2
 
 ; Increment [[VA]] again.
 ; O32-DAG:       lw [[VA:\$[0-9]+]], 0([[SP]])
 ; O32-DAG:       addiu [[VA2:\$[0-9]+]], [[VA]], 4

 ; O32-DAG:       sw [[ARG1]], 8([[GV]])
 ; O32-DAG:       lw [[VA:\$[0-9]+]], 0([[SP]])
 ; O32-DAG:       addiu [[VA2:\$[0-9]+]], [[VA]], 4
 ; O32-DAG:       sw [[VA2]], 0([[SP]])
 ; O32-DAG:       lw [[ARG1:\$[0-9]+]], 0([[VA]])
 ; O32-DAG:       sw [[ARG1]], 12([[GV]])
 
 ; N32-DAG:       addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)
-; N64-DAG:       ld [[GV:\$[0-9]+]], %got_disp(dwords)(
+; N64-DAG:       daddiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)
 ; NEW-DAG:       ld [[ARG1:\$[0-9]+]], 0([[VA]])
 ; NEW-DAG:       sd [[ARG1]], 8([[GV]])
 
 ; ALL: teqi $zero, 2
 
 ; Increment [[VA]] again.
 ; FIXME: We're still aligned from the last one but CodeGen doesn't spot that.
 ; O32:           lw [[VA:\$[0-9]+]], 0([[SP]])

test/CodeGen/Mips/cconv/arguments.ll

entry:
         store volatile i8 %j, i8* %9
         ret void
 }
 
 ; ALL-LABEL: align_to_arg_slots:
 ; We won't test the way the global address is calculated in this test. This is
 ; just to get the register number for the other checks.
 ; SYM32-DAG:           addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
-; SYM64-DAG:           ld [[R1:\$[0-9]+]], %got_disp(bytes)(
+; SYM64-DAG:           daddiu [[R1:\$[0-9]+]], ${{[0-9]+}},  %lo(bytes)
 
 ; The first four arguments are the same in O32/N32/N64
 ; ALL-DAG:           sb $4, 1([[R1]])
 ; ALL-DAG:           sb $5, 2([[R1]])
 ; ALL-DAG:           sb $6, 3([[R1]])
 ; ALL-DAG:           sb $7, 4([[R1]])
 
 ; N32/N64 get an extra four arguments in registers
entry:
         store volatile i8 %j, i8* %8
         ret void
 }
 
 ; ALL-LABEL: slot_skipping:
 ; We won't test the way the global address is calculated in this test. This is
 ; just to get the register number for the other checks.
 ; SYM32-DAG:           addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
-; SYM64-DAG:           ld [[R1:\$[0-9]+]], %got_disp(bytes)(
+; SYM64-DAG:           daddiu [[R1:\$[0-9]+]], ${{[0-9]+}},  %lo(bytes)
 ; SYM32-DAG:           addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)
-; SYM64-DAG:           ld [[R2:\$[0-9]+]], %got_disp(dwords)(
+; SYM64-DAG:           daddiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)
 
 ; The first argument is the same in O32/N32/N64.
 ; ALL-DAG:           sb $4, 1([[R1]])
 
 ; The second slot is insufficiently aligned for i64 on O32 so it is skipped.
 ; Also, i64 occupies two slots on O32 and only one for N32/N64.
 ; O32-DAG:           sw $6, 8([[R2]])
 ; O32-DAG:           sw $7, 12([[R2]])

test/CodeGen/Mips/cconv/return-float.ll

entry:
         ret float %0
 }
 
 ; ALL-LABEL: retfloat:
 ; O32-DAG:           lui [[R1:\$[0-9]+]], %hi(float)
 ; O32-DAG:           lw $2, %lo(float)([[R1]])
 ; N32-DAG:           lui [[R1:\$[0-9]+]], %hi(float)
 ; N32-DAG:           lw $2, %lo(float)([[R1]])
-; N64-DAG:           ld  [[R1:\$[0-9]+]], %got_disp(float)(
-; N64-DAG:           lw $2, 0([[R1]])
+; N64-DAG:           lw $2, %lo(float)([[R1:\$[0-9+]]])
 
 define double @retdouble() nounwind {
 entry:
         %0 = load volatile double, double* @double
         ret double %0
 }
 
 ; ALL-LABEL: retdouble:
 ; O32-DAG:           lw $2, %lo(double)([[R1:\$[0-9]+]])
 ; O32-DAG:           addiu [[R2:\$[0-9]+]], [[R1]], %lo(double)
 ; O32-DAG:           lw $3, 4([[R2]])
 ; N32-DAG:           ld $2, %lo(double)([[R1:\$[0-9]+]])
-; N64-DAG:           ld  [[R1:\$[0-9]+]], %got_disp(double)(
-; N64-DAG:           ld $2, 0([[R1]])
+; N64-DAG:           ld $2, %lo(double)([[R1:\$[0-9]+]])

test/CodeGen/Mips/cconv/return-hard-float.ll

entry:
         ret float %0
 }
 
 ; ALL-LABEL: retfloat:
 ; O32-DAG:           lui [[R1:\$[0-9]+]], %hi(float)
 ; O32-DAG:           lwc1 $f0, %lo(float)([[R1]])
 ; N32-DAG:           lui [[R1:\$[0-9]+]], %hi(float)
 ; N32-DAG:           lwc1 $f0, %lo(float)([[R1]])
-; N64-DAG:           ld  [[R1:\$[0-9]+]], %got_disp(float)(
-; N64-DAG:           lwc1 $f0, 0([[R1]])
+; N64-DAG:           lwc1 $f0, %lo(float)([[R1:\$[0-9+]]])
 
 define double @retdouble() nounwind {
 entry:
         %0 = load volatile double, double* @double
         ret double %0
 }
 
 ; ALL-LABEL: retdouble:
 ; O32-DAG:           ldc1 $f0, %lo(double)([[R1:\$[0-9]+]])
 ; N32-DAG:           ldc1 $f0, %lo(double)([[R1:\$[0-9]+]])
-; N64-DAG:           ld  [[R1:\$[0-9]+]], %got_disp(double)(
-; N64-DAG:           ldc1 $f0, 0([[R1]])
+; N64-DAG:           ldc1 $f0, %lo(double)([[R1:\$[0-9]+]])
 
 define { double, double } @retComplexDouble() #0 {
   %retval = alloca { double, double }, align 8
   %1 = load { double, double }, { double, double }* %retval
   ret { double, double } %1
 }
 
 ; ALL-LABEL: retComplexDouble:
 ; 032FP64-DAG:      ldc1     $f0, 0($sp)
 ; 032FP64-DAG:      ldc1     $f2, 8($sp)

test/CodeGen/Mips/cconv/return-hard-fp128.ll

 
 ; ALL-LABEL: retldouble:
 ; N32-DAG:           ld [[R2:\$[0-9]+]], %lo(fp128)([[R1:\$[0-9]+]])
 ; N32-DAG:           addiu [[R3:\$[0-9]+]], [[R1]], %lo(fp128)
 ; N32-DAG:           ld [[R4:\$[0-9]+]], 8([[R3]])
 ; N32-DAG:           dmtc1 [[R2]], $f0
 ; N32-DAG:           dmtc1 [[R4]], $f2
 
-; N64-DAG:           ld [[R2:\$[0-9]+]], %got_disp(fp128)([[R1:\$[0-9]+]])
-; N64-DAG:           ld [[R3:\$[0-9]+]], 0([[R2]])
+; N64-DAG:           lui [[R2:\$[0-9]+]], %highest(fp128)
+; N64-DAG:           ld [[R3:\$[0-9]+]], %lo(fp128)([[R2]])
 ; N64-DAG:           ld [[R4:\$[0-9]+]], 8([[R2]])
 ; N64-DAG:           dmtc1 [[R3]], $f0
 ; N64-DAG:           dmtc1 [[R4]], $f2

test/CodeGen/Mips/cconv/return-hard-struct-f128.ll

 ; match the de facto ABI as implemented by GCC.
 ; N32-DAG:        lui [[R1:\$[0-9]+]], %hi(struct_fp128)
 ; N32-DAG:        ld  [[R2:\$[0-9]+]], %lo(struct_fp128)([[R1]])
 ; N32-DAG:        dmtc1 [[R2]], $f0
 ; N32-DAG:        addiu [[R3:\$[0-9]+]], [[R1]], %lo(struct_fp128)
 ; N32-DAG:        ld  [[R4:\$[0-9]+]], 8([[R3]])
 ; N32-DAG:        dmtc1 [[R4]], $f1
 
-; N64-DAG:        ld  [[R1:\$[0-9]+]], %got_disp(struct_fp128)($1)
-; N64-DAG:        ld  [[R2:\$[0-9]+]], 0([[R1]])
+; N64-DAG:        lui  [[R1:\$[0-9]+]], %highest(struct_fp128)
+; N64-DAG:        ld  [[R2:\$[0-9]+]], %lo(struct_fp128)([[R1]])
 ; N64-DAG:        dmtc1 [[R2]], $f0
 ; N64-DAG:        ld  [[R4:\$[0-9]+]], 8([[R1]])
 ; N64-DAG:        dmtc1 [[R4]], $f1

test/CodeGen/Mips/cconv/return-struct.ll

 
 ; N32-LE-DAG:        lui [[R1:\$[0-9]+]], %hi(struct_byte)
 ; N32-LE-DAG:        lb $2, %lo(struct_byte)([[R1]])
 
 ; N32-BE-DAG:        lui [[R1:\$[0-9]+]], %hi(struct_byte)
 ; N32-BE-DAG:        lb [[R2:\$[0-9]+]], %lo(struct_byte)([[R1]])
 ; N32-BE-DAG:        dsll $2, [[R2]], 56
 
-; N64-LE-DAG:        ld  [[R1:\$[0-9]+]], %got_disp(struct_byte)($1)
-; N64-LE-DAG:        lb $2, 0([[R1]])
+; N64-LE-DAG:        lb $2, %lo(struct_byte)(${{[0-9]+}})
 
-; N64-BE-DAG:        ld  [[R1:\$[0-9]+]], %got_disp(struct_byte)($1)
-; N64-BE-DAG:        lb [[R2:\$[0-9]+]], 0([[R1]])
-; N64-BE-DAG:        dsll $2, [[R2]], 56
+; N64-BE-DAG:        lb [[R1:\$[0-9]+]], %lo(struct_byte)(${{[0-9]+}})
+; N64-BE-DAG:        dsll $2, [[R1]], 56
 
 ; This test is based on the way clang currently lowers {i8,i8} to {i16}.
 ; FIXME: It should probably work for without any lowering too but this doesn't
 ;        work as expected. Each member gets mapped to a register rather than
 ;        packed into a single register.
 define inreg {i16} @ret_struct_i16() nounwind {
 entry:
         %retval = alloca {i8,i8}, align 1

 ; N32-LE-DAG:        lh  $2, 8([[SP:\$sp]])
 
 ; N32-BE-DAG:        lui [[R1:\$[0-9]+]], %hi(struct_2byte)
 ; N32-BE-DAG:        lhu [[R2:\$[0-9]+]], %lo(struct_2byte)([[R1]])
 ; N32-BE-DAG:        sh  [[R2]], 8([[SP:\$sp]])
 ; N32-BE-DAG:        lh  [[R3:\$[0-9]+]], 8([[SP:\$sp]])
 ; N32-BE-DAG:        dsll $2, [[R3]], 48
 
-; N64-LE-DAG:        ld  [[R1:\$[0-9]+]], %got_disp(struct_2byte)($1)
-; N64-LE-DAG:        lhu [[R2:\$[0-9]+]], 0([[R1]])
+; N64-LE-DAG:        daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %hi(struct_2byte)
+; N64-LE-DAG:        dsll [[R1:\$[0-9]]], $[[R0]], 16
+; N64-LE-DAG:        lhu [[R2:\$[0-9]+]], %lo(struct_2byte)([[R1]])
 ; N64-LE-DAG:        sh  [[R2]], 8([[SP:\$sp]])
 ; N64-LE-DAG:        lh  $2, 8([[SP:\$sp]])
 
-; N64-BE-DAG:        ld  [[R1:\$[0-9]+]], %got_disp(struct_2byte)($1)
-; N64-BE-DAG:        lhu [[R2:\$[0-9]+]], 0([[R1]])
+; N64-BE-DAG:        daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %hi(struct_2byte)
+; N64-BE-DAG:        dsll $[[R1:[0-9]]], $[[R0]], 16
+; N64-BE-DAG:        lhu [[R2:\$[0-9]+]], %lo(struct_2byte)($[[R1]])
 ; N64-BE-DAG:        sh  [[R2]], 8([[SP:\$sp]])
 ; N64-BE-DAG:        lh  [[R3:\$[0-9]+]], 8([[SP:\$sp]])
 ; N64-BE-DAG:        dsll $2, [[R3]], 48
 
 ; Ensure that structures bigger than 32-bits but smaller than 64-bits are
 ; also returned in the upper bits on big endian targets. Previously, these were
 ; missed by the CCPromoteToType and the shift didn't happen.
 define inreg {i48} @ret_struct_3xi16() nounwind {

 ; N32-BE-DAG:        lui [[PTR_HI:\$[0-9]+]], %hi(struct_3xi16)
 ; N32-BE-DAG:        addiu [[PTR_LO:\$[0-9]+]], [[PTR_HI]], %lo(struct_3xi16)
 ; N32-BE-DAG:        lw [[R1:\$[0-9]+]], %lo(struct_3xi16)([[PTR_HI]])
 ; N32-BE-DAG:        dsll [[R2:\$[0-9]+]], [[R1]], 16
 ; N32-BE-DAG:        lhu [[R3:\$[0-9]+]], 4([[PTR_LO]])
 ; N32-BE-DAG:        or [[R4:\$[0-9]+]], [[R3]], [[R2]]
 ; N32-BE-DAG:        dsll $2, [[R4]], 16
 
-; N64-LE-DAG:        ld  [[PTR:\$[0-9]+]], %got_disp(struct_3xi16)($1)
+; N64-LE-DAG:        daddiu [[PTR:\$[0-9]+]], [[R0:\$[0-9]+]], %lo(struct_3xi16)
 ; N64-LE-DAG:        lh [[R1:\$[0-9]+]], 4([[PTR]])
-; N64-LE-DAG:        lwu [[R2:\$[0-9]+]], 0([[PTR]])
+; N64-LE-DAG:        lwu [[R2:\$[0-9]+]], %lo(struct_3xi16)([[R0]])
 ; N64-LE-DAG:        dsll [[R3:\$[0-9]+]], [[R1]], 32
 ; N64-LE-DAG:        or $2, [[R2]], [[R3]]
 
-; N64-BE-DAG:        ld  [[PTR:\$[0-9]+]], %got_disp(struct_3xi16)($1)
-; N64-BE-DAG:        lw [[R1:\$[0-9]+]], 0([[PTR]])
+; N64-BE-DAG:        daddiu [[PTR:\$[0-9]+]], [[R0:\$[0-9]+]], %lo(struct_3xi16)
+; N64-BE-DAG:        lw [[R1:\$[0-9]+]], %lo(struct_3xi16)([[R0]])
 ; N64-BE-DAG:        dsll [[R2:\$[0-9]+]], [[R1]], 16
 ; N64-BE-DAG:        lhu [[R3:\$[0-9]+]], 4([[PTR]])
 ; N64-BE-DAG:        or [[R4:\$[0-9]+]], [[R3]], [[R2]]
 ; N32-BE-DAG:        dsll $2, [[R4]], 16
 
 ; Ensure that large structures (>128-bit) are returned indirectly.
 ; We pick an extremely large structure so we don't have to match inlined memcpy's.
 define void @ret_struct_128xi16({[128 x i16]}* sret %returnval) {

 ; O32:            jal memcpy
 
 ; sret pointer is already in $4
 ; N32-DAG:        lui [[PTR_HI:\$[0-9]+]], %hi(struct_128xi16)
 ; N32-DAG:        addiu [[PTR:\$[0-9]+]], [[PTR_HI]], %lo(struct_128xi16)
 ; N32:            jal memcpy
 
 ; sret pointer is already in $4
-; N64-DAG:        ld $5, %got_disp(struct_128xi16)(
-; N64-DAG:        ld $25, %call16(memcpy)(
-; N64:            jalr $25
+; N64-DAG:        lui ${{[0-9]}}, %highest(struct_128xi16)
+; N64:            jal memcpy
 
 ; Ensure that large structures (>128-bit) are returned indirectly.
 ; This will generate inlined memcpy's anyway so pick the smallest large
 ; structure
 ; This time we let the backend lower the sret argument.
 define {[6 x i32]} @ret_struct_6xi32() {
 entry:
         %0 = load volatile {[6 x i32]}, {[6 x i32]}* @struct_6xi32, align 2

 ; N32-DAG:        sw [[T0]], 0([[RET_PTR]])
 ; N32-DAG:        sw [[T1]], 4([[RET_PTR]])
 ; N32-DAG:        sw [[T2]], 8([[RET_PTR]])
 ; N32-DAG:        sw [[T3]], 12([[RET_PTR]])
 ; N32-DAG:        sw [[T4]], 16([[RET_PTR]])
 ; N32-DAG:        sw [[T5]], 20([[RET_PTR]])
 
 ; sret pointer is already in $4
-; N64-DAG:        ld [[PTR:\$[0-9]+]], %got_disp(struct_6xi32)(
-; N64-DAG:        lw [[T0:\$[0-9]+]], 0([[PTR]])
+; N64-DAG:        lui [[PTR_HI:\$[0-9]+]], %highest(struct_6xi32)
+; N64-DAG:        daddiu [[PTR:\$[0-9]+]], [[PTR_HI]], %lo(struct_6xi32)
 ; N64-DAG:        lw [[T1:\$[0-9]+]], 4([[PTR]])
 ; N64-DAG:        lw [[T2:\$[0-9]+]], 8([[PTR]])
 ; N64-DAG:        lw [[T3:\$[0-9]+]], 12([[PTR]])
 ; N64-DAG:        lw [[T4:\$[0-9]+]], 16([[PTR]])
 ; N64-DAG:        lw [[T5:\$[0-9]+]], 20([[PTR]])
+; N64-DAG:        lw [[T0:\$[0-9]+]], %lo(struct_6xi32)([[PTR_HI]])
 ; N64-DAG:        sw [[T0]], 0($4)
 ; N64-DAG:        sw [[T1]], 4($4)
 ; N64-DAG:        sw [[T2]], 8($4)
 ; N64-DAG:        sw [[T3]], 12($4)
 ; N64-DAG:        sw [[T4]], 16($4)
 ; N64-DAG:        sw [[T5]], 20($4)

test/CodeGen/Mips/cconv/return.ll

entry:
         ret i8 %0
 }
 
 ; ALL-LABEL: reti8:
 ; O32-DAG:           lui [[R1:\$[0-9]+]], %hi(byte)
 ; O32-DAG:           lbu $2, %lo(byte)([[R1]])
 ; N32-DAG:           lui [[R1:\$[0-9]+]], %hi(byte)
 ; N32-DAG:           lbu $2, %lo(byte)([[R1]])
-; N64-DAG:           ld  [[R1:\$[0-9]+]], %got_disp(byte)(
-; N64-DAG:           lbu $2, 0([[R1]])
+; N64-DAG:           lui  [[R1:\$[0-9]+]], %highest(byte)
+; N64-DAG:           lbu $2, %lo(byte)([[R1]])
 
 define i32 @reti32() nounwind {
 entry:
         %0 = load volatile i32, i32* @word
         ret i32 %0
 }
 
 ; ALL-LABEL: reti32:
 ; O32-DAG:           lui [[R1:\$[0-9]+]], %hi(word)
 ; O32-DAG:           lw $2, %lo(word)([[R1]])
 ; N32-DAG:           lui [[R1:\$[0-9]+]], %hi(word)
 ; N32-DAG:           lw $2, %lo(word)([[R1]])
-; N64-DAG:           ld  [[R1:\$[0-9]+]], %got_disp(word)(
-; N64-DAG:           lw $2, 0([[R1]])
+; N64-DAG:           lui [[R1:\$[0-9]+]], %highest(word)
+; N64-DAG:           lw $2, %lo(word)([[R1]])
 
 define i64 @reti64() nounwind {
 entry:
         %0 = load volatile i64, i64* @dword
         ret i64 %0
 }
 
 ; ALL-LABEL: reti64:
 ; On O32, we must use v0 and v1 for the return value
 ; O32-DAG:           lw $2, %lo(dword)([[R1:\$[0-9]+]])
 ; O32-DAG:           addiu [[R2:\$[0-9]+]], [[R1]], %lo(dword)
 ; O32-DAG:           lw $3, 4([[R2]])
 ; N32-DAG:           ld $2, %lo(dword)([[R1:\$[0-9]+]])
-; N64-DAG:           ld  [[R1:\$[0-9]+]], %got_disp(dword)([[R1:\$[0-9]+]])
-; N64-DAG:           ld $2, 0([[R1]])
+; N64-DAG:           lui  [[R1:\$[0-9]+]], %highest(dword)
+; N64-DAG:           ld $2, %lo(dword)([[R1]])

test/CodeGen/Mips/cconv/roundl-call.ll

 ; RUN: llc -march=mips64 -mcpu=mips64 -target-abi=n32 -relocation-model=pic < \
 ; RUN:     %s | FileCheck %s -check-prefixes=ALL,N32,HARD-FLOAT
 ; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n32 -relocation-model=pic < \
 ; RUN:     %s | FileCheck %s -check-prefixes=ALL,N32,HARD-FLOAT
 
 ; RUN: llc -march=mips64 -mcpu=mips64 -target-abi=n64 -relocation-model=pic < \
 ; RUN:     %s | FileCheck %s -check-prefixes=ALL,N64,HARD-FLOAT
-; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < \
-; RUN:     %s | FileCheck %s -check-prefixes=ALL,N64,HARD-FLOAT
+; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic \
+
+; RUN:     < %s | FileCheck %s -check-prefixes=ALL,N64,HARD-FLOAT
 
 ; RUN: llc -march=mips64 -mcpu=mips64 -mattr=+soft-float -target-abi=n32 \
 ; RUN:     -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,N32,SOFT-FLOAT
 ; RUN: llc -march=mips64el -mcpu=mips64 -mattr=+soft-float -target-abi=n32 \
 ; RUN:     -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,N32,SOFT-FLOAT
 
 ; RUN: llc -march=mips64 -mcpu=mips64 -mattr=+soft-float -target-abi=n64 < %s \
-; RUN: | FileCheck %s -check-prefixes=ALL,N64,SOFT-FLOAT
+; RUN:     -relocation-model=pic | FileCheck %s \
+; RUN:     -check-prefixes=ALL,N64,SOFT-FLOAT
 ; RUN: llc -march=mips64el -mcpu=mips64 -mattr=+soft-float -target-abi=n64 < \
-; RUN:     %s | FileCheck %s -check-prefixes=ALL,N64,SOFT-FLOAT
+; RUN:     %s -relocation-model=pic | FileCheck %s \
+; RUN:     -check-prefixes=ALL,N64,SOFT-FLOAT
 
 @fp128 = global fp128 zeroinitializer
 
 define void @roundl_call(fp128 %value) {
 entry:
 ; ALL-LABEL: roundl_call:
 ; N32:          lw      $25, %call16(roundl)($gp)
 ; N64:          ld      $25, %call16(roundl)($gp)

test/CodeGen/Mips/compactbranches/compact-branches-64.ll

-; RUN: llc -march=mipsel -mcpu=mips64r6 -disable-mips-delay-filler -target-abi=n64 < %s | FileCheck %s
+; RUN: llc -relocation-model=pic -march=mipsel -mcpu=mips64r6 \
+; RUN:     -disable-mips-delay-filler -target-abi=n64 < %s | FileCheck %s
 
 ; Function Attrs: nounwind
 define void @l() {
 entry:
 ; CHECK-LABEL:  l:
 ; CHECK: jalrc $25
   %call = tail call i64 @k()
 ; CHECK: jalrc $25

test/CodeGen/Mips/compactbranches/compact-branches.ll

-; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=static -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=STATIC32
-; RUN: llc -march=mipsel -mcpu=mips64r6 -target-abi n64 -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=PIC
+; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=static \
+; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=STATIC32
+; RUN: llc -march=mipsel -mcpu=mips64r6 -relocation-model=pic -target-abi n64 \
+; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=PIC
 
 ; Function Attrs: nounwind
 define void @l()  {
 entry:
 ; PIC: jalrc $25
   %call = tail call i32 @k()
 ; PIC: jalrc $25
   %call1 = tail call i32 @j()

test/CodeGen/Mips/cstmaterialization/stack.ll

 ; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefix=CHECK-MIPS32
-; RUN: llc -march=mips64el -mcpu=mips64 < %s | \
+; RUN: llc -march=mips64el -mcpu=mips64 -relocation-model=pic < %s | \
 ; RUN:      FileCheck %s -check-prefix=CHECK-MIPS64
 ; RUN: llc -march=mipsel -mcpu=mips64 -target-abi n32 < %s | \
 ; RUN:      FileCheck %s -check-prefix=CHECK-MIPSN32
 
 ; Test that the expansion of ADJCALLSTACKDOWN and ADJCALLSTACKUP generate
 ; (d)subu and (d)addu rather than just (d)addu. The (d)subu sequences are
 ; generally shorter as the constant that has to be materialized is smaller.
 

test/CodeGen/Mips/fcmp.ll

 ; 32-CMP-DAG:    lwc1     $[[T1:f[0-9]+]], %lo($CPI32_0)(
 ; 32-CMP-DAG:    cmp.le.s $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
 ; 32-CMP-DAG:    mfc1     $[[T3:[0-9]+]], $[[T2]]
 ; FIXME: This instruction is redundant.
 ; 32-CMP-DAG:    andi     $[[T4:[0-9]+]], $[[T3]], 1
 ; 32-CMP-DAG:    bnezc    $[[T4]],
 
 ; 64-C-DAG:      add.s    $[[T0:f[0-9]+]], $f13, $f12
-; 64-C-DAG:      lwc1     $[[T1:f[0-9]+]], %got_ofst(.LCPI32_0)(
+; 64-C-DAG:      lwc1     $[[T1:f[0-9]+]], %lo(.LCPI32_0)(
 ; 64-C-DAG:      c.ole.s  $[[T0]], $[[T1]]
 ; 64-C-DAG:      bc1t
 
 ; 64-CMP-DAG:    add.s    $[[T0:f[0-9]+]], $f13, $f12
-; 64-CMP-DAG:    lwc1     $[[T1:f[0-9]+]], %got_ofst(.LCPI32_0)(
+; 64-CMP-DAG:    lwc1     $[[T1:f[0-9]+]], %lo(.LCPI32_0)(
 ; 64-CMP-DAG:    cmp.le.s $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
 ; 64-CMP-DAG:    mfc1     $[[T3:[0-9]+]], $[[T2]]
 ; FIXME: This instruction is redundant.
 ; 64-CMP-DAG:    andi     $[[T4:[0-9]+]], $[[T3]], 1
 ; 64-CMP-DAG:    bnezc    $[[T4]],
 
 ; MM32R3-DAG:    add.s    $[[T0:f[0-9]+]], $f14, $f12
 ; MM32R3-DAG:    lui      $[[T1:[0-9]+]], %hi($CPI32_0)
 ; MM32R3-DAG:    lwc1     $[[T2:f[0-9]+]], %lo($CPI32_0)($[[T1]])
 ; MM32R3-DAG:    c.ole.s  $[[T0]], $[[T2]]
 ; MM32R3-DAG:    bc1t
 
 ; MM32R6-DAG:    add.s    $[[T0:f[0-9]+]], $f14, $f12
 ; MM32R6-DAG:    lui      $[[T1:[0-9]+]], %hi($CPI32_0)
 ; MM32R6-DAG:    lwc1     $[[T2:f[0-9]+]], %lo($CPI32_0)($[[T1]])
 ; MM32R6-DAG:    cmp.le.s $[[T3:f[0-9]+]], $[[T0]], $[[T2]]
 ; MM32R6-DAG:    mfc1     $[[T4:[0-9]+]], $[[T3:f[0-9]+]]
 ; MM32R6-DAG:    andi16   $[[T5:[0-9]+]], $[[T4]], 1
 ; MM32R6-DAG:    bnez     $[[T5]],
 
-; MM64R6-DAG:    lui      $[[T0:[0-9]+]], %hi(%neg(%gp_rel(bug1_f32)))
-; MM64R6-DAG:    daddu    $[[T1:[0-9]+]], $[[T0]], $25
-; MM64R6-DAG:    daddiu   $[[T2:[0-9]+]], $[[T1]], %lo(%neg(%gp_rel(bug1_f32)))
-; MM64R6-DAG:    add.s    $[[T3:f[0-9]+]], $f13, $f12
-; MM64R6-DAG:    ld       $[[T4:[0-9]+]], %got_page(.LCPI32_0)($[[T2]])
-; MM64R6-DAG:    lwc1     $[[T5:f[0-9]+]], %got_ofst(.LCPI32_0)($[[T4]])
-; MM64R6-DAG:    cmp.le.s $[[T6:f[0-9]+]], $[[T3]], $[[T5]]
-; MM64R6-DAG:    mfc1     $[[T7:[0-9]+]], $[[T6]]
-; MM64R6-DAG:    andi16   $[[T8:[0-9]+]], $[[T7]], 1
-; MM64R6-DAG:    bnez     $[[T8]],
+; MM64R6-DAG:    add.s    $[[T0:f[0-9]+]], $f13, $f12
+; MM64R6-DAG:    lui      $[[T1:[0-9]+]], %highest(.LCPI32_0)
+; MM64R6-DAG:    daddiu   $[[T2:[0-9]+]], $[[T1]], %higher(.LCPI32_0)
+; MM64R6-DAG:    dsll     $[[T3:[0-9]+]], $[[T2]], 16
+; MM64R6-DAG:    daddiu   $[[T4:[0-9]+]], $[[T3]], %hi(.LCPI32_0)
+; MM64R6-DAG:    dsll     $[[T5:[0-9]+]], $[[T4]], 16
+; MM64R6-DAG:    lwc1     $[[T6:f[0-9]+]], %lo(.LCPI32_0)($[[T5]])
+; MM64R6-DAG:    cmp.le.s $[[T7:f[0-9]+]], $[[T0]], $[[T6]]
+; MM64R6-DAG:    mfc1     $[[T8:[0-9]+]], $[[T7]]
+; MM64R6-DAG:    andi16   $[[T9:[0-9]+]], $[[T8]], 1
+; MM64R6-DAG:    bnez     $[[T9]],
 
   %add = fadd fast float %at, %angle
   %cmp = fcmp ogt float %add, 1.000000e+00
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:
   %sub = fadd fast float %add, -1.000000e+00
   br label %if.end

 ; 32-CMP-DAG:    ldc1     $[[T1:f[0-9]+]], %lo($CPI33_0)(
 ; 32-CMP-DAG:    cmp.le.d $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
 ; 32-CMP-DAG:    mfc1     $[[T3:[0-9]+]], $[[T2]]
 ; FIXME: This instruction is redundant.
 ; 32-CMP-DAG:    andi     $[[T4:[0-9]+]], $[[T3]], 1
 ; 32-CMP-DAG:    bnezc    $[[T4]],
 
 ; 64-C-DAG:      add.d    $[[T0:f[0-9]+]], $f13, $f12
-; 64-C-DAG:      ldc1     $[[T1:f[0-9]+]], %got_ofst(.LCPI33_0)(
+; 64-C-DAG:      ldc1     $[[T1:f[0-9]+]], %lo(.LCPI33_0)(
 ; 64-C-DAG:      c.ole.d  $[[T0]], $[[T1]]
 ; 64-C-DAG:      bc1t
 
 ; 64-CMP-DAG:    add.d    $[[T0:f[0-9]+]], $f13, $f12
-; 64-CMP-DAG:    ldc1     $[[T1:f[0-9]+]], %got_ofst(.LCPI33_0)(
+; 64-CMP-DAG:    ldc1     $[[T1:f[0-9]+]], %lo(.LCPI33_0)(
 ; 64-CMP-DAG:    cmp.le.d $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
 ; 64-CMP-DAG:    mfc1     $[[T3:[0-9]+]], $[[T2]]
 ; FIXME: This instruction is redundant.
 ; 64-CMP-DAG:    andi     $[[T4:[0-9]+]], $[[T3]], 1
 ; 64-CMP-DAG:    bnezc    $[[T4]],
 
 ; MM32R3-DAG:    add.d    $[[T0:f[0-9]+]], $f14, $f12
 ; MM32R3-DAG:    lui      $[[T1:[0-9]+]], %hi($CPI33_0)
 ; MM32R3-DAG:    ldc1     $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]])
 ; MM32R3-DAG:    c.ole.d  $[[T0]], $[[T2]]
 ; MM32R3-DAG:    bc1t
 
 ; MM32R6-DAG:    add.d    $[[T0:f[0-9]+]], $f14, $f12
 ; MM32R6-DAG:    lui      $[[T1:[0-9]+]], %hi($CPI33_0)
 ; MM32R6-DAG:    ldc1     $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]])
 ; MM32R6-DAG:    cmp.le.d $[[T3:f[0-9]+]], $[[T0]], $[[T2]]
 ; MM32R6-DAG:    mfc1     $[[T4:[0-9]+]], $[[T3]]
 ; MM32R6-DAG:    andi16   $[[T5:[0-9]+]], $[[T4]], 1
 ; MM32R6-DAG:    bnez     $[[T5]],
 
-; MM64R6-DAG:    lui      $[[T0:[0-9]+]], %hi(%neg(%gp_rel(bug1_f64)))
-; MM64R6-DAG:    daddu    $[[T1:[0-9]+]], $[[T0]], $25
-; MM64R6-DAG:    daddiu   $[[T2:[0-9]+]], $[[T1]], %lo(%neg(%gp_rel(bug1_f64)))
-; MM64R6-DAG:    add.d    $[[T3:f[0-9]+]], $f13, $f12
-; MM64R6-DAG:    ld       $[[T4:[0-9]+]], %got_page(.LCPI33_0)($[[T2]])
-; MM64R6-DAG:    ldc1     $[[T5:f[0-9]+]], %got_ofst(.LCPI33_0)($[[T4]])
-; MM64R6-DAG:    cmp.le.d $[[T6:f[0-9]+]], $[[T3]], $[[T5]]
-; MM64R6-DAG:    mfc1     $[[T7:[0-9]+]], $[[T6]]
-; MM64R6-DAG:    andi16   $[[T8:[0-9]+]], $[[T7]], 1
-; MM64R6-DAG:    bnez     $[[T8]],
+; MM64R6-DAG:    add.d    $[[T0:f[0-9]+]], $f13, $f12
+; MM64R6-DAG:    lui      $[[T1:[0-9]+]], %highest(.LCPI33_0)
+; MM64R6-DAG:    daddiu   $[[T2:[0-9]+]], $[[T1]], %higher(.LCPI33_0)
+; MM64R6-DAG:    dsll     $[[T3:[0-9]+]], $[[T2]], 16
+; MM64R6-DAG:    daddiu   $[[T4:[0-9]+]], $[[T3]], %hi(.LCPI33_0)
+; MM64R6-DAG:    dsll     $[[T5:[0-9]+]], $[[T4]], 16
+; MM64R6-DAG:    ldc1     $[[T6:f[0-9]+]], %lo(.LCPI33_0)($[[T5]])
+; MM64R6-DAG:    cmp.le.d $[[T7:f[0-9]+]], $[[T0]], $[[T6]]
+; MM64R6-DAG:    mfc1     $[[T8:[0-9]+]], $[[T7]]
+; MM64R6-DAG:    andi16   $[[T9:[0-9]+]], $[[T8]], 1
+; MM64R6-DAG:    bnez     $[[T9]],
 
   %add = fadd fast double %at, %angle
   %cmp = fcmp ogt double %add, 1.000000e+00
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:
   %sub = fadd fast double %add, -1.000000e+00
   br label %if.end
 
 if.end:
   %theta.0 = phi double [ %sub, %if.then ], [ %add, %entry ]
   ret double %theta.0
 }
 
 attributes #0 = { nounwind readnone "no-nans-fp-math"="true" }

test/CodeGen/Mips/fcopysign-f32-f64.ll

 }
 
 define double @func3(double %d, float %f) nounwind readnone {
 entry:
 ; ALL-LABEL: func3:
 
 ; 64-DAG: mfc1    $[[MFC:[0-9]+]], $f13
 ; 64-DAG: srl     $[[SRL:[0-9]+]], $[[MFC:[0-9]+]], 31
-; 64:     dsll    $[[DSLL:[0-9]+]], $[[SRL]], 63
 ; 64-DAG: daddiu  $[[R1:[0-9]+]], $zero, 1
+; 64:     dsll    $[[DSLL:[0-9]+]], $[[SRL]], 63
 ; 64-DAG: dsll    $[[R2:[0-9]+]], $[[R1]], 63
 ; 64-DAG: daddiu  $[[R3:[0-9]+]], $[[R2]], -1
 ; 64-DAG: dmfc1   $[[R0:[0-9]+]], ${{.*}}
 ; 64:     and     $[[AND0:[0-9]+]], $[[R0]], $[[R3]]
 ; 64:     or      $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]]
 ; 64:     dmtc1   $[[OR]], $f0
 
 ; 64R2: ext   ${{[0-9]+}}, ${{[0-9]+}}, 31, 1
 ; 64R2: dins  $[[INS:[0-9]+]], ${{[0-9]+}}, 63, 1
 ; 64R2: dmtc1 $[[INS]], $f0
 
   %add = fadd double %d, 1.000000e+00
   %conv = fpext float %f to double
   %call = tail call double @copysign(double %add, double %conv) nounwind readnone
   ret double %call
 }

test/CodeGen/Mips/global-address.ll

 ; STATIC-N32: lui $[[R1:[0-9]+]], %hi(s1)
 ; STATIC-N32: lw  ${{[0-9]+}}, %lo(s1)($[[R1]])
 ; STATIC-N32: lui $[[R2:[0-9]+]], %hi(g1)
 ; STATIC-N32: lw  ${{[0-9]+}}, %lo(g1)($[[R2]])
 
 ; PIC-N64: ld  $[[R0:[0-9]+]], %got_page(s1)
 ; PIC-N64: lw  ${{[0-9]+}}, %got_ofst(s1)($[[R0]])
 ; PIC-N64: ld  ${{[0-9]+}}, %got_disp(g1)
-; STATIC-N64: ld  $[[R1:[0-9]+]], %got_page(s1)
-; STATIC-N64: lw  ${{[0-9]+}}, %got_ofst(s1)($[[R1]])
-; STATIC-N64: ld  ${{[0-9]+}}, %got_disp(g1)
+; STATIC-N64: lui $[[R1:[0-9]+]], %highest(s1)
+; STATIC-N64: daddiu ${{[0-9]+}}, ${{[0-9]+}}, %higher(s1)
+; STATIC-N64: daddiu ${{[0-9]+}}, ${{[0-9]+}}, %hi(s1)
+; STATIC-N64: dsll $[[R2:[0-9]+]], $[[R1]], 16
+; STATIC-N64: lw  ${{[0-9]+}}, %lo(s1)($[[R2]])
+; STATIC-N64: lui $[[R3:[0-9]+]], %highest(g1)
+; STATIC-N64: daddiu $[[R3]], $[[R3]], %higher(g1)
+; STATIC-N64: daddiu $[[R3]], $[[R3]], %hi(g1)
+; STATIC-N64: lw  ${{[0-9]+}}, %lo(g1)($[[R3]])
 
   %0 = load i32, i32* @s1, align 4
   tail call void @foo1(i32 %0) nounwind
   %1 = load i32, i32* @g1, align 4
   store i32 %1, i32* @s1, align 4
   %add = add nsw i32 %1, 2
   store i32 %add, i32* @g1, align 4
   ret void
 }
 
 declare void @foo1(i32)
 

test/CodeGen/Mips/inlineasm-constraint_ZC_2.ll

 ; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s --check-prefixes=ALL,R6
-; RUN: llc -march=mips -mcpu=mips64r6 -target-abi=n64 < %s | FileCheck %s --check-prefixes=ALL,R6
+; RUN: llc -march=mips -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic \
+; RUN:     < %s | FileCheck %s --check-prefixes=ALL,R6
 ; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s --check-prefixes=ALL,PRER6
-; RUN: llc -march=mips -mcpu=mips64 -target-abi=n64 < %s | FileCheck %s --check-prefixes=ALL,PRER6
+; RUN: llc -march=mips -mcpu=mips64 -target-abi=n64 -relocation-model=pic \
+; RUN:     < %s | FileCheck %s --check-prefixes=ALL,PRER6
 
 
 %struct.anon = type { [63 x i32], i32, i32 }
 
 define i32 @Atomic() {
 ; CHECK-LABEL: Atomic:
 entry:
   %s = alloca %struct.anon, align 4

test/CodeGen/Mips/llvm-ir/call.ll

 ; Test the 'call' instruction and the tailcall variant.
 
 ; RUN: llc -march=mips   -mcpu=mips32   -relocation-model=pic  < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C
 ; RUN: llc -march=mips   -mcpu=mips32r2 -relocation-model=pic  < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C
 ; RUN: llc -march=mips   -mcpu=mips32r3 -relocation-model=pic  < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C
 ; RUN: llc -march=mips   -mcpu=mips32r5 -relocation-model=pic  < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C
 ; RUN: llc -march=mips   -mcpu=mips32r6 -relocation-model=pic -disable-mips-delay-filler  < %s | FileCheck %s -check-prefixes=ALL,O32,R6C
 ; RUN: llc -march=mips   -mcpu=mips32r6 -relocation-model=pic -mattr=+fp64,+nooddspreg -disable-mips-delay-filler  < %s | FileCheck %s -check-prefixes=ALL,O32,R6C
-; RUN: llc -march=mips64 -mcpu=mips4     < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
-; RUN: llc -march=mips64 -mcpu=mips64    < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
-; RUN: llc -march=mips64 -mcpu=mips64r2  < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
-; RUN: llc -march=mips64 -mcpu=mips64r3  < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
-; RUN: llc -march=mips64 -mcpu=mips64r5  < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
-; RUN: llc -march=mips64 -mcpu=mips64r6 -disable-mips-delay-filler  < %s | FileCheck %s -check-prefixes=ALL,N64,R6C
+; RUN: llc -march=mips64 -mcpu=mips4    -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64   -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64r2 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64r3 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64r5 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64r6 -relocation-model=pic -disable-mips-delay-filler  < %s | FileCheck %s -check-prefixes=ALL,N64,R6C
 ; RUN: llc -march=mips   -mcpu=mips32   -relocation-model=pic  < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
 ; RUN: llc -march=mips   -mcpu=mips32r2 -relocation-model=pic  < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
 ; RUN: llc -march=mips   -mcpu=mips32r3 -relocation-model=pic  < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
 ; RUN: llc -march=mips   -mcpu=mips32r5 -relocation-model=pic  < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
 ; RUN: llc -march=mips   -mcpu=mips32r6 -relocation-model=pic -disable-mips-delay-filler  < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=R6C
 ; RUN: llc -march=mips   -mcpu=mips32r6 -relocation-model=pic -mattr=+fp64,+nooddspreg -disable-mips-delay-filler  < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=R6C
-; RUN: llc -march=mips64 -mcpu=mips4     < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
-; RUN: llc -march=mips64 -mcpu=mips64    < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
-; RUN: llc -march=mips64 -mcpu=mips64r2  < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
-; RUN: llc -march=mips64 -mcpu=mips64r3  < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
-; RUN: llc -march=mips64 -mcpu=mips64r5  < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
-; RUN: llc -march=mips64 -mcpu=mips64r6 -disable-mips-delay-filler  < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=R6C
+; RUN: llc -march=mips64 -mcpu=mips4    -relocation-model=pic < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64   -relocation-model=pic < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64r2 -relocation-model=pic < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64r3 -relocation-model=pic < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64r5 -relocation-model=pic < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64r6 -relocation-model=pic -disable-mips-delay-filler  < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=R6C
 
 declare void @extern_void_void()
 declare i32 @extern_i32_void()
 declare float @extern_float_void()
 
 define i32 @call_void_void() {
 ; ALL-LABEL: call_void_void:
 

test/CodeGen/Mips/mips64-f128-call.ll

 ; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s
 
 @gld0 = external global fp128
 @gld1 = external global fp128
 
 ; CHECK: foo0
+; CHECK: sdc1  $f12, %lo(gld0)(${{[0-9]+}})
 ; CHECK: sdc1  $f13, 8(${{[0-9]+}})
-; CHECK: sdc1  $f12, 0(${{[0-9]+}})
 
 define void @foo0(fp128 %a0) {
 entry:
   store fp128 %a0, fp128* @gld0, align 16
   ret void
 }
 
 ; CHECK: foo1
+; CHECK: ldc1  $f12, %lo(gld0)(${{[0-9]+}})
 ; CHECK: ldc1  $f13, 8(${{[0-9]+}})
-; CHECK: ldc1  $f12, 0(${{[0-9]+}})
 
 define void @foo1() {
 entry:
   %0 = load fp128, fp128* @gld0, align 16
   tail call void @foo2(fp128 %0)
   ret void
 }
 
 declare void @foo2(fp128)
 
-; CHECK: foo3
-; CHECK: ld   $[[R0:[0-9]+]], %got_disp(gld0)
-; CHECK: sdc1 $f2, 8($[[R0]])
-; CHECK: sdc1 $f0, 0($[[R0]])
-; CHECK: ld   $[[R1:[0-9]+]], %got_disp(gld1)
-; CHECK: ldc1 $f0, 0($[[R1]])
-; CHECK: ldc1 $f2, 8($[[R1]])
+; CHECK: foo3:
+; CHECK: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %hi(gld0)
+; CHECK: dsll $[[R1:[0-9]+]], $[[R0]], 16
+; CHECK: sdc1 $f0, %lo(gld0)($[[R1]])
+; CHECK: daddiu $[[R2:[0-9]]], $[[R1]], %lo(gld0)
+; CHECK: sdc1 $f2, 8($[[R2]])
+; CHECK: daddiu $[[R3:[0-9]+]], ${{[0-9]+}}, %hi(gld1)
+; CHECK: dsll $[[R4:[0-9]+]], $[[R3]], 16
+; CHECK: ldc1 $f0, %lo(gld1)($[[R4]])
+; CHECK: daddiu $[[R5:[0-9]]], $[[R4]], %lo(gld1)
+; CHECK: ldc1 $f2, 8($[[R5]])
+
+
 
 define fp128 @foo3() {
 entry:
   %call = tail call fp128 @foo4()
   store fp128 %call, fp128* @gld0, align 16
   %0 = load fp128, fp128* @gld1, align 16
   ret fp128 %0
 }
 
 declare fp128 @foo4()

test/CodeGen/Mips/mips64-f128.ll

 ; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips4 -mattr=+soft-float -O1 \
-; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,C_CC_FMT,PRER6
+; RUN:     -disable-mips-delay-filler -relocation-model=pic < %s | FileCheck \
+; RUN:     %s -check-prefixes=ALL,C_CC_FMT,PRER6
 ; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64 -mattr=+soft-float -O1 \
-; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,C_CC_FMT,PRER6
-; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64r2 -mattr=+soft-float -O1 \
-; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,C_CC_FMT,PRER6
-; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64r6 -mattr=+soft-float -O1 \
-; RUN:     -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,CMP_CC_FMT,R6
+; RUN:     -disable-mips-delay-filler -relocation-model=pic < %s | FileCheck \
+; RUN:     %s -check-prefixes=ALL,C_CC_FMT,PRER6
+; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64r2 -mattr=+soft-float \
+; RUN:     -O1 -disable-mips-delay-filler -relocation-model=pic < %s | FileCheck \
+; RUN:     %s -check-prefixes=ALL,C_CC_FMT,PRER6
+; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64r6 -mattr=+soft-float \
+; RUN:     -O1 -disable-mips-delay-filler -relocation-model=pic < %s | FileCheck \
+; RUN:     %s -check-prefixes=ALL,CMP_CC_FMT,R6
 
 @gld0 = external global fp128
 @gld1 = external global fp128
 @gld2 = external global fp128
 @gf1 = external global float
 @gd1 = external global double
 
 ; ALL-LABEL: addLD:

test/CodeGen/Mips/mips64-libcall.ll

entry:
   ret double %call
 }
 
 declare double @floor(double) nounwind readnone
 
 ; Check call16.
 ;
 ; SOFT-LABEL: f64add:
-; SOFT: ld $25, %call16(__adddf3)
+; SOFT: jal __adddf3
 
 define double @f64add(double %a, double %b) {
 entry:
   %add = fadd double %a, %b
   ret double %add
 }

test/CodeGen/Mips/mips64instrs.ll

; GPRMULDIV:     dmul $2, ${{[45]}}, ${{[45]}}
 
   %mul = mul i64 %b, %a
   ret i64 %mul
 }
 
 define i64 @f14(i64 %a, i64 %b) nounwind readnone {
 entry:
 ; ALL-LABEL: f14:
-; ALL-DAG:       ld $[[P0:[0-9]+]], %got_disp(gll0)(
-; ALL-DAG:       ld $[[P1:[0-9]+]], %got_disp(gll1)(
-; ALL-DAG:       ld $[[T0:[0-9]+]], 0($[[P0]])
-; ALL-DAG:       ld $[[T1:[0-9]+]], 0($[[P1]])
+; ALL-DAG:       ld $[[T0:[0-9]+]], %lo(gll0)(${{[0-9]+}})
+; ALL-DAG:       ld $[[T1:[0-9]+]], %lo(gll1)(${{[0-9]+}})
 
 ; ACCMULDIV:     ddiv $zero, $[[T0]], $[[T1]]
 ; ACCMULDIV:     teq $[[T1]], $zero, 7
 ; ACCMULDIV:     mflo $2
 
 ; GPRMULDIV:     ddiv $2, $[[T0]], $[[T1]]
 ; GPRMULDIV:     teq $[[T1]], $zero, 7
 
   %0 = load i64, i64* @gll0, align 8
   %1 = load i64, i64* @gll1, align 8
   %div = sdiv i64 %0, %1
   ret i64 %div
 }
 
 define i64 @f15() nounwind readnone {
 entry:
 ; ALL-LABEL: f15:
-; ALL-DAG:       ld $[[P0:[0-9]+]], %got_disp(gll0)(
-; ALL-DAG:       ld $[[P1:[0-9]+]], %got_disp(gll1)(
-; ALL-DAG:       ld $[[T0:[0-9]+]], 0($[[P0]])
-; ALL-DAG:       ld $[[T1:[0-9]+]], 0($[[P1]])
+; ALL-DAG:       ld $[[T0:[0-9]+]], %lo(gll0)(${{[0-9]+}})
+; ALL-DAG:       ld $[[T1:[0-9]+]], %lo(gll1)(${{[0-9]+}})
 
 ; ACCMULDIV:     ddivu $zero, $[[T0]], $[[T1]]
 ; ACCMULDIV:     teq $[[T1]], $zero, 7
 ; ACCMULDIV:     mflo $2
 
 ; GPRMULDIV:     ddivu $2, $[[T0]], $[[T1]]
 ; GPRMULDIV:     teq $[[T1]], $zero, 7
 

test/CodeGen/Mips/tailcall/tailcall.ll

 ; RUN: llc -march=mipsel -relocation-model=pic  \
 ; RUN:     -verify-machineinstrs < %s | FileCheck %s -check-prefix=PIC32
 ; RUN: llc -march=mipsel -relocation-model=static  \
 ; RUN:     -verify-machineinstrs < %s | FileCheck %s -check-prefix=STATIC32
-; RUN: llc -march=mips64el -mcpu=mips64r2  \
-; RUN:     -verify-machineinstrs < %s | FileCheck %s -check-prefix=N64
+
+; RUN: llc -march=mips64el -mcpu=mips64r2 -relocation-model=pic \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s -check-prefix=PIC64
+
+; RUN: llc -march=mips64el -mcpu=mips64r2 -relocation-model=static \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s -check-prefix=STATIC64
+
+
 ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic \
 ; RUN:      -verify-machineinstrs < %s | \
 ; RUN:     FileCheck %s -check-prefix=PIC16
 
 ; RUN: llc -march=mipsel -relocation-model=pic -mattr=+micromips < %s | \
 ; RUN:     FileCheck %s -check-prefix=PIC32
 ; RUN: llc -march=mipsel -relocation-model=static -mattr=+micromips \
 ; RUN:     < %s | FileCheck %s -check-prefix=STATIC32
 
 ; RUN: llc -march=mipsel -relocation-model=pic -mcpu=mips32r6 < %s | \
 ; RUN:     FileCheck %s -check-prefix=PIC32
 ; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r6 \
 ; RUN:     < %s | FileCheck %s -check-prefix=STATIC32
-; RUN: llc -march=mips64el -mcpu=mips64r6  \
-; RUN:     < %s | FileCheck %s -check-prefix=N64
+; RUN: llc -march=mips64el -mcpu=mips64r6 -relocation-model=static \
+; RUN:     < %s | FileCheck %s -check-prefix=STATIC64
+; RUN: llc -march=mips64el -mcpu=mips64r6 -relocation-model=pic \
+; RUN:     < %s | FileCheck %s -check-prefix=PIC64
+
 
 ; RUN: llc -march=mipsel -relocation-model=pic -mcpu=mips32r6 -mattr=+micromips \
 ; RUN:      < %s | FileCheck %s -check-prefix=PIC32
 ; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r6 \
 ; RUN:     -mattr=+micromips < %s | FileCheck %s -check-prefix=STATIC32
-; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=+micromips < %s \
-; RUN:      | FileCheck %s -check-prefix=N64
+; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=+micromips \
+; RUN:     -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC64
+; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=+micromips \
+; RUN:     -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC64
+
+
 
 @g0 = common global i32 0, align 4
 @g1 = common global i32 0, align 4
 @g2 = common global i32 0, align 4
 @g3 = common global i32 0, align 4
 @g4 = common global i32 0, align 4
 @g5 = common global i32 0, align 4
 @g6 = common global i32 0, align 4
 @g7 = common global i32 0, align 4
 @g8 = common global i32 0, align 4
 @g9 = common global i32 0, align 4
 
 define i32 @caller1(i32 %a0) nounwind {
 entry:
 ; PIC32-NOT: jalr
 ; STATIC32-NOT: jal
-; N64-NOT: jalr
+; PIC64: jr
+; STATIC64: j
 ; PIC16: jalrc
 
   %call = tail call i32 @callee1(i32 1, i32 1, i32 1, i32 %a0) nounwind
   ret i32 %call
 }
 
 declare i32 @callee1(i32, i32, i32, i32)
 
 define i32 @caller2(i32 %a0, i32 %a1, i32 %a2, i32 %a3) nounwind {
 entry:
 ; PIC32: jalr
 ; STATIC32: jal
-; N64-NOT: jalr
+; PIC64: j
+; STATIC64: j
 ; PIC16: jalrc
 
   %call = tail call i32 @callee2(i32 1, i32 %a0, i32 %a1, i32 %a2, i32 %a3) nounwind
   ret i32 %call
 }
 
 declare i32 @callee2(i32, i32, i32, i32, i32)
 
 define i32 @caller3(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4) nounwind {
 entry:
 ; PIC32: jalr
 ; STATIC32: jal
-; N64-NOT: jalr
+; PIC64: jr
+; STATIC64: j
 ; PIC16: jalrc
 
   %call = tail call i32 @callee3(i32 1, i32 1, i32 1, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4) nounwind
   ret i32 %call
 }
 
 declare i32 @callee3(i32, i32, i32, i32, i32, i32, i32, i32)
 
 define i32 @caller4(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7) nounwind {
 entry:
 ; PIC32: jalr
 ; STATIC32: jal
-; N64: jalr
+; PIC64: jalr
+; STATIC64: jal
 ; PIC16: jalrc
 
   %call = tail call i32 @callee4(i32 1, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7) nounwind
   ret i32 %call
 }
 
 declare i32 @callee4(i32, i32, i32, i32, i32, i32, i32, i32, i32)
 
 define i32 @caller5() nounwind readonly {
 entry:
 ; PIC32: .ent caller5
 ; PIC32-NOT: jalr $25
 ; PIC32: .end caller5
 ; STATIC32: .ent caller5
 ; STATIC32-NOT: jal
 ; STATIC32: .end caller5
-; N64: .ent caller5
-; N64-NOT: jalr $25
-; N64: .end caller5
+; PIC64: .ent caller5
+; PIC64: jr $25
+; PIC64: .end caller5
+; STATIC64: .ent caller5
+; STATIC64: j
+; STATIC64: .end caller5
 ; PIC16: .ent caller5
 ; PIC16: jalrc
 ; PIC16: .end caller5
 
   %0 = load i32, i32* @g0, align 4
   %1 = load i32, i32* @g1, align 4
   %2 = load i32, i32* @g2, align 4
   %3 = load i32, i32* @g3, align 4

 define i32 @caller8_0() nounwind {
 entry:
 ; PIC32: .ent caller8_0
 ; PIC32: jr
 ; PIC32: .end caller8_0
 ; STATIC32: .ent caller8_0
 ; STATIC32: j
 ; STATIC32: .end caller8_0
-; N64: .ent caller8_0
-; N64-NOT: jalr $25
-; N64: .end caller8_0
+; PIC64: .ent caller8_0
+; PIC64: jr
+; PIC64: .end caller8_0
+; STATIC64: .ent caller8_0
+; STATIC64: j
+; STATIC64: .end caller8_0
 ; PIC16: .ent caller8_0
 ; PIC16: jalrc
 ; PIC16: .end caller8_0
 
   %call = tail call fastcc i32 @caller8_1()
   ret i32 %call
 }
 
 define internal fastcc i32 @caller8_1() nounwind noinline {
 entry:
 ; PIC32: .ent caller8_1
 ; PIC32: jalr
 ; PIC32: .end caller8_1
 ; STATIC32: .ent caller8_1
 ; STATIC32: jal
 ; STATIC32: .end caller8_1
-; N64: .ent caller8_1
-; N64-NOT: jalr $25
-; N64: .end caller8_1
+; PIC64: .ent caller8_1
+; PIC64: jr $25
+; PIC64: .end caller8_1
+; STATIC64: .ent caller8_1
+; STATIC64: j
+; STATIC64: .end caller8_1
 ; PIC16: .ent caller8_1
 ; PIC16: jalrc
 ; PIC16: .end caller8_1
 
   %call = tail call i32 (i32, ...) @callee8(i32 2, i32 1) nounwind
   ret i32 %call
 }
 
 %struct.S = type { [2 x i32] }
 
 @gs1 = external global %struct.S
 
 declare i32 @callee9(%struct.S* byval)
 
 define i32 @caller9_0() nounwind {
 entry:
 ; PIC32: .ent caller9_0
 ; PIC32: jr
 ; PIC32: .end caller9_0
 ; STATIC32: .ent caller9_0
 ; STATIC32: j
 ; STATIC32: .end caller9_0
-; N64: .ent caller9_0
-; N64-NOT: jalr $25
-; N64: .end caller9_0
+; PIC64: .ent caller9_0
+; PIC64: jr
+; PIC64: .end caller9_0
+; STATIC64: .ent caller9_0
+; STATIC64: j
+; STATIC64: .end caller9_0
 ; PIC16: .ent caller9_0
 ; PIC16: jalrc
 ; PIC16: .end caller9_0
   %call = tail call fastcc i32 @caller9_1()
   ret i32 %call
 }
 
 define internal fastcc i32 @caller9_1() nounwind noinline {
 entry:
 ; PIC32: .ent caller9_1
 ; PIC32: jalr
 ; PIC32: .end caller9_1
 ; STATIC32: .ent caller9_1
 ; STATIC32: jal
 ; STATIC32: .end caller9_1
-; N64: .ent caller9_1
-; N64: jalr
-; N64: .end caller9_1
+; PIC64: .ent caller9_1
+; PIC64: jalr
+; PIC64: .end caller9_1
+; STATIC64: .ent caller9_1
+; STATIC64: jal
+; STATIC64: .end caller9_1
 ; PIC16: .ent caller9_1
 ; PIC16: jalrc
 ; PIC16: .end caller9_1
 
   %call = tail call i32 @callee9(%struct.S* byval @gs1) nounwind
   ret i32 %call
 }
 
 declare i32 @callee10(i32, i32, i32, i32, i32, i32, i32, i32, i32)
 
 define i32 @caller10(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8) nounwind {
 entry:
 ; PIC32: .ent caller10
 ; PIC32-NOT: jalr $25
 ; STATIC32: .ent caller10
 ; STATIC32-NOT: jal
-; N64: .ent caller10
-; N64-NOT: jalr $25
+; PIC64: .ent caller10
+; PIC64: jr
+; STATIC64: .ent caller10
+; STATIC64: j
 ; PIC16: .ent caller10
 ; PIC16: jalrc
 
   %call = tail call i32 @callee10(i32 %a8, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7) nounwind
   ret i32 %call
 }
 
 declare i32 @callee11(%struct.S* byval)
 
 define i32 @caller11() nounwind noinline {
 entry:
 ; PIC32: .ent caller11
 ; PIC32: jalr
 ; STATIC32: .ent caller11
 ; STATIC32: jal
-; N64: .ent caller11
-; N64: jalr
+; PIC64: .ent caller11
+; PIC64: jalr
+; STATIC64: .ent caller11
+; STATIC64: jal
 ; PIC16: .ent caller11
 ; PIC16: jalrc
 
   %call = tail call i32 @callee11(%struct.S* byval @gs1) nounwind
   ret i32 %call
 }
 
 declare i32 @callee12()
 
 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
 
 define i32 @caller12(%struct.S* nocapture byval %a0) nounwind {
 entry:
 ; PIC32: .ent caller12
 ; PIC32: jalr
 ; STATIC32: .ent caller12
 ; STATIC32: jal
-; N64: .ent caller12
-; N64: jalr
+; PIC64: .ent caller12
+; PIC64: jalr
+; STATIC64: .ent caller12
+; STATIC64: jal
 ; PIC16: .ent caller12
 ; PIC16: jalrc
 
   %0 = bitcast %struct.S* %a0 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* bitcast (%struct.S* @gs1 to i8*), i8* %0, i32 8, i32 4, i1 false)
   %call = tail call i32 @callee12() nounwind
   ret i32 %call
 }
 
 declare i32 @callee13(i32, ...)
 
 define i32 @caller13() nounwind {
 entry:
 ; PIC32: .ent caller13
 ; PIC32-NOT: jalr
 ; STATIC32: .ent caller13
 ; STATIC32-NOT: jal
-; N64: .ent caller13
-; N64-NOT: jalr $25
+; PIC64: .ent caller13
+; PIC64: jr $25
+; STATIC64: .ent caller13
+; STATIC64: j
 ; PIC16: .ent caller13
 ; PIC16: jalrc
 
   %call = tail call i32 (i32, ...) @callee13(i32 1, i32 2) nounwind
   ret i32 %call
 }
 
 ; Check that there is a chain edge between the load and store nodes.