[x86] Refactor a PowerPC specific ctlz/srl transformation (NFC).

[pgousseau]

Summary

Following the discussion on D22038, this refactors a PowerPC specific setcc -> srl(ctlz) transformation so it can be used by other targets.

[hfinkel]

include/llvm/Target/TargetLowering.h

3061 ↗

(On Diff #67823)

Please add a comment here explaining what this function does, including its relationship to isCtlzFast.

[spatel]

include/llvm/Target/TargetLowering.h

3061 ↗

(On Diff #67823)

A better name might also help: lowerCmpEqZeroToCtlzSrl() ?

[pgousseau]

Renaming method and adding comment following Hal and Sanjay comments.

[spatel]

Just a couple of nits, otherwise LGTM.
But please wait for Hal's feedback on the requested function comment.

lib/CodeGen/SelectionDAG/TargetLowering.cpp

3566–3567 ↗

(On Diff #67855)

Indentation looks wrong - use clang-format.
Also, I know it's a giant mess, but I assume that we should use the current naming convention when creating a new function, so "Lower" -> "lower".

3572 ↗

(On Diff #67855)

I think it's ok for this patch to be a cut-and-paste and NFC, but a couple of possible improvements for a follow-up:

1. Sink 'dl' below the first two 'if' statements.
2. Do we need to use a target-specific type rather than hard-coding MVT::i32 under this?

[pgousseau]

lib/CodeGen/SelectionDAG/TargetLowering.cpp

3572 ↗

(On Diff #67855)

Sounds good, only I am not sure I understand point 2, are you suggesting to pass the value type as a parameter to this new method?

[spatel]

lib/CodeGen/SelectionDAG/TargetLowering.cpp

3572 ↗

(On Diff #67855)

Sorry, I hadn't looked at D23446 when I made this comment. I see that adds a param for 'ExtTy'. I was also wondering what would happen if a target, for example, only had ctlz for a 64-bit type (or it might only have it for a smaller type than i32). I think some more customization would be needed.

But to keep it simple, we don't need to deal with any of that in this patch.

[hfinkel]

include/llvm/Target/TargetLowering.h

3063 ↗

(On Diff #67855)

I think it would be clearer if you include in the comment the form of the transform; something like:

// seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))

[pgousseau]

clang-format and fix method name following Sanjay's comments.

[pgousseau]

Add form of the transform in the comment following Hal's comment.

[hfinkel]

In D23445#516316, @pgousseau wrote:

Add form of the transform in the comment following Hal's comment.

LGTM, thanks.

llvm/trunk/include/llvm/Target/TargetLowering.h

virtual bool isCheapToSpeculateCttz() const {
     return false;
   }
 
   /// \brief Return true if it is cheap to speculate a call to intrinsic ctlz.
   virtual bool isCheapToSpeculateCtlz() const {
     return false;
   }
 
+  /// \brief Return true if ctlz instruction is fast.
+  virtual bool isCtlzFast() const {
+    return false;
+  }
+
   /// Return true if it is safe to transform an integer-domain bitwise operation
   /// into the equivalent floating-point operation. This should be set to true
   /// if the target has IEEE-754-compliant fabs/fneg operations for the input
   /// type.
   virtual bool hasBitPreservingFPLogic(EVT VT) const {
     return false;
   }
 
public:
   virtual bool useLoadStackGuardNode() const {
     return false;
   }
 
   /// Lower TLS global address SDNode for target independent emulated TLS model.
   virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
                                           SelectionDAG &DAG) const;
 
+  // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
+  // If we're comparing for equality to zero and isCtlzFast is true, expose the
+  // fact that this can be implemented as a ctlz/srl pair, so that the dag
+  // combiner can fold the new nodes.
+  SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
+
 private:
   SDValue simplifySetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
                                ISD::CondCode Cond, DAGCombinerInfo &DCI,
                                const SDLoc &DL) const;
 };
 
 /// Given an LLVM IR type and return type attributes, compute the return value
 /// EVTs and flags, and optionally also the offsets, if the return value is
 /// being lowered to memory.
 void GetReturnInfo(Type *ReturnType, AttributeSet attr,
                    SmallVectorImpl<ISD::OutputArg> &Outs,
                    const TargetLowering &TLI, const DataLayout &DL);
 
 } // end llvm namespace
 
 #endif

llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp

SDValue TargetLowering::LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
   MFI.setAdjustsStack(true);  // Is this only for X86 target?
   MFI.setHasCalls(true);
 
   assert((GA->getOffset() == 0) &&
          "Emulated TLS must have zero offset in GlobalAddressSDNode");
   return CallResult.first;
 }
+
+SDValue TargetLowering::lowerCmpEqZeroToCtlzSrl(SDValue Op,
+                                                SelectionDAG &DAG) const {
+  assert((Op->getOpcode() == ISD::SETCC) && "Input has to be a SETCC node.");
+  if (!isCtlzFast())
+    return SDValue();
+  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
+  SDLoc dl(Op);
+  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+    if (C->isNullValue() && CC == ISD::SETEQ) {
+      EVT VT = Op.getOperand(0).getValueType();
+      SDValue Zext = Op.getOperand(0);
+      if (VT.bitsLT(MVT::i32)) {
+        VT = MVT::i32;
+        Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
+      }
+      unsigned Log2b = Log2_32(VT.getSizeInBits());
+      SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
+      SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
+                                DAG.getConstant(Log2b, dl, MVT::i32));
+      return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
+    }
+  }
+  return SDValue();
+}

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h

public:
     bool isCheapToSpeculateCttz() const override {
       return true;
     }
 
     bool isCheapToSpeculateCtlz() const override {
       return true;
     }
 
+    bool isCtlzFast() const override {
+      return true;
+    }
+
     bool supportSplitCSR(MachineFunction *MF) const override {
       return
         MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
         MF->getFunction()->hasFnAttribute(Attribute::NoUnwind);
     }
 
     void initializeSplitCSR(MachineBasicBlock *Entry) const override;
 

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

if (Op.getValueType() == MVT::v2i64) {
 
     // We handle most of these in the usual way.
     return Op;
   }
 
   // If we're comparing for equality to zero, expose the fact that this is
   // implemented as a ctlz/srl pair on ppc, so that the dag combiner can
   // fold the new nodes.
+  if (SDValue V = lowerCmpEqZeroToCtlzSrl(Op, DAG))
+    return V;
+
   if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
-    if (C->isNullValue() && CC == ISD::SETEQ) {
-      EVT VT = Op.getOperand(0).getValueType();
-      SDValue Zext = Op.getOperand(0);
-      if (VT.bitsLT(MVT::i32)) {
-        VT = MVT::i32;
-        Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
-      }
-      unsigned Log2b = Log2_32(VT.getSizeInBits());
-      SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
-      SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
-                                DAG.getConstant(Log2b, dl, MVT::i32));
-      return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
-    }
     // Leave comparisons against 0 and -1 alone for now, since they're usually
     // optimized.  FIXME: revisit this when we can custom lower all setcc
     // optimizations.
     if (C->isAllOnesValue() || C->isNullValue())
       return SDValue();
   }
 
   // If we have an integer seteq/setne, turn it into a compare against zero