MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.

[MatzeB]

Summary

Specifying isSSA is an extra line at best and results in invalid MI at
worst. Compute the value instead.

[MatzeB]

Fix some bugs in the patch.

[kparzysz]

lib/CodeGen/MIRParser/MIRParser.cpp

303 ↗

(On Diff #65213)

This check is insufficient. The def must dominate all uses. It is possible to have a non-SSA program where all registers have single definitions, but where a use is not dominated by the def.

[MatzeB]

lib/CodeGen/MIRParser/MIRParser.cpp

303 ↗

(On Diff #65213)

While true in general, in llvm machine functions we can never have a virtual register use without any dominating definition (you need to place an IMPLICIT_DEF if you do not have a real definition).
I don't think we need to cater for malformed .mir here. The MachineVerifier step performed after reading should catch that case.

[qcolombet]

LGTM

llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h

struct MachineFunction {
   bool HasInlineAsm = false;
   // MachineFunctionProperties
   bool AllVRegsAllocated = false;
   // GISel MachineFunctionProperties.
   bool Legalized = false;
   bool RegBankSelected = false;
   bool Selected = false;
   // Register information
-  bool IsSSA = false;
   bool TracksRegLiveness = false;
   bool TracksSubRegLiveness = false;
   std::vector<VirtualRegisterDefinition> VirtualRegisters;
   std::vector<MachineFunctionLiveIn> LiveIns;
   Optional<std::vector<FlowStringValue>> CalleeSavedRegisters;
   // TODO: Serialize the various register masks.
   // Frame information
   MachineFrameInfo FrameInfo;
static void mapping(IO &YamlIO, MachineFunction &MF) {
     YamlIO.mapRequired("name", MF.Name);
     YamlIO.mapOptional("alignment", MF.Alignment);
     YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice);
     YamlIO.mapOptional("hasInlineAsm", MF.HasInlineAsm);
     YamlIO.mapOptional("allVRegsAllocated", MF.AllVRegsAllocated);
     YamlIO.mapOptional("legalized", MF.Legalized);
     YamlIO.mapOptional("regBankSelected", MF.RegBankSelected);
     YamlIO.mapOptional("selected", MF.Selected);
-    YamlIO.mapOptional("isSSA", MF.IsSSA);
     YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);
     YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness);
     YamlIO.mapOptional("registers", MF.VirtualRegisters);
     YamlIO.mapOptional("liveins", MF.LiveIns);
     YamlIO.mapOptional("calleeSavedRegisters", MF.CalleeSavedRegisters);
     YamlIO.mapOptional("frameInfo", MF.FrameInfo);
     YamlIO.mapOptional("fixedStack", MF.FixedStackObjects);
     YamlIO.mapOptional("stack", MF.StackObjects);

llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp

 static bool hasPHI(const MachineFunction &MF) {
   for (const MachineBasicBlock &MBB : MF)
     for (const MachineInstr &MI : MBB)
       if (MI.isPHI())
         return true;
   return false;
 }
 
+static bool isSSA(const MachineFunction &MF) {
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
+  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
+    unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
+    if (!MRI.hasOneDef(Reg) && !MRI.def_empty(Reg))
+      return false;
+  }
+  return true;
+}
+
 void MIRParserImpl::computeFunctionProperties(MachineFunction &MF) {
+  MachineFunctionProperties &Properties = MF.getProperties();
   if (!hasPHI(MF))
-    MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);
+    Properties.set(MachineFunctionProperties::Property::NoPHIs);
+
+  if (isSSA(MF))
+    Properties.set(MachineFunctionProperties::Property::IsSSA);
+  else
+    Properties.clear(MachineFunctionProperties::Property::IsSSA);
 }
 
 bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
   auto It = Functions.find(MF.getName());
   if (It == Functions.end())
     return error(Twine("no machine function information for function '") +
                  MF.getName() + "' in the MIR file");
   // TODO: Recreate the machine function.
bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
   MF.verify();
   return false;
 }
 
 bool MIRParserImpl::initializeRegisterInfo(PerFunctionMIParsingState &PFS,
     const yaml::MachineFunction &YamlMF) {
   MachineFunction &MF = PFS.MF;
   MachineRegisterInfo &RegInfo = MF.getRegInfo();
-  assert(RegInfo.isSSA());
-  if (!YamlMF.IsSSA)
-    RegInfo.leaveSSA();
   assert(RegInfo.tracksLiveness());
   if (!YamlMF.TracksRegLiveness)
     RegInfo.invalidateLiveness();
   RegInfo.enableSubRegLiveness(YamlMF.TracksSubRegLiveness);
 
   SMDiagnostic Error;
   // Parse the virtual register information.
   for (const auto &VReg : YamlMF.VirtualRegisters) {

llvm/trunk/lib/CodeGen/MIRPrinter.cpp

void MIRPrinter::print(const MachineFunction &MF) {
   StrOS.flush();
   yaml::Output Out(OS);
   Out << YamlMF;
 }
 
 void MIRPrinter::convert(yaml::MachineFunction &MF,
                          const MachineRegisterInfo &RegInfo,
                          const TargetRegisterInfo *TRI) {
-  MF.IsSSA = RegInfo.isSSA();
   MF.TracksRegLiveness = RegInfo.tracksLiveness();
   MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
 
   // Print the virtual register definitions.
   for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
     unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
     yaml::VirtualRegisterDefinition VReg;
     VReg.ID = I;

llvm/trunk/lib/CodeGen/MachineVerifier.cpp

if (*i == b)
     return *++i == a;
   return false;
 }
 
 void
 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
   FirstTerminator = nullptr;
 
-  if (MRI->isSSA()) {
+  if (!MF->getProperties().hasProperty(
+      MachineFunctionProperties::Property::NoPHIs)) {
     // If this block has allocatable physical registers live-in, check that
     // it is an entry block or landing pad.
     for (const auto &LI : MBB->liveins()) {
       if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() &&
           MBB->getIterator() != MBB->getParent()->begin()) {
         report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB);
       }
     }

llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir

 
 ...
 
 ---
 # Check that we select a 32-bit GPR G_ADD into ADDWrr on GPR32.
 # Also check that we constrain the register class of the COPY to GPR32.
 # CHECK-LABEL: name: add_s32_gpr
 name:            add_s32_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr32 }
 # CHECK-NEXT:  - { id: 1, class: gpr32 }
 # CHECK-NEXT:  - { id: 2, class: gpr32 }
 registers:
bb.0:
     %1(32) = COPY %w1
     %2(32) = G_ADD s32 %0, %1
 ...
 
 ---
 # Same as add_s32_gpr, for 64-bit operations.
 # CHECK-LABEL: name: add_s64_gpr
 name:            add_s64_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr64 }
 # CHECK-NEXT:  - { id: 1, class: gpr64 }
 # CHECK-NEXT:  - { id: 2, class: gpr64 }
 registers:
bb.0:
     %1(64) = COPY %x1
     %2(64) = G_ADD s64 %0, %1
 ...
 
 ---
 # Same as add_s32_gpr, for G_SUB operations.
 # CHECK-LABEL: name: sub_s32_gpr
 name:            sub_s32_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr32 }
 # CHECK-NEXT:  - { id: 1, class: gpr32 }
 # CHECK-NEXT:  - { id: 2, class: gpr32 }
 registers:
bb.0:
     %1(32) = COPY %w1
     %2(32) = G_SUB s32 %0, %1
 ...
 
 ---
 # Same as add_s64_gpr, for G_SUB operations.
 # CHECK-LABEL: name: sub_s64_gpr
 name:            sub_s64_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr64 }
 # CHECK-NEXT:  - { id: 1, class: gpr64 }
 # CHECK-NEXT:  - { id: 2, class: gpr64 }
 registers:
bb.0:
     %1(64) = COPY %x1
     %2(64) = G_SUB s64 %0, %1
 ...
 
 ---
 # Same as add_s32_gpr, for G_OR operations.
 # CHECK-LABEL: name: or_s32_gpr
 name:            or_s32_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr32 }
 # CHECK-NEXT:  - { id: 1, class: gpr32 }
 # CHECK-NEXT:  - { id: 2, class: gpr32 }
 registers:
bb.0:
     %1(32) = COPY %w1
     %2(32) = G_OR s32 %0, %1
 ...
 
 ---
 # Same as add_s64_gpr, for G_OR operations.
 # CHECK-LABEL: name: or_s64_gpr
 name:            or_s64_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr64 }
 # CHECK-NEXT:  - { id: 1, class: gpr64 }
 # CHECK-NEXT:  - { id: 2, class: gpr64 }
 registers:
bb.0:
     %1(64) = COPY %x1
     %2(64) = G_OR s64 %0, %1
 ...
 
 ---
 # Same as add_s32_gpr, for G_XOR operations.
 # CHECK-LABEL: name: xor_s32_gpr
 name:            xor_s32_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr32 }
 # CHECK-NEXT:  - { id: 1, class: gpr32 }
 # CHECK-NEXT:  - { id: 2, class: gpr32 }
 registers:
bb.0:
     %1(32) = COPY %w1
     %2(32) = G_XOR s32 %0, %1
 ...
 
 ---
 # Same as add_s64_gpr, for G_XOR operations.
 # CHECK-LABEL: name: xor_s64_gpr
 name:            xor_s64_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr64 }
 # CHECK-NEXT:  - { id: 1, class: gpr64 }
 # CHECK-NEXT:  - { id: 2, class: gpr64 }
 registers:
bb.0:
     %1(64) = COPY %x1
     %2(64) = G_XOR s64 %0, %1
 ...
 
 ---
 # Same as add_s32_gpr, for G_AND operations.
 # CHECK-LABEL: name: and_s32_gpr
 name:            and_s32_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr32 }
 # CHECK-NEXT:  - { id: 1, class: gpr32 }
 # CHECK-NEXT:  - { id: 2, class: gpr32 }
 registers:
bb.0:
     %1(32) = COPY %w1
     %2(32) = G_AND s32 %0, %1
 ...
 
 ---
 # Same as add_s64_gpr, for G_AND operations.
 # CHECK-LABEL: name: and_s64_gpr
 name:            and_s64_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr64 }
 # CHECK-NEXT:  - { id: 1, class: gpr64 }
 # CHECK-NEXT:  - { id: 2, class: gpr64 }
 registers:
bb.0:
     %1(64) = COPY %x1
     %2(64) = G_AND s64 %0, %1
 ...
 
 ---
 # Same as add_s32_gpr, for G_SHL operations.
 # CHECK-LABEL: name: shl_s32_gpr
 name:            shl_s32_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr32 }
 # CHECK-NEXT:  - { id: 1, class: gpr32 }
 # CHECK-NEXT:  - { id: 2, class: gpr32 }
 registers:
bb.0:
     %1(32) = COPY %w1
     %2(32) = G_SHL s32 %0, %1
 ...
 
 ---
 # Same as add_s64_gpr, for G_SHL operations.
 # CHECK-LABEL: name: shl_s64_gpr
 name:            shl_s64_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr64 }
 # CHECK-NEXT:  - { id: 1, class: gpr64 }
 # CHECK-NEXT:  - { id: 2, class: gpr64 }
 registers:
bb.0:
     %1(64) = COPY %x1
     %2(64) = G_SHL s64 %0, %1
 ...
 
 ---
 # Same as add_s32_gpr, for G_LSHR operations.
 # CHECK-LABEL: name: lshr_s32_gpr
 name:            lshr_s32_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr32 }
 # CHECK-NEXT:  - { id: 1, class: gpr32 }
 # CHECK-NEXT:  - { id: 2, class: gpr32 }
 registers:
bb.0:
     %1(32) = COPY %w1
     %2(32) = G_LSHR s32 %0, %1
 ...
 
 ---
 # Same as add_s64_gpr, for G_LSHR operations.
 # CHECK-LABEL: name: lshr_s64_gpr
 name:            lshr_s64_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr64 }
 # CHECK-NEXT:  - { id: 1, class: gpr64 }
 # CHECK-NEXT:  - { id: 2, class: gpr64 }
 registers:
bb.0:
     %1(64) = COPY %x1
     %2(64) = G_LSHR s64 %0, %1
 ...
 
 ---
 # Same as add_s32_gpr, for G_ASHR operations.
 # CHECK-LABEL: name: ashr_s32_gpr
 name:            ashr_s32_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr32 }
 # CHECK-NEXT:  - { id: 1, class: gpr32 }
 # CHECK-NEXT:  - { id: 2, class: gpr32 }
 registers:
bb.0:
     %1(32) = COPY %w1
     %2(32) = G_ASHR s32 %0, %1
 ...
 
 ---
 # Same as add_s64_gpr, for G_ASHR operations.
 # CHECK-LABEL: name: ashr_s64_gpr
 name:            ashr_s64_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr64 }
 # CHECK-NEXT:  - { id: 1, class: gpr64 }
 # CHECK-NEXT:  - { id: 2, class: gpr64 }
 registers:
bb.0:
     %1(64) = COPY %x1
     %2(64) = G_ASHR s64 %0, %1
 ...
 
 # Check that we select s32 GPR G_MUL. This is trickier than other binops because
 # there is only MADDWrrr, and we have to use the WZR physreg.
 # CHECK-LABEL: name: mul_s32_gpr
 name:            mul_s32_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr32 }
 # CHECK-NEXT:  - { id: 1, class: gpr32 }
 # CHECK-NEXT:  - { id: 2, class: gpr32 }
 registers:
bb.0:
     %1(32) = COPY %w1
     %2(32) = G_MUL s32 %0, %1
 ...
 
 ---
 # Same as mul_s32_gpr for the s64 type.
 # CHECK-LABEL: name: mul_s64_gpr
 name:            mul_s64_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr64 }
 # CHECK-NEXT:  - { id: 1, class: gpr64 }
 # CHECK-NEXT:  - { id: 2, class: gpr64 }
 registers:
bb.0:
     %1(64) = COPY %x1
     %2(64) = G_MUL s64 %0, %1
 ...
 
 ---
 # Same as add_s32_gpr, for G_SDIV operations.
 # CHECK-LABEL: name: sdiv_s32_gpr
 name:            sdiv_s32_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr32 }
 # CHECK-NEXT:  - { id: 1, class: gpr32 }
 # CHECK-NEXT:  - { id: 2, class: gpr32 }
 registers:
bb.0:
     %1(32) = COPY %w1
     %2(32) = G_SDIV s32 %0, %1
 ...
 
 ---
 # Same as add_s64_gpr, for G_SDIV operations.
 # CHECK-LABEL: name: sdiv_s64_gpr
 name:            sdiv_s64_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr64 }
 # CHECK-NEXT:  - { id: 1, class: gpr64 }
 # CHECK-NEXT:  - { id: 2, class: gpr64 }
 registers:
bb.0:
     %1(64) = COPY %x1
     %2(64) = G_SDIV s64 %0, %1
 ...
 
 ---
 # Same as add_s32_gpr, for G_UDIV operations.
 # CHECK-LABEL: name: udiv_s32_gpr
 name:            udiv_s32_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr32 }
 # CHECK-NEXT:  - { id: 1, class: gpr32 }
 # CHECK-NEXT:  - { id: 2, class: gpr32 }
 registers:
bb.0:
     %1(32) = COPY %w1
     %2(32) = G_UDIV s32 %0, %1
 ...
 
 ---
 # Same as add_s64_gpr, for G_UDIV operations.
 # CHECK-LABEL: name: udiv_s64_gpr
 name:            udiv_s64_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr64 }
 # CHECK-NEXT:  - { id: 1, class: gpr64 }
 # CHECK-NEXT:  - { id: 2, class: gpr64 }
 registers:
bb.0:
     %1(64) = COPY %x1
     %2(64) = G_UDIV s64 %0, %1
 ...
 
 ---
 # Check that we select a s32 FPR G_FADD into FADDSrr.
 # CHECK-LABEL: name: fadd_s32_gpr
 name:            fadd_s32_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: fpr32 }
 # CHECK-NEXT:  - { id: 1, class: fpr32 }
 # CHECK-NEXT:  - { id: 2, class: fpr32 }
 registers:
bb.0:
     %0(32) = COPY %s0
     %1(32) = COPY %s1
     %2(32) = G_FADD s32 %0, %1
 ...
 
 ---
 # CHECK-LABEL: name: fadd_s64_gpr
 name:            fadd_s64_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: fpr64 }
 # CHECK-NEXT:  - { id: 1, class: fpr64 }
 # CHECK-NEXT:  - { id: 2, class: fpr64 }
 registers:
bb.0:
     %0(64) = COPY %d0
     %1(64) = COPY %d1
     %2(64) = G_FADD s64 %0, %1
 ...
 
 ---
 # CHECK-LABEL: name: fsub_s32_gpr
 name:            fsub_s32_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: fpr32 }
 # CHECK-NEXT:  - { id: 1, class: fpr32 }
 # CHECK-NEXT:  - { id: 2, class: fpr32 }
 registers:
bb.0:
     %0(32) = COPY %s0
     %1(32) = COPY %s1
     %2(32) = G_FSUB s32 %0, %1
 ...
 
 ---
 # CHECK-LABEL: name: fsub_s64_gpr
 name:            fsub_s64_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: fpr64 }
 # CHECK-NEXT:  - { id: 1, class: fpr64 }
 # CHECK-NEXT:  - { id: 2, class: fpr64 }
 registers:
bb.0:
     %0(64) = COPY %d0
     %1(64) = COPY %d1
     %2(64) = G_FSUB s64 %0, %1
 ...
 
 ---
 # CHECK-LABEL: name: fmul_s32_gpr
 name:            fmul_s32_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: fpr32 }
 # CHECK-NEXT:  - { id: 1, class: fpr32 }
 # CHECK-NEXT:  - { id: 2, class: fpr32 }
 registers:
bb.0:
     %0(32) = COPY %s0
     %1(32) = COPY %s1
     %2(32) = G_FMUL s32 %0, %1
 ...
 
 ---
 # CHECK-LABEL: name: fmul_s64_gpr
 name:            fmul_s64_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: fpr64 }
 # CHECK-NEXT:  - { id: 1, class: fpr64 }
 # CHECK-NEXT:  - { id: 2, class: fpr64 }
 registers:
bb.0:
     %0(64) = COPY %d0
     %1(64) = COPY %d1
     %2(64) = G_FMUL s64 %0, %1
 ...
 
 ---
 # CHECK-LABEL: name: fdiv_s32_gpr
 name:            fdiv_s32_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: fpr32 }
 # CHECK-NEXT:  - { id: 1, class: fpr32 }
 # CHECK-NEXT:  - { id: 2, class: fpr32 }
 registers:
bb.0:
     %0(32) = COPY %s0
     %1(32) = COPY %s1
     %2(32) = G_FDIV s32 %0, %1
 ...
 
 ---
 # CHECK-LABEL: name: fdiv_s64_gpr
 name:            fdiv_s64_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: fpr64 }
 # CHECK-NEXT:  - { id: 1, class: fpr64 }
 # CHECK-NEXT:  - { id: 2, class: fpr64 }
 registers:
bb.0:
     %0(64) = COPY %d0
     %1(64) = COPY %d1
     %2(64) = G_FDIV s64 %0, %1
 ...
 
 ---
 # CHECK-LABEL: name: unconditional_br
 name:            unconditional_br
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:  body:
 # CHECK:   bb.0:
 # CHECK:    successors: %bb.0
 # CHECK:    B %bb.0
 body:             |
   bb.0:
     successors: %bb.0
 
     G_BR unsized %bb.0
 ...
 
 ---
 # CHECK-LABEL: name: load_s64_gpr
 name:            load_s64_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr64sp }
 # CHECK-NEXT:  - { id: 1, class: gpr64 }
 registers:
   - { id: 0, class: gpr }
bb.0:
     %0(64) = COPY %x0
     %1(64) = G_LOAD { s64, p0 }  %0 :: (load 8 from %ir.addr)
 
 ...
 
 ---
 # CHECK-LABEL: name: load_s32_gpr
 name:            load_s32_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr64sp }
 # CHECK-NEXT:  - { id: 1, class: gpr32 }
 registers:
   - { id: 0, class: gpr }
bb.0:
     %0(64) = COPY %x0
     %1(32) = G_LOAD { s32, p0 }  %0 :: (load 4 from %ir.addr)
 
 ...
 
 ---
 # CHECK-LABEL: name: store_s64_gpr
 name:            store_s64_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr64sp }
 # CHECK-NEXT:  - { id: 1, class: gpr64 }
 registers:
   - { id: 0, class: gpr }
bb.0:
     %1(64) = COPY %x1
     G_STORE { s64, p0 }  %1, %0 :: (store 8 into %ir.addr)
 
 ...
 
 ---
 # CHECK-LABEL: name: store_s32_gpr
 name:            store_s32_gpr
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr64sp }
 # CHECK-NEXT:  - { id: 1, class: gpr32 }
 registers:
   - { id: 0, class: gpr }
bb.0:
     %1(32) = COPY %w1
     G_STORE { s32, p0 }  %1, %0 :: (store 4 into %ir.addr)
 
 ...
 
 ---
 # CHECK-LABEL: name: frame_index
 name:            frame_index
-isSSA:           true
 legalized:       true
 regBankSelected: true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr64sp }
 registers:
   - { id: 0, class: gpr }
 
 stack:
   - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
 
 # CHECK:  body:
 # CHECK: %0 = ADDXri %stack.0.ptr0, 0, 0
 body:             |
   bb.0:
     %0(64) = G_FRAME_INDEX p0  %stack.0.ptr0
 ...
 
 ---
 # Check that we set the "selected" property.
 # CHECK-LABEL: name: selected_property
 # CHECK: legalized: true
 # CHECK-NEXT: regBankSelected: true
 # CHECK-NEXT: selected: true
-# CHECK-NEXT: isSSA: true
 name:            selected_property
-isSSA:           true
 legalized:       true
 regBankSelected: true
 selected:        false
 body:             |
   bb.0:
 ...

llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir

--- |
 
   define void @regBankSelected_property() { ret void }
 ...
 
 ---
 # Check that we assign a relevant register bank for %0.
 # Based on the type i32, this should be gpr.
 name:            defaultMapping
-isSSA:           true
 legalized:       true
 # CHECK:      registers:
 # CHECK-NEXT:   - { id: 0, class: gpr }
 registers:
   - { id: 0, class: _ }
 body: |
   bb.0.entry:
     liveins: %x0
     ; CHECK:      %0(32) = G_ADD s32 %w0
     %0(32) = G_ADD s32 %w0, %w0
 ...
 
 ---
 # Check that we assign a relevant register bank for %0.
 # Based on the type <2 x i32>, this should be fpr.
 # FPR is used for both floating point and vector registers.
 name:            defaultMappingVector
-isSSA:           true
 legalized:       true
 # CHECK:      registers:
 # CHECK-NEXT:   - { id: 0, class: fpr }
 registers:
   - { id: 0, class: _ }
 body: |
   bb.0.entry:
     liveins: %d0
     ; CHECK:      %0(64) = G_ADD <2 x s32> %d0
     %0(64) = G_ADD <2 x s32> %d0, %d0
 ...
 
 ---
 # Check that we repair the assignment for %0.
 # Indeed based on the source of the copy it should live
 # in FPR, but at the use, it should be GPR.
 name:            defaultMapping1Repair
-isSSA:           true
 legalized:       true
 # CHECK:      registers:
 # CHECK-NEXT:   - { id: 0, class: fpr }
 # CHECK-NEXT:   - { id: 1, class: gpr }
 # CHECK-NEXT:   - { id: 2, class: gpr }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0.entry:
     liveins: %s0, %x0
     ; CHECK:           %0(32) = COPY %s0
     ; CHECK-NEXT:      %2(32) = COPY %0
     ; CHECK-NEXT:      %1(32) = G_ADD s32 %2, %w0
     %0(32) = COPY %s0
     %1(32) = G_ADD s32 %0, %w0
 ...
 
 # Check that we repair the assignment for %0 differently for both uses.
 name:            defaultMapping2Repairs
-isSSA:           true
 legalized:       true
 # CHECK:      registers:
 # CHECK-NEXT:   - { id: 0, class: fpr }
 # CHECK-NEXT:   - { id: 1, class: gpr }
 # CHECK-NEXT:   - { id: 2, class: gpr }
 # CHECK-NEXT:   - { id: 3, class: gpr }
 registers:
   - { id: 0, class: _ }

 ...
 
 ---
 # Check that we repair the definition of %1.
 # %1 is forced to be into FPR, but its definition actually
 # requires that it lives in GPR. Make sure regbankselect
 # fixes that.
 name:            defaultMappingDefRepair
-isSSA:           true
 legalized:       true
 # CHECK:      registers:
 # CHECK-NEXT:   - { id: 0, class: gpr }
 # CHECK-NEXT:   - { id: 1, class: fpr }
 # CHECK-NEXT:   - { id: 2, class: gpr }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: fpr }
 body: |
   bb.0.entry:
     liveins: %w0
     ; CHECK:           %0(32) = COPY %w0
     ; CHECK-NEXT:      %2(32) = G_ADD s32 %0, %w0
     ; CHECK-NEXT:      %1(32) = COPY %2
     %0(32) = COPY %w0
     %1(32) = G_ADD s32 %0, %w0
 ...
 
 ---
 # Check that we are able to propagate register banks from phis.
 name:            phiPropagation
-isSSA:           true
 legalized:       true
 tracksRegLiveness:   true
 # CHECK:      registers:
 # CHECK-NEXT:   - { id: 0, class: gpr32 }
 # CHECK-NEXT:   - { id: 1, class: gpr64sp }
 # CHECK-NEXT:   - { id: 2, class: gpr32 }
 # CHECK-NEXT:   - { id: 3, class: gpr }
 # CHECK-NEXT:   - { id: 4, class: gpr }
bb.2.end:
     %4(32) = PHI %0, %bb.0.entry, %3, %bb.1.then
     STRWui killed %4, killed %1, 0 :: (store 4 into %ir.dst)
     RET_ReallyLR
 ...
 
 ---
 # Make sure we can repair physical register uses as well.
 name:            defaultMappingUseRepairPhysReg
-isSSA:           true
 legalized:       true
 # CHECK:      registers:
 # CHECK-NEXT:   - { id: 0, class: gpr }
 # CHECK-NEXT:   - { id: 1, class: gpr }
 # CHECK-NEXT:   - { id: 2, class: gpr }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0.entry:
     liveins: %w0, %s0
     ; CHECK:           %0(32) = COPY %w0
     ; CHECK-NEXT:      %2(32) = COPY %s0
     ; CHECK-NEXT:      %1(32) = G_ADD s32 %0, %2
     %0(32) = COPY %w0
     %1(32) = G_ADD s32 %0, %s0
 ...
 
 ---
 # Make sure we can repair physical register defs.
 name:            defaultMappingDefRepairPhysReg
-isSSA:           true
 legalized:       true
 # CHECK:      registers:
 # CHECK-NEXT:   - { id: 0, class: gpr }
 # CHECK-NEXT:   - { id: 1, class: gpr }
 registers:
   - { id: 0, class: _ }
 body: |
   bb.0.entry:
     liveins: %w0
     ; CHECK:           %0(32) = COPY %w0
     ; CHECK-NEXT:      %1(32) = G_ADD s32 %0, %0
     ; CHECK-NEXT:      %s0 = COPY %1
     %0(32) = COPY %w0
     %s0 = G_ADD s32 %0, %0
 ...
 
 ---
 # Check that the greedy mode is able to switch the
 # G_OR instruction from fpr to gpr.
 name:            greedyMappingOr
-isSSA:           true
 legalized:       true
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr }
 # CHECK-NEXT:  - { id: 1, class: gpr }
 
 # Fast mode maps vector instruction on FPR.
 # FAST-NEXT:  - { id: 2, class: fpr }
 # Fast mode needs two extra copies.
bb.0.entry:
     %2(64) = G_OR <2 x s32> %0, %1
 ...
 
 ---
 # Check that the greedy mode is able to switch the
 # G_OR instruction from fpr to gpr, while still honoring
 # %2 constraint.
 name:            greedyMappingOrWithConstraints
-isSSA:           true
 legalized:       true
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr }
 # CHECK-NEXT:  - { id: 1, class: gpr }
 # CHECK-NEXT:  - { id: 2, class: fpr }
 
 # Fast mode maps vector instruction on FPR.
 # Fast mode needs two extra copies.
bb.0.entry:
     %0(64) = COPY %x0
     %1(64) = COPY %x1
     %2(64) = G_OR <2 x s32> %0, %1
 ...
 
 ---
 # CHECK-LABEL: name: ignoreTargetSpecificInst
 name:            ignoreTargetSpecificInst
-isSSA:           true
 legalized:       true
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr64 }
 # CHECK-NEXT:  - { id: 1, class: gpr64 }
 registers:
   - { id: 0, class: gpr64 }
   - { id: 1, class: gpr64 }
 body: |
bb.0:
     RET_ReallyLR implicit %x0
 ...
 
 ---
 # Check that we set the "regBankSelected" property.
 # CHECK-LABEL: name: regBankSelected_property
 # CHECK: legalized: true
 # CHECK: regBankSelected: true
-# CHECK: isSSA: true
 name:            regBankSelected_property
-isSSA:           true
 legalized:       true
 regBankSelected: false
 body:             |
   bb.0:
 ...

llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir

--- |
   define void @test_vector_add() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_scalar_add_big
-isSSA:           true
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
     ; CHECK-LABEL: name: test_scalar_add_big
     ; CHECK-DAG: [[LHS_LO:%.*]](64), [[LHS_HI:%.*]](64) = G_EXTRACT { s64, s64, s128 } %0, 0, 64
     ; CHECK-DAG: [[RHS_LO:%.*]](64), [[RHS_HI:%.*]](64) = G_EXTRACT { s64, s64, s128 } %1, 0, 64
     ; CHECK-DAG: [[CARRY0:%.*]](1) = G_CONSTANT s1 0
     ; CHECK: [[RES_LO:%.*]](64), [[CARRY:%.*]](1) = G_UADDE s64 [[LHS_LO]], [[RHS_LO]], [[CARRY0]]
     ; CHECK: [[RES_HI:%.*]](64), {{%.*}}(1) = G_UADDE s64 [[LHS_HI]], [[RHS_HI]], [[CARRY]]
     ; CHECK: %2(128) = G_SEQUENCE { s128, s64, s64 } [[RES_LO]], 0, [[RES_HI]], 64
 
     %0(128) = G_SEQUENCE { s128, s64, s64 } %x0, 0, %x1, 64
     %1(128) = G_SEQUENCE { s128, s64, s64 } %x2, 0, %x3, 64
     %2(128) = G_ADD s128 %0, %1
     %x0, %x1 = G_EXTRACT { s64, s64, s128 } %2, 0, 64
 ...
 
 ---
 name:            test_scalar_add_small
-isSSA:           true
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
     ; CHECK-LABEL: name: test_scalar_add_small
     ; CHECK-DAG: [[LHS:%.*]](32) = G_ANYEXT { s32, s8 } %0
     ; CHECK-DAG: [[RHS:%.*]](32) = G_ANYEXT { s32, s8 } %1
     ; CHECK: [[RES:%.*]](32) = G_ADD s32 [[LHS]], [[RHS]]
     ; CHECK: %2(8) = G_TRUNC { s8, s32 } [[RES]]
 
     %0(8) = G_TRUNC { s8, s64 } %x0
     %1(8) = G_TRUNC { s8, s64 } %x1
     %2(8) = G_ADD s8 %0, %1
     %x0 = G_ANYEXT { s64, s8 } %2
 ...
 
 ---
 name:            test_vector_add
-isSSA:           true
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body: |
   bb.0.entry:
     liveins: %q0, %q1, %q2, %q3
     ; CHECK-LABEL: name: test_vector_add

llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir

 # RUN: llc -O0 -run-pass=legalize-mir -global-isel %s -o - 2>&1 | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64-apple-ios"
   define void @test_scalar_and_small() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_scalar_and_small
-isSSA:           true
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
     ; CHECK-LABEL: name: test_scalar_and_small

llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir

 # RUN: llc -O0 -run-pass=legalize-mir -global-isel %s -o - 2>&1 | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64-apple-ios"
   define void @test_icmp() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_icmp
-isSSA:           true
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }
   - { id: 6, class: _ }

llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir

--- |
   define void @test_fconstant() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_constant
-isSSA:           true
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
 body: |
   bb.0.entry:
bb.0.entry:
     %1(8) = G_CONSTANT s8 42
     %2(16) = G_CONSTANT s16 65535
     %3(32) = G_CONSTANT s32 -1
     %4(64) = G_CONSTANT s64 1
 ...
 
 ---
 name:            test_fconstant
-isSSA:           true
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body: |
   bb.0.entry:
     ; CHECK-LABEL: name: test_fconstant
     ; CHECK: %0(32) = G_FCONSTANT s32  float 1.000000e+00
     ; CHECK: %1(64) = G_FCONSTANT s64  double 2.000000e+00
     ; CHECK: [[TMP:%[0-9]+]](32) = G_FCONSTANT s32 half 0xH0000
     ; CHECK; %2(16) = G_FPTRUNC { s16, s32 } [[TMP]]
 
     %0(32) = G_FCONSTANT s32 float 1.0
     %1(64) = G_FCONSTANT s64 double 2.0
     %2(16) = G_FCONSTANT s16 half 0.0
 ...

llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir

 # RUN: llc -O0 -run-pass=legalize-mir -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64--"
   define void @test_copy() { ret void }
   define void @test_targetspecific() { ret void }
 ...
 
 ---
 name:            test_copy
-isSSA:           true
 registers:
   - { id: 0, class: _ }
 body: |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: test_copy
     ; CHECK: %0(64) = COPY %x0
     ; CHECK-NEXT: %x0 = COPY %0
 
     %0(64) = COPY %x0
     %x0 = COPY %0
 ...
 
 ---
 name:            test_targetspecific
-isSSA:           true
 body: |
   bb.0:
     ; CHECK-LABEL: name: test_targetspecific
     ; CHECK: RET_ReallyLR
 
     RET_ReallyLR
 ...

llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir

--- |
   define void @test_store(i8* %addr) {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_load
-isSSA:           true
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }
 body: |
bb.0.entry:
     %4(32) = G_LOAD { s32, p0 } %0 :: (load 4 from %ir.addr)
 
     ; CHECK: %5(64) = G_LOAD { s64, p0 } %0 :: (load 8 from %ir.addr)
     %5(64) = G_LOAD { s64, p0 } %0 :: (load 8 from %ir.addr)
 ...
 
 ---
 name:            test_store
-isSSA:           true
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
 body: |
   bb.0.entry:

llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir

 # RUN: llc -O0 -run-pass=legalize-mir -global-isel %s -o - 2>&1 | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64-apple-ios"
   define void @test_scalar_mul_small() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_scalar_mul_small
-isSSA:           true
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
     ; CHECK-LABEL: name: test_scalar_mul_small

llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir

 # RUN: llc -O0 -run-pass=legalize-mir -global-isel %s -o - 2>&1 | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64-apple-ios"
   define void @test_scalar_or_small() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_scalar_or_small
-isSSA:           true
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
     ; CHECK-LABEL: name: test_scalar_or_small

llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-property.mir

 # RUN: llc -O0 -run-pass=legalize-mir -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64--"
   define void @legalized_property() { ret void }
 ...
 
 ---
 # Check that we set the "legalized" property.
 # CHECK-LABEL: name: legalized_property
 # CHECK: legalized: true
-# CHECK: isSSA: true
 name:            legalized_property
-isSSA:           true
 legalized:       false
 body:             |
   bb.0:
 ...

llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir

 # RUN: llc -O0 -run-pass=legalize-mir -global-isel %s -o - 2>&1 | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64-apple-ios"
   define void @test_simple() {
   entry:
     ret void
   next:
     ret void
   }
 ...
 
 ---
 name:            test_simple
-isSSA:           true
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3

llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir

 # RUN: llc -O0 -run-pass=legalize-mir -global-isel %s -o - 2>&1 | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64-apple-ios"
   define void @test_scalar_sub_small() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_scalar_sub_small
-isSSA:           true
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
     ; CHECK-LABEL: name: test_scalar_sub_small

llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir

 # RUN: llc -O0 -run-pass=legalize-mir -global-isel %s -o - 2>&1 | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64-apple-ios"
   define void @test_scalar_xor_small() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test_scalar_xor_small
-isSSA:           true
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
     ; CHECK-LABEL: name: test_scalar_xor_small

llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir

 # RUN: not llc -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
 
 --- |
 
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64--"
   define void @test() { ret void }
 
 ...
 ---
 # CHECK: *** Bad machine code: Generic virtual register must have a bank in a RegBankSelected function ***
 # CHECK: instruction: %vreg0<def>(64) = COPY
 # CHECK: operand 0: %vreg0<def>
 name:            test
-isSSA: true
 regBankSelected: true
 registers:
   - { id: 0, class: _ }
 body: |
   bb.0:
    liveins: %x0
    %0(64) = COPY %x0
 ...

llvm/trunk/test/CodeGen/AArch64/GlobalISel/verify-selected.mir

 # RUN: not llc -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
 
 --- |
 
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64--"
   define void @test() { ret void }
 
 ...
 
 ---
 name:            test
-isSSA: true
 regBankSelected: true
 selected: true
 registers:
   - { id: 0, class: gpr64 }
   - { id: 1, class: gpr64 }
   - { id: 2, class: gpr }
 body: |
   bb.0:

llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir

 
 ...
 ---
 name:            promote-load-from-store
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: true
-isSSA:           false
 tracksRegLiveness: false
 tracksSubRegLiveness: false
 liveins:         
   - { reg: '%x0' }
   - { reg: '%w1' }
 frameInfo:       
   isFrameAddressTaken: false
   isReturnAddressTaken: false

 # CHECK: STRWui killed %w1
 # CHECK: UBFMWri %w1
 ---
 name:            store-pair
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: true
-isSSA:           false
 tracksRegLiveness: false
 tracksSubRegLiveness: false
 liveins:         
   - { reg: '%x0' }
   - { reg: '%w1' }
 frameInfo:       
   isFrameAddressTaken: false
   isReturnAddressTaken: false

llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir

 
 ...
 ---
 name:            test_mov_0
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: true
-isSSA:           false
 tracksRegLiveness: false
 tracksSubRegLiveness: false
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0

llvm/trunk/test/CodeGen/AMDGPU/detect-dead-lanes.mir

 # CHECK: S_NOP 0, implicit %3.sub1
 # CHECK: S_NOP 0, implicit undef %3.sub2
 # CHECK: %4 = COPY %3.sub0_sub1
 # CHECK: %5 = COPY undef %3.sub2_sub3
 # CHECK: S_NOP 0, implicit %4.sub0
 # CHECK: S_NOP 0, implicit %4.sub1
 # CHECK: S_NOP 0, implicit undef %5.sub0
 name: test0
-isSSA: true
 registers:
   - { id: 0, class: sreg_32 }
   - { id: 1, class: sreg_32 }
   - { id: 2, class: sreg_32 }
   - { id: 3, class: sreg_128 }
   - { id: 4, class: sreg_64 }
   - { id: 5, class: sreg_64 }
 body: |

 
 # CHECK: %8 = IMPLICIT_DEF
 # CHECK: %9 = EXTRACT_SUBREG undef %8, {{[0-9]+}}
 # CHECK: S_NOP 0, implicit undef %9
 
 # CHECK: %10 = EXTRACT_SUBREG undef %0, {{[0-9]+}}
 # CHECK: S_NOP 0, implicit undef %10
 name: test1
-isSSA: true
 registers:
   - { id: 0, class: sreg_128 }
   - { id: 1, class: sreg_128 }
   - { id: 2, class: sreg_64 }
   - { id: 3, class: sreg_32 }
   - { id: 4, class: sreg_128 }
   - { id: 5, class: sreg_64 }
   - { id: 6, class: sreg_32 }

 
 # CHECK: S_NOP 0, implicit-def %13
 # CHECK: S_NOP 0, implicit-def dead %14
 # CHECK: %15 = REG_SEQUENCE %13, {{[0-9]+}}, undef %14, {{[0-9]+}}
 # CHECK: %16 = EXTRACT_SUBREG %15, {{[0-9]+}}
 # CHECK: S_NOP 0, implicit %16.sub1
 
 name: test2
-isSSA: true
 registers:
   - { id: 0, class: sreg_32 }
   - { id: 1, class: sreg_32 }
   - { id: 2, class: sreg_64 }
   - { id: 3, class: sreg_128 }
   - { id: 4, class: sreg_32 }
   - { id: 5, class: sreg_32 }
   - { id: 6, class: sreg_64 }

 # Check that copies to physregs use all lanes, copies from physregs define all
 # lanes. So we should not get a dead/undef flag here.
 # CHECK-LABEL: name: test3
 # CHECK: S_NOP 0, implicit-def %0
 # CHECK: %vcc = COPY %0
 # CHECK: %1 = COPY %vcc
 # CHECK: S_NOP 0, implicit %1
 name: test3
-isSSA: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: sreg_64 }
   - { id: 1, class: sreg_64 }
 body: |
   bb.0:
     S_NOP 0, implicit-def %0
     %vcc = COPY %0
 
     %1 = COPY %vcc
     S_NOP 0, implicit %1
 ...
 ---
 # Check that implicit-def/kill do not count as def/uses.
 # CHECK-LABEL: name: test4
 # CHECK: S_NOP 0, implicit-def dead %0
 # CHECK: KILL undef %0
 # CHECK: %1 = IMPLICIT_DEF
 # CHECK: S_NOP 0, implicit undef %1
 name: test4
-isSSA: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: sreg_64 }
   - { id: 1, class: sreg_64 }
 body: |
   bb.0:
     S_NOP 0, implicit-def %0
     KILL %0
 
     %1 = IMPLICIT_DEF
     S_NOP 0, implicit %1
 ...
 ---
 # Check that unused inputs are marked as undef, even if the vreg itself is
 # used.
 # CHECK-LABEL: name: test5
 # CHECK: S_NOP 0, implicit-def %0
 # CHECK: %1 = REG_SEQUENCE undef %0, {{[0-9]+}}, %0, {{[0-9]+}}
 # CHECK: S_NOP 0, implicit %1.sub1
 name: test5
-isSSA: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: sreg_32 }
   - { id: 1, class: sreg_64 }
 body: |
   bb.0:
     S_NOP 0, implicit-def %0
     %1 = REG_SEQUENCE %0, %subreg.sub0, %0, %subreg.sub1

 
 # CHECK: bb.1:
 # CHECK: %4 = PHI %3, %bb.0, %5, %bb.1
 
 # CHECK: bb.2:
 # CHECK:   S_NOP 0, implicit %4.sub0
 # CHECK:   S_NOP 0, implicit undef %4.sub3
 name: loop0
-isSSA: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: sreg_32 }
   - { id: 1, class: sreg_32 }
   - { id: 2, class: sreg_32 }
   - { id: 3, class: sreg_128 }
   - { id: 4, class: sreg_128 }
   - { id: 5, class: sreg_128 }

 # CHECK: bb.1:
 # CHECK: %5 = PHI %4, %bb.0, %6, %bb.1
 
 # CHECK: %6 = REG_SEQUENCE %5.sub1, {{[0-9]+}}, %5.sub3, {{[0-9]+}}, undef %5.sub2, {{[0-9]+}}, %5.sub0, {{[0-9]+}}
 
 # CHECK: bb.2:
 # CHECK:   S_NOP 0, implicit %6.sub3
 name: loop1
-isSSA: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: sreg_32 }
   - { id: 1, class: sreg_32 }
   - { id: 2, class: sreg_32 }
   - { id: 3, class: sreg_32 }
   - { id: 4, class: sreg_128 }
   - { id: 5, class: sreg_128 }

 # CHECK: %3 = REG_SEQUENCE %2.sub3, {{[0-9]+}}, undef %2.sub1, {{[0-9]+}}, %2.sub0, {{[0-9]+}}, %2.sub2, {{[0-9]+}}
 
 # CHECK: bb.2:
 # CHECK:   S_NOP 0, implicit %2.sub0
 # CHECK:   S_NOP 0, implicit undef %2.sub1
 # CHECK:   S_NOP 0, implicit %2.sub2
 # CHECK:   S_NOP 0, implicit %2.sub3
 name: loop2
-isSSA: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: sreg_32 }
   - { id: 1, class: sreg_128 }
   - { id: 2, class: sreg_128 }
   - { id: 3, class: sreg_128 }
 body: |
   bb.0:

llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir

 
 ...
 ---
 name:            f
 alignment:       1
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: true
-isSSA:           false
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 liveins:
   - { reg: '%r0' }
   - { reg: '%r1' }
   - { reg: '%r2' }
   - { reg: '%r3' }
 calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13',

llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir

 # RUN: not llc -mtriple=aarch64-apple-ios -run-pass none -o - %s 2>&1 \
 # RUN:        | FileCheck %s --check-prefix=ERR
 # REQUIRES: global-isel
 # This test ensures that the MIR parser errors out when
 # generic virtual register definitions are not correct.
 
 --- |
   define void @baz() { ret void }
 ...
 
 ---
 name:            baz
-isSSA:           true
 registers:
   - { id: 0, class: _ }
 body: |
   bb.0:
     liveins: %w0
     ; ERR: generic virtual registers must have a size
     ; ERR-NEXT: %0
     ; ERR: Unable to initialize machine function
     %0 = G_ADD i32 %w0, %w0
 ...

llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir

 # RUN: not llc -mtriple=aarch64-apple-ios -run-pass none -o - %s 2>&1 \
 # RUN:        | FileCheck %s --check-prefix=ERR
 # REQUIRES: global-isel
 # This test ensures that the MIR parser errors out when
 # generic virtual register definitions are not correct.
 # In that case, it is defined by a register bank.
 
 --- |
   define void @bar() { ret void }
 ...
 
 ---
 name:            bar
-isSSA:           true
 registers:
   - { id: 0, class: gpr }
 body: |
   bb.0:
     liveins: %w0
     ; ERR: generic virtual registers must have a size
     ; ERR-NEXT: %0
     ; ERR: Unable to initialize machine function
     %0 = G_ADD i32 %w0, %w0
 ...

llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir

 # than what TLSDESC_CALLSEQ is lowered to).
 # CHECK: TBZW killed %w0, 0, %bb.1.true
 # CHECK: B %bb.2.false
 name:            test_tlsdesc_callseq_length
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: true
-isSSA:           false
 tracksRegLiveness: false
 tracksSubRegLiveness: false
 liveins:
   - { reg: '%w0' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false

llvm/trunk/test/CodeGen/MIR/AArch64/machine-scheduler.mir

 ...
 ---
 # CHECK-LABEL: name: load_imp-def
 # CHECK: bb.0.entry:
 # CHECK: LDRWui %x0, 0
 # CHECK: LDRWui %x0, 1
 # CHECK: STRWui %w1, %x0, 2
 name:            load_imp-def
-isSSA:           true
 body:             |
   bb.0.entry:
     liveins: %w1, %x0
     %w8 = LDRWui %x0, 1, implicit-def %x8  :: (load 4 from %ir.0)
     STRWui killed %w1, %x0, 2 :: (store 4 into %ir.arrayidx1)
     %w9 = LDRWui killed %x0, 0, implicit-def %x9  :: (load 4 from %ir.arrayidx19, align 8)
     %x0 = ADDXrr killed %x9, killed %x8
     RET_ReallyLR implicit %x0
 ...
 

llvm/trunk/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir

entry:
     %val = load i64, i64* @var
     store i64 %val, i64* %local_var
     store i64* %local_var, i64** @local_addr
     ret void
   }
 ...
 ---
 name:            stack_local
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gpr64common }
   - { id: 1, class: gpr64 }
   - { id: 2, class: gpr64common }
   - { id: 3, class: gpr64common }
 frameInfo:
   maxAlignment:    8

llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir

 
 ...
 ---
 name:            f
 alignment:       1
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: true
-isSSA:           false
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 liveins:
   - { reg: '%r0' }
   - { reg: '%r1' }
   - { reg: '%r2' }
   - { reg: '%r3' }
 calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13',

llvm/trunk/test/CodeGen/MIR/Generic/frame-info.mir

entry:
     store i32 %a, i32* %b
     %c = load i32, i32* %b
     ret i32 %c
   }
 
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 
 # CHECK: frameInfo:
 # CHECK-NEXT: isFrameAddressTaken: false
 # CHECK-NEXT: isReturnAddressTaken: false
 # CHECK-NEXT: hasStackMap: false
 # CHECK-NEXT: hasPatchPoint: false
 # CHECK-NEXT: stackSize: 0

 # CHECK: body
 frameInfo:
   maxAlignment:    4
 body: |
   bb.0.entry:
 ...
 ---
 name:            test2
-isSSA:           true
 tracksRegLiveness: true
 
 # CHECK: test2
 # CHECK: frameInfo:
 # CHECK-NEXT: isFrameAddressTaken: true
 # CHECK-NEXT: isReturnAddressTaken: true
 # CHECK-NEXT: hasStackMap: true
 # CHECK-NEXT: hasPatchPoint: true

llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir

--- |
   define i32 @bar() {
   start:
     ret i32 0
   }
 
 ...
 ---
 # CHECK: name: foo
-# CHECK:      isSSA: false
-# CHECK-NEXT: tracksRegLiveness: false
+# CHECK: tracksRegLiveness: false
 # CHECK-NEXT: tracksSubRegLiveness: false
 # CHECK: ...
 name:            foo
 body: |
   bb.0:
 ...
 ---
 # CHECK: name: bar
-# CHECK:      isSSA: false
-# CHECK-NEXT: tracksRegLiveness: true
+# CHECK: tracksRegLiveness: true
 # CHECK-NEXT: tracksSubRegLiveness: true
 # CHECK: ...
 name: bar
-isSSA: false
 tracksRegLiveness: true
 tracksSubRegLiveness: true
 body: |
   bb.0:
 ...

llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir

 
 ...
 ---
 name:            test0a
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: false
-isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }

 
 ...
 ---
 name:            test0b
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: false
-isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }

 
 ...
 ---
 name:            test1a
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: false
-isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }

 
 ...
 ---
 name:            test1b
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: false
-isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }

 
 ...
 ---
 name:            test2a
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: false
-isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }

 
 ...
 ---
 name:            test2b
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: false
-isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }

 
 ...
 ---
 name:            test3
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: false
-isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }

 
 ...
 ---
 name:            test4
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: false
-isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }

 
 ...
 ---
 name:            testBB
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: false
-isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }

llvm/trunk/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir

entry:
     %or.1 = or i32 %1, %or
     ret i32 %or.1
   }
 
   attributes #0 = { nounwind "target-cpu"="ppc64" }
 ...
 ---
 name:            main
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: g8rc_and_g8rc_nox0 }
   - { id: 1, class: gprc }
   - { id: 2, class: gprc }
   - { id: 3, class: gprc }
   - { id: 4, class: g8rc }
 liveins:

llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir

--- |
   !12 = !DILocalVariable(name: "x", arg: 1, scope: !4, file: !5, line: 4, type: !8)
   !13 = !DIExpression()
   !14 = !DILocation(line: 4, scope: !4)
   !15 = !DILocation(line: 8, scope: !4)
 
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
 frameInfo:
   maxAlignment:  4
 stack:
   - { id: 0, name: x.addr, size: 4, alignment: 4 }
 body: |
   bb.0.entry:
     %0 = COPY %edi
     ; CHECK: [[@LINE+1]]:46: expected a metadata node after 'debug-location'
     DBG_VALUE _, 0, !12, !13, debug-location 14
     MOV32mr %stack.x.addr, 1, _, 0, _, %0
     %eax = COPY %0
     RETQ %eax
 ...

llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir

--- |
   !12 = !DILocalVariable(name: "x", arg: 1, scope: !4, file: !5, line: 4, type: !8)
   !13 = !DIExpression()
   !14 = !DILocation(line: 4, scope: !4)
   !15 = !DILocation(line: 8, scope: !4)
 
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
 frameInfo:
   maxAlignment:  4
 stack:
   - { id: 0, name: x.addr, size: 4, alignment: 4 }
 body: |
   bb.0.entry:
     %0 = COPY %edi
     ; CHECK: [[@LINE+1]]:28: expected metadata id after '!'
     DBG_VALUE _, 0, !12, ! _
     MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
     %eax = COPY %0
     RETQ %eax
 ...

llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir

 # RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
 
 --- |
 
   define i32 @test(i32 %a) {
   body:
     ret i32 %a
   }
 
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
 liveins:
   # CHECK: [[@LINE+1]]:13: expected a named register
   - { reg: '%0' }
 body: |
   bb.0.body:
     liveins: %edi
 
     %0 = COPY %edi
     %eax = COPY %0
     RETQ %eax
 ...

llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir

 # RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
 
 --- |
 
   define zeroext i1 @t(i1 %c) {
   entry:
     ret i1 %c
   }
 
 ...
 ---
 name:            t
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr8 }
   - { id: 2, class: gr8 }
 body: |
   bb.0.entry:
     %0 = COPY %edi
     ; CHECK: [[@LINE+1]]:20: expected a subregister index after '.'
     %1 = COPY %0 . 42
     %2 = AND8ri %1, 1, implicit-def %eflags
     %al = COPY %2
     RETQ %al
 ...

llvm/trunk/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir

 # RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
 
 --- |
 
   define i32 @test(i32 %a) {
   body:
     ret i32 %a
   }
 
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
 liveins:
   # CHECK: [[@LINE+1]]:34: expected a virtual register
   - { reg: '%edi', virtual-reg: '%edi' }
 body: |
   bb.0.body:
     liveins: %edi
 
     %0 = COPY %edi
     %eax = COPY %0
     RETQ %eax
 ...

llvm/trunk/test/CodeGen/MIR/X86/function-liveins.mir

 # RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
 # This test ensures that the MIR parser parses machine function's liveins
 # correctly.
 
 --- |
 
   define i32 @test(i32 %a, i32 %b) {
   body:
     %c = add i32 %a, %b
     ret i32 %c
   }
 
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr32 }
   - { id: 2, class: gr32 }
 # CHECK: liveins:
 # CHECK-NEXT: - { reg: '%edi', virtual-reg: '%0' }
 # CHECK-NEXT: - { reg: '%esi', virtual-reg: '%1' }

llvm/trunk/test/CodeGen/MIR/X86/generic-instr-type.mir

--- |
   define void @test_unsized() {
     ret void
   }
 
 ...
 
 ---
 name:            test_vregs
-isSSA:           true
 # CHECK:      registers:
 # CHECK-NEXT:   - { id: 0, class: _ }
 # CHECK-NEXT:   - { id: 1, class: _ }
 # CHECK-NEXT:   - { id: 2, class: _ }
 # CHECK-NEXT:   - { id: 3, class: _ }
 # CHECK-NEXT:   - { id: 4, class: _ }
 registers:
   - { id: 0, class: _ }
bb.0:
     ; CHECK:      %3(64) = G_ADD s64 %edi
     %3(64) = G_ADD s64 %edi, %edi
     ; CHECK:      %4(48) = G_ADD s48 %edi
     %4(48) = G_ADD s48 %edi, %edi
 ...
 
 ---
 name:            test_unsized
-isSSA:           true
 body: |
   bb.0:
     successors: %bb.0
 
     ; CHECK:      G_BR unsized %bb.0
     G_BR unsized %bb.0
 ...

llvm/trunk/test/CodeGen/MIR/X86/instructions-debug-location.mir

--- |
   !12 = !DILocalVariable(name: "x", arg: 1, scope: !4, file: !5, line: 4, type: !8)
   !13 = !DIExpression()
   !14 = !DILocation(line: 4, scope: !4)
   !15 = !DILocation(line: 8, scope: !4)
 
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
 frameInfo:
   maxAlignment:  4
 stack:
   - { id: 0, name: x.addr, size: 4, alignment: 4 }
 body: |
   bb.0.entry:
     liveins: %edi
     ; CHECK: DBG_VALUE debug-use _, 0, !11, !12, debug-location !13
     ; CHECK: %eax = COPY %0, debug-location !14
     ; CHECK: RETQ %eax, debug-location !14
     %0 = COPY %edi
     DBG_VALUE debug-use _, 0, !12, !13, debug-location !14
     MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
     %eax = COPY %0, debug-location !15
     RETQ %eax, debug-location !15
 ...
 ---
 name:            test_typed_immediates
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
 frameInfo:
   maxAlignment:  4
 stack:
   - { id: 0, name: x.addr, size: 4, alignment: 4 }
 body: |

llvm/trunk/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir

--- |
   !4 = !DILocalVariable(name: "x", scope: !5, file: !1, line: 16, type: !6)
   !5 = distinct !DISubprogram(scope: null, isLocal: false, isDefinition: true, isOptimized: false, unit: !0)
   !6 = !DIBasicType(name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char)
   !7 = !DIExpression()
   !8 = !DILocation(line: 0, scope: !5)
 ...
 ---
 name:            foo
-isSSA:           true
 tracksRegLiveness: true
 frameInfo:
   maxAlignment:    16
 stack:
 # CHECK: [[@LINE+1]]:75: expected a reference to a 'DILocalVariable' metadata node
   - { id: 0, name: y.i, offset: 0, size: 256, alignment: 16, di-variable: '!8',
       di-expression: '!7', di-location: '!8' }
 body: |
   bb.0.entry:
     successors: %bb.1.for.body
   bb.1.for.body:
     successors: %bb.1.for.body
 
     DBG_VALUE %stack.0.y.i, 0, !4, !7, debug-location !8
     JMP_1 %bb.1.for.body
 ...

llvm/trunk/test/CodeGen/MIR/X86/metadata-operands.mir

--- |
   !12 = !DILocalVariable(name: "x", arg: 1, scope: !4, file: !5, line: 4, type: !8)
   !13 = !DIExpression()
   !14 = !DILocation(line: 4, scope: !4)
   !15 = !DILocation(line: 8, scope: !4)
 
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
 frameInfo:
   maxAlignment:  4
 stack:
   - { id: 0, name: x.addr, size: 4, alignment: 4 }
 body: |

llvm/trunk/test/CodeGen/MIR/X86/stack-object-debug-info.mir

--- |
   !7 = !DIExpression()
   !8 = !DILocation(line: 0, scope: !5)
   !9 = !DICompositeType(tag: DW_TAG_array_type, baseType: !6, size: 2048, align: 8, elements: !10)
   !10 = !{!11}
   !11 = !DISubrange(count: 256)
 ...
 ---
 name:            foo
-isSSA:           true
 tracksRegLiveness: true
 frameInfo:
   maxAlignment:    16
 # CHECK-LABEL: foo
 # CHECK: stack:
 # CHECK:  - { id: 0, name: y.i, offset: 0, size: 256, alignment: 16, di-variable: '!4',
 # CHECK-NEXT: di-expression: '!10', di-location: '!11' }
 stack:

llvm/trunk/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir

entry:
     store i32 %a, i32* %b
     %c = load i32, i32* %b
     ret i32 %c
   }
 
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
 frameInfo:
   maxAlignment:  4
 stack:
   - { id: 0, name: b, size: 4, alignment: 4 }
 body: |
   bb.0.entry:
     %0 = COPY %edi
     ; CHECK: [[@LINE+1]]:13: the name of the stack object '%stack.0' isn't 'x'
     MOV32mr %stack.0.x, 1, _, 0, _, %0
     %eax = COPY %0
     RETQ %eax
 ...

llvm/trunk/test/CodeGen/MIR/X86/stack-object-operands.mir

entry:
     store i32 2, i32* %0
     %c = load i32, i32* %b
     ret i32 %c
   }
 
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr32 }
 frameInfo:
   maxAlignment:    4
 fixedStack:
   - { id: 0, offset: 0, size: 4, isImmutable: true, isAliased: false }

llvm/trunk/test/CodeGen/MIR/X86/standalone-register-error.mir

 # RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
 --- |
   define i32 @test(i32 %a) {
   body:
     ret i32 %a
   }
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
 liveins:
 # CHECK: [[@LINE+1]]:13: unknown register name 'register'
   - { reg: '%register', virtual-reg: '%0' }
 body: |
   bb.0.body:
     liveins: %edi
 
     %0 = COPY %edi
     %eax = COPY %0
     RETQ %eax
 ...

llvm/trunk/test/CodeGen/MIR/X86/subregister-index-operands.mir

 
 ...
 ---
 # CHECK-LABEL: name: t
 # CHECK: %0 = INSERT_SUBREG %edi, %al, {{[0-9]+}}
 # CHECK: %1 = EXTRACT_SUBREG %eax, {{[0-9]+}}
 # CHECK: %ax = REG_SEQUENCE %1, {{[0-9]+}}, %1, {{[0-9]+}}
 name:            t
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr8 }
 body: |
   bb.0.entry:
     liveins: %edi, %eax
     %0 = INSERT_SUBREG %edi, %al, %subreg.sub_8bit
     %1 = EXTRACT_SUBREG %eax, %subreg.sub_8bit_hi
     %ax = REG_SEQUENCE %1, %subreg.sub_8bit, %1, %subreg.sub_8bit_hi
     RETQ %ax
 ...
 

llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir

 # RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
 # This test ensures that the MIR parser parses subregisters in register operands
 # correctly.
 
 --- |
 
   define zeroext i1 @t(i1 %c) {
   entry:
     ret i1 %c
   }
 
 ...
 ---
 name:            t
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr8 }
   - { id: 2, class: gr8 }
 body: |
   bb.0.entry:
     liveins: %edi

llvm/trunk/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir

 # RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
 --- |
 
   define i32 @test(i32 %a) {
   entry:
     %b = alloca i32
     %0 = alloca i32
     store i32 %a, i32* %b
     store i32 2, i32* %0
     %c = load i32, i32* %b
     ret i32 %c
   }
 
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr32 }
 frameInfo:
   maxAlignment:    4
 fixedStack:
   - { id: 0, offset: 0, size: 4, isImmutable: true, isAliased: false }

llvm/trunk/test/CodeGen/MIR/X86/undefined-register-class.mir

 # RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
 # This test ensures that the MIR parser reports an error when it encounters an
 # unknown register class.
 
 --- |
 
   define i32 @test(i32 %a) {
   entry:
     ret i32 %a
   }
 
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   # CHECK: [[@LINE+1]]:20: use of undefined register class or register bank 'gr3200'
   - {id: 0, class: 'gr3200'}
 body: |
   bb.0.entry:
     RETQ %eax
 ...
 

llvm/trunk/test/CodeGen/MIR/X86/undefined-stack-object.mir

 # RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
 --- |
 
   define i32 @test(i32 %a) {
   entry:
     %b = alloca i32
     store i32 %a, i32* %b
     %c = load i32, i32* %b
     ret i32 %c
   }
 
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
 frameInfo:
   maxAlignment:  4
 stack:
   - { id: 0, name: b, size: 4, alignment: 4 }
 body: |
   bb.0.entry:
     %0 = COPY %edi
     ; CHECK: [[@LINE+1]]:13: use of undefined stack object '%stack.2'
     MOV32mr %stack.2, 1, _, 0, _, %0
     %eax = COPY %0
     RETQ %eax
 ...

llvm/trunk/test/CodeGen/MIR/X86/undefined-virtual-register.mir

 # RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
 # This test ensures that the MIR parser reports an error when parsing a
 # reference to an undefined virtual register.
 
 --- |
 
   define i32 @test(i32 %a) {
   entry:
     ret i32 %a
   }
 
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
 body: |
   bb.0.entry:
     %0 = COPY %edi
     ; CHECK: [[@LINE+1]]:17: use of undefined virtual register '%10'
     %eax = COPY %10
     RETQ %eax
 ...
 

llvm/trunk/test/CodeGen/MIR/X86/unexpected-size-non-generic-register-phys.mir

 # RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
 # This test ensures that an error is reported when a register operand is sized
 # but isn't generic, like a physical register.
 
 ---
 name:            test_size_physreg
-isSSA:           true
 registers:
 body: |
   bb.0.entry:
     liveins: %edi
     ; CHECK: [[@LINE+1]]:10: unexpected size on physical register
     %edi(32) = G_ADD i32 %edi, %edi
 ...

llvm/trunk/test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir

 # RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
 # This test ensures that an error is reported when a register operand is sized
 # but isn't generic like a regular virtual register (gr32).
 
 ---
 name:            test_size_regclass
-isSSA:           true
 registers:
   - { id: 0, class: gr32 }
 body: |
   bb.0.entry:
     liveins: %edi
     ; CHECK: [[@LINE+1]]:8: unexpected size on non-generic virtual register
     %0(32) = G_ADD i32 %edi, %edi
 ...

llvm/trunk/test/CodeGen/MIR/X86/unknown-metadata-node.mir

--- |
   !12 = !DILocalVariable(name: "x", arg: 1, scope: !4, file: !5, line: 4, type: !8)
   !13 = !DIExpression()
   !14 = !DILocation(line: 4, scope: !4)
   !15 = !DILocation(line: 8, scope: !4)
 
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
 frameInfo:
   maxAlignment:  4
 stack:
   - { id: 0, name: x.addr, size: 4, alignment: 4 }
 body: |
   bb.0.entry:
     %0 = COPY %edi
     ; CHECK: [[@LINE+1]]:21: use of undefined metadata '!42'
     DBG_VALUE _, 0, !42, !13
     MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
     %eax = COPY %0
     RETQ %eax
 ...

llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir

 # RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
 # This test ensures that an error is reported when an unknown subregister index
 # is encountered.
 
 --- |
 
   define zeroext i1 @t(i1 %c) {
   entry:
     ret i1 %c
   }
 
 ...
 ---
 name:            t
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr8 }
   - { id: 2, class: gr8 }
 body: |
   bb.0.entry:
     ; CHECK: [[@LINE+1]]:35: unknown subregister index 'bit8'
     %0 = INSERT_SUBREG %edi, %al, %subreg.bit8
     RETQ %0
 ...

llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir

 # RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
 # This test ensures that an error is reported when an unknown subregister index
 # is encountered.
 
 --- |
 
   define zeroext i1 @t(i1 %c) {
   entry:
     ret i1 %c
   }
 
 ...
 ---
 name:            t
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr8 }
   - { id: 2, class: gr8 }
 body: |
   bb.0.entry:
     %0 = COPY %edi
     ; CHECK: [[@LINE+1]]:18: use of unknown subregister index 'bit8'
     %1 = COPY %0.bit8
     %2 = AND8ri %1, 1, implicit-def %eflags
     %al = COPY %2
     RETQ %al
 ...

llvm/trunk/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir

 # RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
 
 --- |
 
   define i32 @test(i32 %a) {
   body:
     ret i32 %a
   }
 
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
 # CHECK: [[@LINE+1]]:11: redefinition of virtual register '%0'
   - { id: 0, class: gr32 }
 body: |
   bb.0.body:
     liveins: %edi
 
     %0 = COPY %edi
     %eax = COPY %0
     RETQ %eax
 ...
 

llvm/trunk/test/CodeGen/MIR/X86/virtual-registers.mir

--- |
 
   exit:
     ret i32 %a
   }
 
 ...
 ---
 name:            bar
-isSSA:           true
 tracksRegLiveness: true
 # CHECK:      registers:
 # CHECK-NEXT:   - { id: 0, class: gr32 }
 # CHECK-NEXT:   - { id: 1, class: gr32 }
 # CHECK-NEXT:   - { id: 2, class: gr32 }
 registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr32 }
bb.1.less:
     RETQ %eax
 
   bb.2.exit:
     %eax = COPY %0
     RETQ %eax
 ...
 ---
 name:            foo
-isSSA:           true
 tracksRegLiveness: true
 # CHECK: name: foo
 # CHECK:      registers:
 # CHECK-NEXT:   - { id: 0, class: gr32 }
 # CHECK-NEXT:   - { id: 1, class: gr32 }
 # CHECK-NEXT:   - { id: 2, class: gr32 }
 registers:
   - { id: 2, class: gr32 }

llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir

 
 ...
 ---
 name:            mm_update_next_owner
 alignment:       4
 exposesReturnsTwice: false
 hasInlineAsm:    true
 allVRegsAllocated: true
-isSSA:           false
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 liveins:         
   - { reg: '%x3' }
   - { reg: '%x4' }
 calleeSavedRegisters: [ '%cr2', '%cr3', '%cr4', '%f14', '%f15', '%f16', 
                         '%f17', '%f18', '%f19', '%f20', '%f21', '%f22', 
                         '%f23', '%f24', '%f25', '%f26', '%f27', '%f28', 

llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir

 
 ...
 ---
 name:            test1
 alignment:       4
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: true
-isSSA:           false
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 frameInfo:       
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       64

llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir

--- |
   attributes #0 = { nounwind "target-cpu"="ppc64" }
 
 ...
 ---
 name:            main
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
-isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
   - { id: 0, class: g8rc_and_g8rc_nox0 }
   - { id: 1, class: g8rc_and_g8rc_nox0 }
   - { id: 2, class: gprc }
   - { id: 3, class: gprc }
   - { id: 4, class: gprc }

llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir

 
 ...
 ---
 name:            fn1
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: false
-isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:
   - { id: 0, class: g8rc }
   - { id: 1, class: g8rc }
   - { id: 2, class: g8rc }
   - { id: 3, class: g8rc }
   - { id: 4, class: g8rc }

llvm/trunk/test/CodeGen/X86/eflags-copy-expansion.mir

false:
     ret void
   }
 
 ...
 
 ---
 name:            foo
 allVRegsAllocated: true
-isSSA:           false
 tracksRegLiveness: true
 liveins:
   - { reg: '%edi' }
 body:             |
   bb.0.entry:
     liveins: %edi
     successors: %bb.1.false
     NOOP implicit-def %al

llvm/trunk/test/CodeGen/X86/fixup-bw-copy.mir

define i16 @test_movw_impdef_gr64(i16 %a0) {
     ret i16 %a0
   }
 
 ...
 
 ---
 name:            test_movb_killed
 allVRegsAllocated: true
-isSSA:           false
 tracksRegLiveness: true
 liveins:
   - { reg: '%edi' }
 body:             |
   bb.0 (%ir-block.0):
     liveins: %edi
 
     ; CHECK: %eax = MOV32rr undef %edi, implicit %dil
     %al = MOV8rr killed %dil
     RETQ killed %al
 
 ...
 
 ---
 name:            test_movb_impuse
 allVRegsAllocated: true
-isSSA:           false
 tracksRegLiveness: true
 liveins:
   - { reg: '%edi' }
 body:             |
   bb.0 (%ir-block.0):
     liveins: %edi
 
     ; CHECK: %eax = MOV32rr undef %edi, implicit %dil
     %al = MOV8rr %dil, implicit %edi
     RETQ killed %al
 
 ...
 
 ---
 name:            test_movb_impdef_gr64
 allVRegsAllocated: true
-isSSA:           false
 tracksRegLiveness: true
 liveins:
   - { reg: '%edi' }
 body:             |
   bb.0 (%ir-block.0):
     liveins: %edi
 
     ; CHECK: %eax = MOV32rr undef %edi, implicit %dil, implicit-def %rax
     %al = MOV8rr %dil, implicit-def %rax
     RETQ killed %al
 
 ...
 
 ---
 name:            test_movb_impdef_gr32
 allVRegsAllocated: true
-isSSA:           false
 tracksRegLiveness: true
 liveins:
   - { reg: '%edi' }
 body:             |
   bb.0 (%ir-block.0):
     liveins: %edi
 
     ; CHECK: %eax = MOV32rr undef %edi, implicit %dil
     %al = MOV8rr %dil, implicit-def %eax
     RETQ killed %al
 
 ...
 
 ---
 name:            test_movb_impdef_gr16
 allVRegsAllocated: true
-isSSA:           false
 tracksRegLiveness: true
 liveins:
   - { reg: '%edi' }
 body:             |
   bb.0 (%ir-block.0):
     liveins: %edi
 
     ; CHECK: %eax = MOV32rr undef %edi, implicit %dil
     %al = MOV8rr %dil, implicit-def %ax
     RETQ killed %al
 
 ...
 
 ---
 name:            test_movw_impdef_gr32
 allVRegsAllocated: true
-isSSA:           false
 tracksRegLiveness: true
 liveins:
   - { reg: '%edi' }
 body:             |
   bb.0 (%ir-block.0):
     liveins: %edi
 
     ; CHECK: %eax = MOV32rr undef %edi, implicit %di
     %ax = MOV16rr %di, implicit-def %eax
     RETQ killed %ax
 
 ...
 
 ---
 name:            test_movw_impdef_gr64
 allVRegsAllocated: true
-isSSA:           false
 tracksRegLiveness: true
 liveins:
   - { reg: '%edi' }
 body:             |
   bb.0 (%ir-block.0):
     liveins: %edi
 
     ; CHECK: %eax = MOV32rr undef %edi, implicit %di, implicit-def %rax
     %ax = MOV16rr %di, implicit-def %rax
     RETQ killed %ax
 
 ...

llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir

bb.4.ret_100:
     %eax = MOV32ri 100
     RET 0, %eax
 
 ...
 ---
 name:            imp_null_check_with_bitwise_op_1
 alignment:       4
 allVRegsAllocated: true
-isSSA:           false
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 liveins:
   - { reg: '%rdi' }
   - { reg: '%esi' }
   - { reg: '%rdx' }
 # CHECK: bb.0.entry:
 # CHECK:    %eax = MOV32rm killed %rdx, 1, _, 0, _ :: (volatile load 4 from %ir.ptr)

llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir

 
 ...
 ---
 name:            add
 alignment:       4
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: true
-isSSA:           false
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 liveins:         
   - { reg: '%edi' }
   - { reg: '%esi' }
   - { reg: '%edx' }
   - { reg: '%ecx' }
 frameInfo:       

llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir

 
 ...
 ---
 name:            main
 alignment:       4
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: true
-isSSA:           false
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 liveins:         
   - { reg: '%edi' }
   - { reg: '%rsi' }
 calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx', 
                         '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15', 
                         '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d',