MachineFunction: Remove AllVRegsAllocated property

[MatzeB]

Summary

Originally I wanted to write some MIRParser code to automatically
determine the correct value for AllVRegsAllocated. Then I realized that
it is equivalent to MachineRegisterInfo::getNumVirtRegs() == 0 so there
is no need to track it in a separate property, we can just assert on the
presence of virtregs instead.

It still catches invalid pass usage, is less code and avoids a line in every .mir file.

[dschuff]

Hi Matthias,
This sort of idea (i.e. essentially what you are proposing with this patch) is what we started with, when we began thinking of how to make more existing MI passes handle virtual registers and/or ensure that the right passes are excluded for WebAssembly. @qcolombet and some others really wanted to have something stronger, clearer to readers, and more declarative and/or structural than asserts to ensure there was no confusion. This is in fact the reason that MachineFunctionProperties was invented (the fact that it's now used for isSSA and tracksLiveness was more of a "because it's there" kind of thing).

I would still be amenable to this kind of approach but I'd want Quentin's input first, and we should think a bit about where we might take this in the future either way.
I wouldn't mind helping out either way (and I know I still owe Quentin a cleanup in PEI anyway).

[MatzeB]

In D22718#494761, @dschuff wrote:

Hi Matthias,
This sort of idea (i.e. essentially what you are proposing with this patch) is what we started with, when we began thinking of how to make more existing MI passes handle virtual registers and/or ensure that the right passes are excluded for WebAssembly. @qcolombet and some others really wanted to have something stronger, clearer to readers, and more declarative and/or structural than asserts to ensure there was no confusion. This is in fact the reason that MachineFunctionProperties was invented (the fact that it's now used for isSSA and tracksLiveness was more of a "because it's there" kind of thing).

I would still be amenable to this kind of approach but I'd want Quentin's input first, and we should think a bit about where we might take this in the future either way.
I wouldn't mind helping out either way (and I know I still owe Quentin a cleanup in PEI anyway).

I did not see what getRequiredProperties() adds over a simple assert, so I went for that in my patch. But that's not my main issue.

My main issue with the current code is that the information in the AllVRegsAllocated property is redundant. So at the very least we should find a way that we do not need to "manually" maintain the AllVRegsAllocated flag.

[kparzysz]

The AllVRegsAllocated property is a convenient way of determining whether the code runs after register allocation or not. It is possible for post-RA code to temporarily have virtual registers (for example in frame lowering), so just counting the number of virtual registers may not be accurate.

[MatzeB]

In D22718#495162, @kparzysz wrote:

The AllVRegsAllocated property is a convenient way of determining whether the code runs after register allocation or not. It is possible for post-RA code to temporarily have virtual registers (for example in frame lowering), so just counting the number of virtual registers may not be accurate.

Sure passes can temporarily use virtual registers but in between passes there is no reason why virtual registers exist.

On the other hand I would find it very troubling if "AllVRegsAllocated" would just have an abstract meaning of a pass that runs after the register allocator. Why would is be important to run a certain place in the pass pipeline? It is important that the machine function has certain properties like no virtual registers used or no phi instructions being present. An abstract property of being run behind the register allocator seems less useful to me than a concrete property about the machine function.

[kparzysz]

In D22718#495216, @MatzeB wrote:

On the other hand I would find it very troubling if "AllVRegsAllocated" would just have an abstract meaning of a pass that runs after the register allocator. Why would is be important to run a certain place in the pass pipeline?

For a pass, yes, altough there are passes that can run in both scenarios (MachineLICM, IIRC). What I was thinking about were utility routines that can be called at various times. In our internal Hexagon repo we have to maintain super-register liveness via implicit operands. We have a function that updates those and it's called from places like, for example, loadRegFromStackSlot. This function does not know where in the optimization pipleline it was called from. Checking whether the destination register is physical or virtual is not sufficient, because we really only want to do this after RA has completed. Once we get the subregister liveness tracking enabled, this problem will go away, but in general it shows that there can be cases whether the pre- vs post-RA status may be useful to know.

[kparzysz]

Btw, if you really want to remove this property, that's fine. We will just keep it around in our internal repo until we no longer need it. I'm just indicating that this property may be useful. Ultimately, if it's removed now and the need for it arises later, it may be brought back.

[MatzeB]

In D22718#495247, @kparzysz wrote:

In D22718#495216, @MatzeB wrote:

On the other hand I would find it very troubling if "AllVRegsAllocated" would just have an abstract meaning of a pass that runs after the register allocator. Why would is be important to run a certain place in the pass pipeline?

For a pass, yes, altough there are passes that can run in both scenarios (MachineLICM, IIRC). What I was thinking about were utility routines that can be called at various times. In our internal Hexagon repo we have to maintain super-register liveness via implicit operands. We have a function that updates those and it's called from places like, for example, loadRegFromStackSlot. This function does not know where in the optimization pipleline it was called from. Checking whether the destination register is physical or virtual is not sufficient, because we really only want to do this after RA has completed. Once we get the subregister liveness tracking enabled, this problem will go away, but in general it shows that there can be cases whether the pre- vs post-RA status may be useful to know.

I think if you look think about .mir files the it becomes clear why an attribute on a machine function is strange:

file1.mir:
...
name: foo
AllVRegsAllocated: true
body: |
  bb.0:
    RETQ
---

file2.mir
...
name: foo
AllVRegsAllocated: false
body: |
  bb.0:
    RETQ
---

Today those are two different functions, but why is that difference meaningful? Also typing the "AllVRegsAllocated: " seems unnecessary.

[MatzeB]

In D22718#495247, @kparzysz wrote:

In D22718#495216, @MatzeB wrote:

On the other hand I would find it very troubling if "AllVRegsAllocated" would just have an abstract meaning of a pass that runs after the register allocator. Why would is be important to run a certain place in the pass pipeline?

For a pass, yes, altough there are passes that can run in both scenarios (MachineLICM, IIRC). What I was thinking about were utility routines that can be called at various times. In our internal Hexagon repo we have to maintain super-register liveness via implicit operands. We have a function that updates those and it's called from places like, for example, loadRegFromStackSlot. This function does not know where in the optimization pipleline it was called from. Checking whether the destination register is physical or virtual is not sufficient, because we really only want to do this after RA has completed.

I find this a minor problem to solve if the function works fine before RA and is just unnecessary. There are so many other function preconditions that we do not explicitely test or that may not be possible to test. I'm not saying checking preconditions isn't useful but I don't find it a convincing argument in this case to keep the AllVRegsAllocated property around.

[kparzysz]

Yes, it is strange. Whether the RA has already run or not is not really a state of the function, I agree with that. I'm not opposed to this change, I'm just bringing up a potential consideration, that's all.

[MatzeB]

Abandon in favor of https://reviews.llvm.org/D23850

include/llvm/CodeGen/MIRYamlMapping.h

template <> struct MappingTraits<MachineFrameInfo> {
   }
 };
 
 struct MachineFunction {
   StringRef Name;
   unsigned Alignment = 0;
   bool ExposesReturnsTwice = false;
   bool HasInlineAsm = false;
-  // MachineFunctionProperties
-  bool AllVRegsAllocated = false;
   // Register information
   bool IsSSA = false;
   bool TracksRegLiveness = false;
   bool TracksSubRegLiveness = false;
   std::vector<VirtualRegisterDefinition> VirtualRegisters;
   std::vector<MachineFunctionLiveIn> LiveIns;
   Optional<std::vector<FlowStringValue>> CalleeSavedRegisters;
   // TODO: Serialize the various register masks.
   // Frame information
   MachineFrameInfo FrameInfo;
   std::vector<FixedMachineStackObject> FixedStackObjects;
   std::vector<MachineStackObject> StackObjects;
   std::vector<MachineConstantPoolValue> Constants; /// Constant pool.
   MachineJumpTable JumpTableInfo;
   BlockStringValue Body;
 };
 
 template <> struct MappingTraits<MachineFunction> {
   static void mapping(IO &YamlIO, MachineFunction &MF) {
     YamlIO.mapRequired("name", MF.Name);
     YamlIO.mapOptional("alignment", MF.Alignment);
     YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice);
     YamlIO.mapOptional("hasInlineAsm", MF.HasInlineAsm);
-    YamlIO.mapOptional("allVRegsAllocated", MF.AllVRegsAllocated);
     YamlIO.mapOptional("isSSA", MF.IsSSA);
     YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);
     YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness);
     YamlIO.mapOptional("registers", MF.VirtualRegisters);
     YamlIO.mapOptional("liveins", MF.LiveIns);
     YamlIO.mapOptional("calleeSavedRegisters", MF.CalleeSavedRegisters);
     YamlIO.mapOptional("frameInfo", MF.FrameInfo);
     YamlIO.mapOptional("fixedStack", MF.FixedStackObjects);

include/llvm/CodeGen/MachineFunction.h

static Ty *create(BumpPtrAllocator &Allocator, MachineFunction &MF) {
     return new (Allocator.Allocate<Ty>()) Ty(MF);
   }
 };
 
 /// Properties which a MachineFunction may have at a given point in time.
 /// Each of these has checking code in the MachineVerifier, and passes can
 /// require that a property be set.
 class MachineFunctionProperties {
-  // TODO: Add MachineVerifier checks for AllVRegsAllocated
   // TODO: Add a way to print the properties and make more useful error messages
   // Possible TODO: Allow targets to extend this (perhaps by allowing the
   // constructor to specify the size of the bit vector)
   // Possible TODO: Allow requiring the negative (e.g. VRegsAllocated could be
   // stated as the negative of "has vregs"
 
 public:
   // The properties are stated in "positive" form; i.e. a pass could require
   // that the property hold, but not that it does not hold.
 
   // Property descriptions:
   // IsSSA: True when the machine function is in SSA form and virtual registers
   //  have a single def.
   // TracksLiveness: True when tracking register liveness accurately.
   //  While this property is set, register liveness information in basic block
   //  live-in lists and machine instruction operands (e.g. kill flags, implicit
   //  defs) is accurate. This means it can be used to change the code in ways
   //  that affect the values in registers, for example by the register
   //  scavenger.
   //  When this property is clear, liveness is no longer reliable.
-  // AllVRegsAllocated: All virtual registers have been allocated; i.e. all
-  //  register operands are physical registers.
   enum class Property : unsigned {
     IsSSA,
     TracksLiveness,
-    AllVRegsAllocated,
     LastProperty,
   };
 
   bool hasProperty(Property P) const {
     return Properties[static_cast<unsigned>(P)];
   }
   MachineFunctionProperties &set(Property P) {
     Properties.set(static_cast<unsigned>(P));
public:
   void setHasInlineAsm(bool B) {
     HasInlineAsm = B;
   }
 
   /// Get the function properties
   const MachineFunctionProperties &getProperties() const { return Properties; }
   MachineFunctionProperties &getProperties() { return Properties; }
 
+  /// Returns true if any virtual register is used or defined.
+  bool hasVirtRegs() const;
+
   /// getInfo - Keep track of various per-function pieces of information for
   /// backends that would like to do so.
   ///
   template<typename Ty>
   Ty *getInfo() {
     if (!MFInfo)
       MFInfo = Ty::template create<Ty>(Allocator, *this);
     return static_cast<Ty*>(MFInfo);

lib/CodeGen/ExecutionDepsFix.cpp

public:
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesAll();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
-  MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::AllVRegsAllocated);
-  }
-
   const char *getPassName() const override {
     return "Execution dependency fix";
   }
 
 private:
   iterator_range<SmallVectorImpl<int>::const_iterator>
   regIndices(unsigned Reg) const;
 
for (int rx : regIndices(mo.getReg())) {
         kill(rx);
         setLiveReg(rx, dv);
       }
     }
   }
 }
 
 bool ExeDepsFix::runOnMachineFunction(MachineFunction &mf) {
+  assert(!mf.hasVirtRegs() && "Registers Allocated");
   if (skipFunction(*mf.getFunction()))
     return false;
   MF = &mf;
   TII = MF->getSubtarget().getInstrInfo();
   TRI = MF->getSubtarget().getRegisterInfo();
   LiveRegs = nullptr;
   assert(NumRegs == RC->getNumRegs() && "Bad regclass");
 

lib/CodeGen/FuncletLayout.cpp

 class FuncletLayout : public MachineFunctionPass {
 public:
   static char ID; // Pass identification, replacement for typeid
   FuncletLayout() : MachineFunctionPass(ID) {
     initializeFuncletLayoutPass(*PassRegistry::getPassRegistry());
   }
 
   bool runOnMachineFunction(MachineFunction &F) override;
-  MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::AllVRegsAllocated);
-  }
 };
 }
 
 char FuncletLayout::ID = 0;
 char &llvm::FuncletLayoutID = FuncletLayout::ID;
 INITIALIZE_PASS(FuncletLayout, "funclet-layout",
                 "Contiguously Lay Out Funclets", false, false)
 
 bool FuncletLayout::runOnMachineFunction(MachineFunction &F) {
+  assert(!F.hasVirtRegs() && "Registers Allocated");
   DenseMap<const MachineBasicBlock *, int> FuncletMembership =
       getFuncletMembership(F);
   if (FuncletMembership.empty())
     return false;
 
   F.sort([&](MachineBasicBlock &X, MachineBasicBlock &Y) {
     auto FuncletX = FuncletMembership.find(&X);
     auto FuncletY = FuncletMembership.find(&Y);
     assert(FuncletX != FuncletMembership.end());
     assert(FuncletY != FuncletMembership.end());
     return FuncletX->second < FuncletY->second;
   });
 
   // Conservatively assume we changed something.
   return true;
 }

lib/CodeGen/IfConversion.cpp

public:
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.addRequired<MachineBlockFrequencyInfo>();
       AU.addRequired<MachineBranchProbabilityInfo>();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 
     bool runOnMachineFunction(MachineFunction &MF) override;
 
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
-
   private:
     bool ReverseBranchCondition(BBInfo &BBI);
     bool ValidSimple(BBInfo &TrueBBI, unsigned &Dups,
                      BranchProbability Prediction) const;
     bool ValidTriangle(BBInfo &TrueBBI, BBInfo &FalseBBI,
                        bool FalseBranch, unsigned &Dups,
                        BranchProbability Prediction) const;
     bool ValidDiamond(BBInfo &TrueBBI, BBInfo &FalseBBI,

lib/CodeGen/ImplicitNullChecks.cpp

ImplicitNullChecks() : MachineFunctionPass(ID) {
     initializeImplicitNullChecksPass(*PassRegistry::getPassRegistry());
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.addRequired<AAResultsWrapperPass>();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
-
-  MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::AllVRegsAllocated);
-  }
 };
 
 /// \brief Detect re-ordering hazards and dependencies.
 ///
 /// This class keeps track of defs and uses, and can be queried if a given
 /// machine instruction can be re-ordered from after the machine instructions
 /// seen so far to before them.
 class HazardDetector {
if (MO.isReg() && MO.getReg()) {
             return false;  // We found a write-after-read
     }
   }
 
   return true;
 }
 
 bool ImplicitNullChecks::runOnMachineFunction(MachineFunction &MF) {
+  assert(!MF.hasVirtRegs() && "Registers Allocated");
   TII = MF.getSubtarget().getInstrInfo();
   TRI = MF.getRegInfo().getTargetRegisterInfo();
   MMI = &MF.getMMI();
   AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
 
   SmallVector<NullCheck, 16> NullCheckList;
 
   for (auto &MBB : MF)

lib/CodeGen/LiveDebugValues.cpp

public:
 
   /// Default construct and initialize the pass.
   LiveDebugValues();
 
   /// Tell the pass manager which passes we depend on and what
   /// information we preserve.
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
-  MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::AllVRegsAllocated);
-  }
-
   /// Print to ostream with a message.
   void printVarLocInMBB(const MachineFunction &MF, const VarLocInMBB &V,
                         const VarLocMap &VarLocIDs, const char *msg,
                         raw_ostream &Out) const;
 
   /// Calculate the liveness information for the given machine function.
   bool runOnMachineFunction(MachineFunction &MF) override;
 };
bool LiveDebugValues::ExtendRanges(MachineFunction &MF) {
   }
 
   DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs, "Final OutLocs", dbgs()));
   DEBUG(printVarLocInMBB(MF, InLocs, VarLocIDs, "Final InLocs", dbgs()));
   return Changed;
 }
 
 bool LiveDebugValues::runOnMachineFunction(MachineFunction &MF) {
+  assert(!MF.hasVirtRegs() && "Registers Allocated");
   TRI = MF.getSubtarget().getRegisterInfo();
   TII = MF.getSubtarget().getInstrInfo();
 
   bool Changed = false;
 
   Changed |= ExtendRanges(MF);
 
   return Changed;
 }

lib/CodeGen/MIRParser/MIRParser.cpp

if (It == Functions.end())
     return error(Twine("no machine function information for function '") +
                  MF.getName() + "' in the MIR file");
   // TODO: Recreate the machine function.
   const yaml::MachineFunction &YamlMF = *It->getValue();
   if (YamlMF.Alignment)
     MF.setAlignment(YamlMF.Alignment);
   MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice);
   MF.setHasInlineAsm(YamlMF.HasInlineAsm);
-  if (YamlMF.AllVRegsAllocated)
-    MF.getProperties().set(MachineFunctionProperties::Property::AllVRegsAllocated);
   PerFunctionMIParsingState PFS(MF, SM, IRSlots);
   if (initializeRegisterInfo(PFS, YamlMF))
     return true;
   if (!YamlMF.Constants.empty()) {
     auto *ConstantPool = MF.getConstantPool();
     assert(ConstantPool && "Constant pool must be created");
     if (initializeConstantPool(PFS, *ConstantPool, YamlMF))
       return true;

lib/CodeGen/MIRPrinter.cpp

 void MIRPrinter::print(const MachineFunction &MF) {
   initRegisterMaskIds(MF);
 
   yaml::MachineFunction YamlMF;
   YamlMF.Name = MF.getName();
   YamlMF.Alignment = MF.getAlignment();
   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
   YamlMF.HasInlineAsm = MF.hasInlineAsm();
-  YamlMF.AllVRegsAllocated = MF.getProperties().hasProperty(
-      MachineFunctionProperties::Property::AllVRegsAllocated);
 
   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
   ModuleSlotTracker MST(MF.getFunction()->getParent());
   MST.incorporateFunction(*MF.getFunction());
   convert(MST, YamlMF.FrameInfo, *MF.getFrameInfo());
   convertStackObjects(YamlMF, *MF.getFrameInfo(), MF.getMMI(), MST,
                       MF.getSubtarget().getRegisterInfo());
   if (const auto *ConstantPool = MF.getConstantPool())

lib/CodeGen/MachineCopyPropagation.cpp

public:
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.setPreservesCFG();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 
     bool runOnMachineFunction(MachineFunction &MF) override;
 
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
-
   private:
     void ClobberRegister(unsigned Reg);
     void CopyPropagateBlock(MachineBasicBlock &MBB);
     bool eraseIfRedundant(MachineInstr &Copy, unsigned Src, unsigned Def);
 
     /// Candidates for deletion.
     SmallSetVector<MachineInstr*, 8> MaybeDeadCopies;
     /// Def -> available copies map.
void MachineCopyPropagation::CopyPropagateBlock(MachineBasicBlock &MBB) {
 
   MaybeDeadCopies.clear();
   AvailCopyMap.clear();
   CopyMap.clear();
   SrcMap.clear();
 }
 
 bool MachineCopyPropagation::runOnMachineFunction(MachineFunction &MF) {
+  assert(!MF.hasVirtRegs() && "Registers Allocated");
   if (skipFunction(*MF.getFunction()))
     return false;
 
   Changed = false;
 
   TRI = MF.getSubtarget().getRegisterInfo();
   TII = MF.getSubtarget().getInstrInfo();
   MRI = &MF.getRegInfo();
 
   for (MachineBasicBlock &MBB : MF)
     CopyPropagateBlock(MBB);
 
   return Changed;
 }
 

lib/CodeGen/MachineFunction.cpp

if (OnlySet && !HasProperty)
       continue;
     switch(static_cast<Property>(i)) {
       case Property::IsSSA:
         ROS << (HasProperty ? "SSA, " : "Post SSA, ");
         break;
       case Property::TracksLiveness:
         ROS << (HasProperty ? "" : "not ") << "tracking liveness, ";
         break;
-      case Property::AllVRegsAllocated:
-        ROS << (HasProperty ? "AllVRegsAllocated" : "HasVRegs");
-        break;
       default:
         break;
     }
   }
 #endif
 }
 
 //===----------------------------------------------------------------------===//

 }
 #endif
 
 StringRef MachineFunction::getName() const {
   assert(getFunction() && "No function!");
   return getFunction()->getName();
 }
 
+bool MachineFunction::hasVirtRegs() const {
+  return getRegInfo().getNumVirtRegs() > 0;
+}
+
 void MachineFunction::print(raw_ostream &OS, const SlotIndexes *Indexes) const {
   OS << "# Machine code for function " << getName() << ": ";
   OS << "Properties: <";
   getProperties().print(OS);
   OS << ">\n";
 
   // Print Frame Information
   FrameInfo->print(*this, OS);

lib/CodeGen/MachineVerifier.cpp

struct MachineVerifier {
     void verifyLiveRangeSegment(const LiveRange&,
                                 const LiveRange::const_iterator I, unsigned,
                                 unsigned);
     void verifyLiveRange(const LiveRange&, unsigned, LaneBitmask LaneMask = 0);
 
     void verifyStackFrame();
 
     void verifySlotIndexes() const;
-    void verifyProperties(const MachineFunction &MF);
   };
 
   struct MachineVerifierPass : public MachineFunctionPass {
     static char ID; // Pass ID, replacement for typeid
     const std::string Banner;
 
     MachineVerifierPass(const std::string &banner = nullptr)
       : MachineFunctionPass(ID), Banner(banner) {
void MachineVerifier::verifySlotIndexes() const {
   SlotIndex Last;
   for (SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin(),
        E = Indexes->MBBIndexEnd(); I != E; ++I) {
     assert(!Last.isValid() || I->first > Last);
     Last = I->first;
   }
 }
 
-void MachineVerifier::verifyProperties(const MachineFunction &MF) {
-  // If a pass has introduced virtual registers without clearing the
-  // AllVRegsAllocated property (or set it without allocating the vregs)
-  // then report an error.
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::AllVRegsAllocated) &&
-      MRI->getNumVirtRegs()) {
-    report(
-        "Function has AllVRegsAllocated property but there are VReg operands",
-        &MF);
-  }
-}
-
 unsigned MachineVerifier::verify(MachineFunction &MF) {
   foundErrors = 0;
 
   this->MF = &MF;
   TM = &MF.getTarget();
   TII = MF.getSubtarget().getInstrInfo();
   TRI = MF.getSubtarget().getRegisterInfo();
   MRI = &MF.getRegInfo();
 
   LiveVars = nullptr;
   LiveInts = nullptr;
   LiveStks = nullptr;
   Indexes = nullptr;
   if (PASS) {
     LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
     // We don't want to verify LiveVariables if LiveIntervals is available.
     if (!LiveInts)
       LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
     LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
     Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
   }
 
   verifySlotIndexes();
 
-  verifyProperties(MF);
-
   visitMachineFunctionBefore();
   for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
        MFI!=MFE; ++MFI) {
     visitMachineBasicBlockBefore(&*MFI);
     // Keep track of the current bundle header.
     const MachineInstr *CurBundle = nullptr;
     // Do we expect the next instruction to be part of the same bundle?
     bool InBundle = false;

lib/CodeGen/PatchableFunction.cpp

 namespace {
 struct PatchableFunction : public MachineFunctionPass {
   static char ID; // Pass identification, replacement for typeid
   PatchableFunction() : MachineFunctionPass(ID) {
     initializePatchableFunctionPass(*PassRegistry::getPassRegistry());
   }
 
   bool runOnMachineFunction(MachineFunction &F) override;
-   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::AllVRegsAllocated);
-  }
 };
 }
 
 /// Returns true if instruction \p MI will not result in actual machine code
 /// instructions.
 static bool doesNotGeneratecode(const MachineInstr &MI) {
   // TODO: Introduce an MCInstrDesc flag for this
   switch (MI.getOpcode()) {
   default: return false;
   case TargetOpcode::IMPLICIT_DEF:
   case TargetOpcode::KILL:
   case TargetOpcode::CFI_INSTRUCTION:
   case TargetOpcode::EH_LABEL:
   case TargetOpcode::GC_LABEL:
   case TargetOpcode::DBG_VALUE:
     return true;
   }
 }
 
 bool PatchableFunction::runOnMachineFunction(MachineFunction &MF) {
+  assert(!MF.hasVirtRegs() && "Registers Allocated");
   if (!MF.getFunction()->hasFnAttribute("patchable-function"))
     return false;
 
 #ifndef NDEBUG
   Attribute PatchAttr = MF.getFunction()->getFnAttribute("patchable-function");
   StringRef PatchType = PatchAttr.getValueAsString();
   assert(PatchType == "prologue-short-redirect" && "Only possibility today!");
 #endif

lib/CodeGen/PostRASchedulerList.cpp

void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.addRequired<TargetPassConfig>();
       AU.addRequired<MachineDominatorTree>();
       AU.addPreserved<MachineDominatorTree>();
       AU.addRequired<MachineLoopInfo>();
       AU.addPreserved<MachineLoopInfo>();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
-
     bool runOnMachineFunction(MachineFunction &Fn) override;
 
   private:
     bool enablePostRAScheduler(
         const TargetSubtargetInfo &ST, CodeGenOpt::Level OptLevel,
         TargetSubtargetInfo::AntiDepBreakMode &Mode,
         TargetSubtargetInfo::RegClassVector &CriticalPathRCs) const;
   };
bool PostRAScheduler::enablePostRAScheduler(
   if (EnablePostRAScheduler.getPosition() > 0)
     return EnablePostRAScheduler;
 
   return ST.enablePostRAScheduler() &&
          OptLevel >= ST.getOptLevelToEnablePostRAScheduler();
 }
 
 bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
+  assert(!Fn.hasVirtRegs() && "Registers Allocated");
   if (skipFunction(*Fn.getFunction()))
     return false;
 
   TII = Fn.getSubtarget().getInstrInfo();
   MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
   AliasAnalysis *AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
   TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>();
 

lib/CodeGen/PrologEpilogInserter.cpp

if (TM && (!TM->usesPhysRegsForPEI())) {
       SpillCalleeSavedRegisters = doSpillCalleeSavedRegs;
       ScavengeFrameVirtualRegs = doScavengeFrameVirtualRegs;
       UsesCalleeSaves = true;
     }
   }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
-  MachineFunctionProperties getRequiredProperties() const override {
-    MachineFunctionProperties MFP;
-    if (UsesCalleeSaves)
-      MFP.set(MachineFunctionProperties::Property::AllVRegsAllocated);
-    return MFP;
-  }
-
   /// runOnMachineFunction - Insert prolog/epilog code and replace abstract
   /// frame indexes with appropriate references.
   ///
   bool runOnMachineFunction(MachineFunction &Fn) override;
 
 private:
   std::function<void(MachineFunction &MF, RegScavenger *RS,
                      unsigned &MinCSFrameIndex, unsigned &MaxCSFrameIndex,

 
 /// StackObjSet - A set of stack object indexes
 typedef SmallSetVector<int, 8> StackObjSet;
 
 /// runOnMachineFunction - Insert prolog/epilog code and replace abstract
 /// frame indexes with appropriate references.
 ///
 bool PEI::runOnMachineFunction(MachineFunction &Fn) {
+  assert(!UsesCalleeSaves || !Fn.hasVirtRegs() && "Registers Allocated");
   const Function* F = Fn.getFunction();
   const TargetRegisterInfo *TRI = Fn.getSubtarget().getRegisterInfo();
   const TargetFrameLowering *TFI = Fn.getSubtarget().getFrameLowering();
 
   RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : nullptr;
   FrameIndexVirtualScavenging = TRI->requiresFrameIndexScavenging(Fn);
 
   // Calculate the MaxCallFrameSize and AdjustsStack variables for the

lib/CodeGen/RegAllocFast.cpp

const char *getPassName() const override {
       return "Fast Register Allocator";
     }
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.setPreservesCFG();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 
-    MachineFunctionProperties getSetProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
-
   private:
     bool runOnMachineFunction(MachineFunction &Fn) override;
     void AllocateBasicBlock();
     void handleThroughOperands(MachineInstr *MI,
                                SmallVectorImpl<unsigned> &VirtDead);
     int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
     bool isLastUseOfLocalReg(MachineOperand&);
 

lib/CodeGen/StackMapLivenessAnalysis.cpp

public:
 
   /// \brief Default construct and initialize the pass.
   StackMapLiveness();
 
   /// \brief Tell the pass manager which passes we depend on and what
   /// information we preserve.
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
-  MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::AllVRegsAllocated);
-  }
-
   /// \brief Calculate the liveness information for the given machine function.
   bool runOnMachineFunction(MachineFunction &MF) override;
 
 private:
   /// \brief Performs the actual liveness calculation for the function.
   bool calculateLiveness(MachineFunction &MF);
 
   /// \brief Add the current register live set to the instruction.
void StackMapLiveness::getAnalysisUsage(AnalysisUsage &AU) const {
   // We preserve all information.
   AU.setPreservesAll();
   AU.setPreservesCFG();
   MachineFunctionPass::getAnalysisUsage(AU);
 }
 
 /// Calculate the liveness information for the given machine function.
 bool StackMapLiveness::runOnMachineFunction(MachineFunction &MF) {
+  assert(!MF.hasVirtRegs() && "Registers Allocated");
   if (!EnablePatchPointLiveness)
     return false;
 
   DEBUG(dbgs() << "********** COMPUTING STACKMAP LIVENESS: " << MF.getName()
                << " **********\n");
   TRI = MF.getSubtarget().getRegisterInfo();
   ++NumStackMapFuncVisited;
 

lib/CodeGen/VirtRegMap.cpp

 
 public:
   static char ID;
   VirtRegRewriter() : MachineFunctionPass(ID) {}
 
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
   bool runOnMachineFunction(MachineFunction&) override;
-  MachineFunctionProperties getSetProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::AllVRegsAllocated);
-  }
 };
 } // end anonymous namespace
 
 char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
 
 INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter",
                       "Virtual Register Rewriter", false, false)
 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)

lib/Target/AArch64/AArch64A53Fix835769.cpp

class AArch64A53Fix835769 : public MachineFunctionPass {
   const TargetInstrInfo *TII;
 
 public:
   static char ID;
   explicit AArch64A53Fix835769() : MachineFunctionPass(ID) {}
 
   bool runOnMachineFunction(MachineFunction &F) override;
 
-  MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::AllVRegsAllocated);
-  }
-
   const char *getPassName() const override {
     return "Workaround A53 erratum 835769 pass";
   }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
 private:
   bool runOnBasicBlock(MachineBasicBlock &MBB);
 };
 char AArch64A53Fix835769::ID = 0;
 
 } // end anonymous namespace
 
 //===----------------------------------------------------------------------===//
 
 bool
 AArch64A53Fix835769::runOnMachineFunction(MachineFunction &F) {
+  assert(!F.hasVirtRegs() && "Registers Allocated");
   DEBUG(dbgs() << "***** AArch64A53Fix835769 *****\n");
   bool Changed = false;
   TII = F.getSubtarget().getInstrInfo();
 
   for (auto &MBB : F) {
     Changed |= runOnBasicBlock(MBB);
   }
   return Changed;

lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp

 public:
   static char ID;
   explicit AArch64A57FPLoadBalancing() : MachineFunctionPass(ID) {
     initializeAArch64A57FPLoadBalancingPass(*PassRegistry::getPassRegistry());
   }
 
   bool runOnMachineFunction(MachineFunction &F) override;
 
-  MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::AllVRegsAllocated);
-  }
-
   const char *getPassName() const override {
     return "A57 FP Anti-dependency breaker";
   }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
     MachineFunctionPass::getAnalysisUsage(AU);
   }

 
 };
 
 } // end anonymous namespace
 
 //===----------------------------------------------------------------------===//
 
 bool AArch64A57FPLoadBalancing::runOnMachineFunction(MachineFunction &F) {
+  assert(!F.hasVirtRegs() && "Registers Allocated");
   if (skipFunction(*F.getFunction()))
     return false;
 
   if (!F.getSubtarget<AArch64Subtarget>().balanceFPOps())
     return false;
 
   bool Changed = false;
   DEBUG(dbgs() << "***** AArch64A57FPLoadBalancing *****\n");

lib/Target/AArch64/AArch64CollectLOH.cpp

 struct AArch64CollectLOH : public MachineFunctionPass {
   static char ID;
   AArch64CollectLOH() : MachineFunctionPass(ID) {
     initializeAArch64CollectLOHPass(*PassRegistry::getPassRegistry());
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
-  MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::AllVRegsAllocated);
-  }
-
   const char *getPassName() const override {
     return AARCH64_COLLECT_LOH_NAME;
   }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesAll();
     MachineFunctionPass::getAnalysisUsage(AU);
     AU.addRequired<MachineDominatorTree>();
for (const MachineInstr &MI : MBB) {
             DEBUG(dbgs() << "Register: " << PrintReg(*AI, TRI) << '\n');
           }
       }
     }
   }
 }
 
 bool AArch64CollectLOH::runOnMachineFunction(MachineFunction &MF) {
+  assert(!MF.hasVirtRegs() && "Registers Allocated");
   if (skipFunction(*MF.getFunction()))
     return false;
 
   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
   const MachineDominatorTree *MDT = &getAnalysis<MachineDominatorTree>();
 
   MapRegToId RegToId;
   MapIdToReg IdToReg;

lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp

public:
   static char ID; // Pass identification, replacement for typeid.
   explicit AArch64DeadRegisterDefinitions() : MachineFunctionPass(ID) {
     initializeAArch64DeadRegisterDefinitionsPass(
         *PassRegistry::getPassRegistry());
   }
 
   bool runOnMachineFunction(MachineFunction &F) override;
 
-  MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::AllVRegsAllocated);
-  }
-
   const char *getPassName() const override { return AARCH64_DEAD_REG_DEF_NAME; }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 };
 char AArch64DeadRegisterDefinitions::ID = 0;
for (MachineInstr &MI : MBB) {
     }
   }
   return Changed;
 }
 
 // Scan the function for instructions that have a dead definition of a
 // register. Replace that register with the zero register when possible.
 bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
+  assert(!MF.hasVirtRegs() && "Registers Allocated");
   TRI = MF.getSubtarget().getRegisterInfo();
   bool Changed = false;
   DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n");
 
   if (skipFunction(*MF.getFunction()))
     return false;
 
   for (auto &MBB : MF)
     if (processMachineBasicBlock(MBB))
       Changed = true;
   return Changed;
 }
 
 FunctionPass *llvm::createAArch64DeadRegisterDefinitions() {
   return new AArch64DeadRegisterDefinitions();
 }

lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

struct AArch64LoadStoreOpt : public MachineFunctionPass {
 
   // Find and promote load instructions which read directly from store.
   bool tryToPromoteLoadFromStore(MachineBasicBlock::iterator &MBBI);
 
   bool optimizeBlock(MachineBasicBlock &MBB, bool enableNarrowLdOpt);
 
   bool runOnMachineFunction(MachineFunction &Fn) override;
 
-  MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::AllVRegsAllocated);
-  }
-
   const char *getPassName() const override {
     return AARCH64_LOAD_STORE_OPT_NAME;
   }
 };
 char AArch64LoadStoreOpt::ID = 0;
 } // namespace
 
 INITIALIZE_PASS(AArch64LoadStoreOpt, "aarch64-ldst-opt",
for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
     }
     }
   }
 
   return Modified;
 }
 
 bool AArch64LoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
+  assert(!Fn.hasVirtRegs() && "Registers Allocated");
   if (skipFunction(*Fn.getFunction()))
     return false;
 
   Subtarget = &static_cast<const AArch64Subtarget &>(Fn.getSubtarget());
   TII = static_cast<const AArch64InstrInfo *>(Subtarget->getInstrInfo());
   TRI = Subtarget->getRegisterInfo();
 
   // Resize the modified and used register bitfield trackers.  We do this once

lib/Target/AArch64/AArch64RedundantCopyElimination.cpp

class AArch64RedundantCopyElimination : public MachineFunctionPass {
   const MachineRegisterInfo *MRI;
   const TargetRegisterInfo *TRI;
 
 public:
   static char ID;
   AArch64RedundantCopyElimination() : MachineFunctionPass(ID) {}
   bool optimizeCopy(MachineBasicBlock *MBB);
   bool runOnMachineFunction(MachineFunction &MF) override;
-  MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::AllVRegsAllocated);
-  }
   const char *getPassName() const override {
     return "AArch64 Redundant Copy Elimination";
   }
 };
 char AArch64RedundantCopyElimination::ID = 0;
 }
 
 INITIALIZE_PASS(AArch64RedundantCopyElimination, "aarch64-copyelim",
for (MachineInstr &MMI :
        make_range(MBB->begin()->getIterator(), LastChange->getIterator()))
     MMI.clearRegisterKills(SmallestDef, TRI);
 
   return true;
 }
 
 bool AArch64RedundantCopyElimination::runOnMachineFunction(
     MachineFunction &MF) {
+  assert(!MF.hasVirtRegs() && "Registers Allocated");
   if (skipFunction(*MF.getFunction()))
     return false;
   TRI = MF.getSubtarget().getRegisterInfo();
   MRI = &MF.getRegInfo();
   bool Changed = false;
   for (MachineBasicBlock &MBB : MF)
     Changed |= optimizeCopy(&MBB);
   return Changed;
 }
 
 FunctionPass *llvm::createAArch64RedundantCopyEliminationPass() {
   return new AArch64RedundantCopyElimination();
 }

lib/Target/ARM/ARMConstantIslandPass.cpp

class ARMConstantIslands : public MachineFunctionPass {
     bool isThumb1;
     bool isThumb2;
   public:
     static char ID;
     ARMConstantIslands() : MachineFunctionPass(ID) {}
 
     bool runOnMachineFunction(MachineFunction &MF) override;
 
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
-
     const char *getPassName() const override {
       return "ARM constant island placement and branch shortening pass";
     }
 
   private:
     void doInitialConstPlacement(std::vector<MachineInstr *> &CPEMIs);
     void doInitialJumpTablePlacement(std::vector<MachineInstr *> &CPEMIs);
     bool BBHasFallthrough(MachineBasicBlock *MBB);

 
 /// createARMConstantIslandPass - returns an instance of the constpool
 /// island pass.
 FunctionPass *llvm::createARMConstantIslandPass() {
   return new ARMConstantIslands();
 }
 
 bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) {
+  assert(!mf.hasVirtRegs() && "Registers Allocated");
   MF = &mf;
   MCP = mf.getConstantPool();
 
   DEBUG(dbgs() << "***** ARMConstantIslands: "
                << MCP->getConstants().size() << " CP entries, aligned to "
                << MCP->getConstantPoolAlignment() << " bytes *****\n");
 
   STI = &static_cast<const ARMSubtarget &>(MF->getSubtarget());

lib/Target/ARM/ARMExpandPseudoInsts.cpp

public:
 
     const ARMBaseInstrInfo *TII;
     const TargetRegisterInfo *TRI;
     const ARMSubtarget *STI;
     ARMFunctionInfo *AFI;
 
     bool runOnMachineFunction(MachineFunction &Fn) override;
 
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
-
     const char *getPassName() const override {
       return "ARM pseudo instruction expansion pass";
     }
 
   private:
     void TransferImpOps(MachineInstr &OldMI,
                         MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
     bool ExpandMI(MachineBasicBlock &MBB,
while (MBBI != E) {
     Modified |= ExpandMI(MBB, MBBI, NMBBI);
     MBBI = NMBBI;
   }
 
   return Modified;
 }
 
 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
+  assert(!MF.hasVirtRegs() && "Registers Allocated");
   STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget());
   TII = STI->getInstrInfo();
   TRI = STI->getRegisterInfo();
   AFI = MF.getInfo<ARMFunctionInfo>();
 
   bool Modified = false;
   for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
        ++MFI)

lib/Target/ARM/ARMLoadStoreOptimizer.cpp

struct ARMLoadStoreOpt : public MachineFunctionPass {
     RegisterClassInfo RegClassInfo;
     MachineBasicBlock::const_iterator LiveRegPos;
     bool LiveRegsValid;
     bool RegClassInfoValid;
     bool isThumb1, isThumb2;
 
     bool runOnMachineFunction(MachineFunction &Fn) override;
 
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
-
     const char *getPassName() const override {
       return ARM_LOAD_STORE_OPT_NAME;
     }
 
   private:
     /// A set of load/store MachineInstrs with same base register sorted by
     /// offset.
     struct MemOpQueueEntry {
if (Use.isKill()) {
       MBB.erase(Prev);
       return true;
     }
 
   llvm_unreachable("tMOVr doesn't kill a reg before tBX_RET?");
 }
 
 bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
+  assert(!Fn.hasVirtRegs() && "Registers Allocated");
   if (skipFunction(*Fn.getFunction()))
     return false;
 
   MF = &Fn;
   STI = &static_cast<const ARMSubtarget &>(Fn.getSubtarget());
   TL = STI->getTargetLowering();
   AFI = Fn.getInfo<ARMFunctionInfo>();
   TII = STI->getInstrInfo();

lib/Target/ARM/ARMOptimizeBarriersPass.cpp

 namespace {
 class ARMOptimizeBarriersPass : public MachineFunctionPass {
 public:
   static char ID;
   ARMOptimizeBarriersPass() : MachineFunctionPass(ID) {}
 
   bool runOnMachineFunction(MachineFunction &Fn) override;
 
-  MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::AllVRegsAllocated);
-  }
-
   const char *getPassName() const override {
     return "optimise barriers pass";
   }
 };
 char ARMOptimizeBarriersPass::ID = 0;
 }
 
 // Returns whether the instruction can safely move past a DMB instruction
 // The current implementation allows this iif MI does not have any possible
 // memory access
 static bool CanMovePastDMB(const MachineInstr *MI) {
   return !(MI->mayLoad() ||
           MI->mayStore() ||
           MI->hasUnmodeledSideEffects() ||
           MI->isCall() ||
           MI->isReturn());
 }
 
 bool ARMOptimizeBarriersPass::runOnMachineFunction(MachineFunction &MF) {
+  assert(!MF.hasVirtRegs() && "Registers Allocated");
   if (skipFunction(*MF.getFunction()))
     return false;
 
   // Vector to store the DMBs we will remove after the first iteration
   std::vector<MachineInstr *> ToRemove;
   // DMBType is the Imm value of the first operand. It determines whether it's a
   // DMB ish, dmb sy, dmb osh, etc
   int64_t DMBType = -1;

lib/Target/ARM/Thumb2ITBlockPass.cpp

public:
 
     bool restrictIT;
     const Thumb2InstrInfo *TII;
     const TargetRegisterInfo *TRI;
     ARMFunctionInfo *AFI;
 
     bool runOnMachineFunction(MachineFunction &Fn) override;
 
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
-
     const char *getPassName() const override {
       return "Thumb IT blocks insertion pass";
     }
 
   private:
     bool MoveCopyOutOfITBlock(MachineInstr *MI,
                               ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
                               SmallSet<unsigned, 4> &Defs,
while (MBBI != E) {
     Modified = true;
     ++NumITs;
   }
 
   return Modified;
 }
 
 bool Thumb2ITBlockPass::runOnMachineFunction(MachineFunction &Fn) {
+  assert(!Fn.hasVirtRegs() && "Registers Allocated");
   const ARMSubtarget &STI =
       static_cast<const ARMSubtarget &>(Fn.getSubtarget());
   if (!STI.isThumb2())
     return false;
   AFI = Fn.getInfo<ARMFunctionInfo>();
   TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo());
   TRI = STI.getRegisterInfo();
   restrictIT = STI.restrictIT();

lib/Target/ARM/Thumb2SizeReduction.cpp

public:
     static char ID;
     Thumb2SizeReduce(std::function<bool(const Function &)> Ftor);
 
     const Thumb2InstrInfo *TII;
     const ARMSubtarget *STI;
 
     bool runOnMachineFunction(MachineFunction &MF) override;
 
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
-
     const char *getPassName() const override {
       return "Thumb2 instruction size reduction pass";
     }
 
   private:
     /// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
     DenseMap<unsigned, unsigned> ReduceOpcodeMap;
 
bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
 
   MBBInfo &Info = BlockInfo[MBB.getNumber()];
   Info.HighLatencyCPSR = HighLatencyCPSR;
   Info.Visited = true;
   return Modified;
 }
 
 bool Thumb2SizeReduce::runOnMachineFunction(MachineFunction &MF) {
+  assert(!MF.hasVirtRegs() && "Registers Allocated");
   if (PredicateFtor && !PredicateFtor(*MF.getFunction()))
     return false;
 
   STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget());
   if (STI->isThumb1Only() || STI->prefers32BitThumb())
     return false;
 
   TII = static_cast<const Thumb2InstrInfo *>(STI->getInstrInfo());

lib/Target/Hexagon/HexagonCFGOptimizer.cpp

public:
   HexagonCFGOptimizer() : MachineFunctionPass(ID) {
     initializeHexagonCFGOptimizerPass(*PassRegistry::getPassRegistry());
   }
 
   const char *getPassName() const override {
     return "Hexagon CFG Optimizer";
   }
   bool runOnMachineFunction(MachineFunction &Fn) override;
-  MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::AllVRegsAllocated);
-  }
 };
 
 
 char HexagonCFGOptimizer::ID = 0;
 
 static bool IsConditionalBranch(int Opc) {
   return (Opc == Hexagon::J2_jumpt) || (Opc == Hexagon::J2_jumpf)
     || (Opc == Hexagon::J2_jumptnewpt) || (Opc == Hexagon::J2_jumpfnewpt);
void HexagonCFGOptimizer::InvertAndChangeJumpTarget(
   }
 
   MI.setDesc(TII->get(NewOpcode));
   MI.getOperand(1).setMBB(NewTarget);
 }
 
 
 bool HexagonCFGOptimizer::runOnMachineFunction(MachineFunction &Fn) {
+  assert(!Fn.hasVirtRegs() && "Registers Allocated");
   if (skipFunction(*Fn.getFunction()))
     return false;
 
   // Loop over all of the basic blocks.
   for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
        MBBb != MBBe; ++MBBb) {
     MachineBasicBlock *MBB = &*MBBb;
 

lib/Target/Hexagon/HexagonCopyToCombine.cpp

public:
   }
 
   const char *getPassName() const override {
     return "Hexagon Copy-To-Combine Pass";
   }
 
   bool runOnMachineFunction(MachineFunction &Fn) override;
 
-  MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::AllVRegsAllocated);
-  }
-
 private:
   MachineInstr *findPairable(MachineInstr &I1, bool &DoInsertAtI1,
                              bool AllowC64);
 
   void findPotentialNewifiableTFRs(MachineBasicBlock &);
 
   void combine(MachineInstr &I1, MachineInstr &I2,
                MachineBasicBlock::iterator &MI, bool DoInsertAtI1,
for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
         }
       } else if (Hexagon::IntRegsRegClass.contains(Reg))
         LastDef[Reg] = &MI;
     }
   }
 }
 
 bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) {
+  assert(!MF.hasVirtRegs() && "Registers Allocated");
 
   if (IsCombinesDisabled) return false;
 
   bool HasChanged = false;
 
   // Get target info.
   TRI = MF.getSubtarget().getRegisterInfo();
   TII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();

lib/Target/Hexagon/HexagonFixupHwLoops.cpp

public:
     static char ID;
 
     HexagonFixupHwLoops() : MachineFunctionPass(ID) {
       initializeHexagonFixupHwLoopsPass(*PassRegistry::getPassRegistry());
     }
 
     bool runOnMachineFunction(MachineFunction &MF) override;
 
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
-
     const char *getPassName() const override {
       return "Hexagon Hardware Loop Fixup";
     }
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.setPreservesCFG();
       MachineFunctionPass::getAnalysisUsage(AU);
     }

 static bool isHardwareLoop(const MachineInstr &MI) {
   return MI.getOpcode() == Hexagon::J2_loop0r ||
          MI.getOpcode() == Hexagon::J2_loop0i ||
          MI.getOpcode() == Hexagon::J2_loop1r ||
          MI.getOpcode() == Hexagon::J2_loop1i;
 }
 
 bool HexagonFixupHwLoops::runOnMachineFunction(MachineFunction &MF) {
+  assert(!MF.hasVirtRegs() && "Registers Allocated");
   if (skipFunction(*MF.getFunction()))
     return false;
   return fixupLoopInstrs(MF);
 }
 
 /// \brief For Hexagon, if the loop label is to far from the
 /// loop instruction then we need to set the LC0 and SA0 registers
 /// explicitly instead of using LOOP(start,count).  This function

lib/Target/Hexagon/HexagonFrameLowering.cpp

namespace {
   class HexagonCallFrameInformation : public MachineFunctionPass {
   public:
     static char ID;
     HexagonCallFrameInformation() : MachineFunctionPass(ID) {
       PassRegistry &PR = *PassRegistry::getPassRegistry();
       initializeHexagonCallFrameInformationPass(PR);
     }
     bool runOnMachineFunction(MachineFunction &MF) override;
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
   };
 
   char HexagonCallFrameInformation::ID = 0;
 }
 
 bool HexagonCallFrameInformation::runOnMachineFunction(MachineFunction &MF) {
+  assert(!MF.hasVirtRegs() && "Registers Allocated");
   auto &HFI = *MF.getSubtarget<HexagonSubtarget>().getFrameLowering();
   bool NeedCFI = MF.getMMI().hasDebugInfo() ||
                  MF.getFunction()->needsUnwindTableEntry();
 
   if (!NeedCFI)
     return false;
   HFI.insertCFIInstructions(MF);
   return true;

lib/Target/Hexagon/HexagonGenMux.cpp

public:
     }
     const char *getPassName() const override {
       return "Hexagon generate mux instructions";
     }
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       MachineFunctionPass::getAnalysisUsage(AU);
     }
     bool runOnMachineFunction(MachineFunction &MF) override;
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
 
   private:
     const HexagonInstrInfo *HII;
     const HexagonRegisterInfo *HRI;
 
     struct CondsetInfo {
       unsigned PredR;
       unsigned TrueX, FalseX;
for (unsigned I = 0, N = ML.size(); I < N; ++I) {
     B.erase(MX.Def2);
     Changed = true;
   }
 
   return Changed;
 }
 
 bool HexagonGenMux::runOnMachineFunction(MachineFunction &MF) {
+  assert(!MF.hasVirtRegs() && "Registers Allocated");
   if (skipFunction(*MF.getFunction()))
     return false;
   HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
   HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
   bool Changed = false;
   for (auto &I : MF)
     Changed |= genMuxInBlock(I);
   return Changed;
 }
 
 FunctionPass *llvm::createHexagonGenMux() {
   return new HexagonGenMux();
 }

lib/Target/Hexagon/HexagonNewValueJump.cpp

void getAnalysisUsage(AnalysisUsage &AU) const override {
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 
     const char *getPassName() const override {
       return "Hexagon NewValueJump";
     }
 
     bool runOnMachineFunction(MachineFunction &Fn) override;
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
 
   private:
     /// \brief A handle to the branch probability pass.
     const MachineBranchProbabilityInfo *MBPI;
 
     bool isNewValueJumpCandidate(const MachineInstr &MI) const;
   };
 
bool HexagonNewValueJump::isNewValueJumpCandidate(
 
   default:
     return false;
   }
 }
 
 
 bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
+  assert(!MF.hasVirtRegs() && "Regisers Allocated");
 
   DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
                << "********** Function: "
                << MF.getName() << "\n");
 
   if (skipFunction(*MF.getFunction()))
     return false;
 

lib/Target/Hexagon/HexagonRDFOpt.cpp

void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.setPreservesAll();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
     const char *getPassName() const override {
       return "Hexagon RDF optimizations";
     }
     bool runOnMachineFunction(MachineFunction &MF) override;
 
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
-
     static char ID;
 
   private:
     MachineDominatorTree *MDT;
     MachineRegisterInfo *MRI;
   };
 
   char HexagonRDFOpt::ID = 0;
bool HexagonDCE::rewrite(NodeAddr<InstrNode*> IA, SetVector<NodeId> &Remove) {
   if (trace())
     dbgs() << "       to: " << *MI;
 
   return true;
 }
 
 
 bool HexagonRDFOpt::runOnMachineFunction(MachineFunction &MF) {
+  assert(!MF.hasVirtRegs() && "Registers Allocated");
   if (skipFunction(*MF.getFunction()))
     return false;
 
   if (RDFLimit.getPosition()) {
     if (RDFCount >= RDFLimit)
       return false;
     RDFCount++;
   }

lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp

  public:
     static char ID;
     HexagonSplitConst32AndConst64() : MachineFunctionPass(ID) {}
 
     const char *getPassName() const override {
       return "Hexagon Split Const32s and Const64s";
     }
     bool runOnMachineFunction(MachineFunction &Fn) override;
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
 };
 
 
 char HexagonSplitConst32AndConst64::ID = 0;
 
 
 bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) {
+  assert(!Fn.hasVirtRegs() && "Registers Allocated");
 
   const HexagonTargetObjectFile &TLOF =
       *static_cast<const HexagonTargetObjectFile *>(
           Fn.getTarget().getObjFileLowering());
   if (TLOF.isSmallDataEnabled())
     return true;
 
   const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo();

lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.addPreserved<MachineDominatorTree>();
       AU.addPreserved<MachineLoopInfo>();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
     const char *getPassName() const override {
       return "Hexagon Packetizer";
     }
     bool runOnMachineFunction(MachineFunction &Fn) override;
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
 
   private:
     const HexagonInstrInfo *HII;
     const HexagonRegisterInfo *HRI;
   };
 
   char HexagonPacketizer::ID = 0;
 }
static MachineBasicBlock::iterator moveInstrOut(MachineInstr *MI,
   SingleI->unbundleFromPred();
   assert(!SingleI->isBundledWithSucc());
   BundleIt->eraseFromParent();
   return NextIt;
 }
 
 
 bool HexagonPacketizer::runOnMachineFunction(MachineFunction &MF) {
+  assert(!MF.hasVirtRegs() && "Registers Allocated");
   if (DisablePacketizer || skipFunction(*MF.getFunction()))
     return false;
 
   HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
   HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
   auto &MLI = getAnalysis<MachineLoopInfo>();
   auto *AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
   auto *MBPI = &getAnalysis<MachineBranchProbabilityInfo>();

lib/Target/Lanai/LanaiDelaySlotFiller.cpp

struct Filler : public MachineFunctionPass {
   static char ID;
   explicit Filler() : MachineFunctionPass(ID) {}
 
   const char *getPassName() const override { return "Lanai Delay Slot Filler"; }
 
   bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
 
   bool runOnMachineFunction(MachineFunction &MF) override {
+    assert(!MF.hasVirtRegs() && "Registers Allocated");
     const LanaiSubtarget &Subtarget = MF.getSubtarget<LanaiSubtarget>();
     TII = Subtarget.getInstrInfo();
     TRI = Subtarget.getRegisterInfo();
 
     bool Changed = false;
     for (MachineFunction::iterator FI = MF.begin(), FE = MF.end(); FI != FE;
          ++FI)
       Changed |= runOnMachineBasicBlock(*FI);
     return Changed;
   }
 
-  MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::AllVRegsAllocated);
-  }
-
   void insertDefsUses(MachineBasicBlock::instr_iterator MI,
                       SmallSet<unsigned, 32> &RegDefs,
                       SmallSet<unsigned, 32> &RegUses);
 
   bool isRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg);
 
   bool delayHasHazard(MachineBasicBlock::instr_iterator MI, bool &SawLoad,
                       bool &SawStore, SmallSet<unsigned, 32> &RegDefs,

lib/Target/Lanai/LanaiMemAluCombiner.cpp

public:
   }
 
   const char *getPassName() const override {
     return "Lanai load / store optimization pass";
   }
 
   bool runOnMachineFunction(MachineFunction &F) override;
 
-  MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::AllVRegsAllocated);
-  }
-
 private:
   MbbIterator findClosestSuitableAluInstr(MachineBasicBlock *BB,
                                           const MbbIterator &MemInstr,
                                           bool Decrement);
   void insertMergedInstruction(MachineBasicBlock *BB,
                                const MbbIterator &MemInstr,
                                const MbbIterator &AluInstr, bool Before);
   bool combineMemAluInBasicBlock(MachineBasicBlock *BB);
bool LanaiMemAluCombiner::combineMemAluInBasicBlock(MachineBasicBlock *BB) {
   }
 
   return Modified;
 }
 
 // Driver function that iterates over the machine basic building blocks of a
 // machine function
 bool LanaiMemAluCombiner::runOnMachineFunction(MachineFunction &MF) {
+  assert(!MF.hasVirtRegs() && "Registers Allocated");
   if (DisableMemAluCombiner)
     return false;
 
   TII = MF.getSubtarget<LanaiSubtarget>().getInstrInfo();
   bool Modified = false;
   for (MfIterator MFI = MF.begin(); MFI != MF.end(); ++MFI) {
     Modified |= combineMemAluInBasicBlock(&*MFI);
   }
   return Modified;
 }
 } // namespace
 
 FunctionPass *llvm::createLanaiMemAluCombinerPass() {
   return new LanaiMemAluCombiner();
 }

lib/Target/MSP430/MSP430BranchSelector.cpp

struct MSP430BSel : public MachineFunctionPass {
     static char ID;
     MSP430BSel() : MachineFunctionPass(ID) {}
 
     /// BlockSizes - The sizes of the basic blocks in the function.
     std::vector<unsigned> BlockSizes;
 
     bool runOnMachineFunction(MachineFunction &Fn) override;
 
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
-
     const char *getPassName() const override {
       return "MSP430 Branch Selector";
     }
   };
   char MSP430BSel::ID = 0;
 }
 
 /// createMSP430BranchSelectionPass - returns an instance of the Branch
 /// Selection Pass
 ///
 FunctionPass *llvm::createMSP430BranchSelectionPass() {
   return new MSP430BSel();
 }
 
 bool MSP430BSel::runOnMachineFunction(MachineFunction &Fn) {
+  assert(!Fn.hasVirtRegs() && "Registers Allocated");
   const MSP430InstrInfo *TII =
       static_cast<const MSP430InstrInfo *>(Fn.getSubtarget().getInstrInfo());
   // Give the blocks of the function a dense, in-order, numbering.
   Fn.RenumberBlocks();
   BlockSizes.resize(Fn.getNumBlockIDs());
 
   // Measure each MBB and compute a size for the entire function.
   unsigned FuncSize = 0;

lib/Target/Mips/MipsConstantIslandPass.cpp

MipsConstantIslands()
           PrescannedForConstants(false) {}
 
     const char *getPassName() const override {
       return "Mips Constant Islands";
     }
 
     bool runOnMachineFunction(MachineFunction &F) override;
 
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
-
     void doInitialPlacement(std::vector<MachineInstr*> &CPEMIs);
     CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI);
     unsigned getCPELogAlign(const MachineInstr &CPEMI);
     void initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs);
     unsigned getOffsetOf(MachineInstr *MI) const;
     unsigned getUserOffset(CPUser&) const;
     void dumpBBs();
 
void MipsConstantIslands::dumpBBs() {
   });
 }
 /// Returns a pass that converts branches to long branches.
 FunctionPass *llvm::createMipsConstantIslandPass() {
   return new MipsConstantIslands();
 }
 
 bool MipsConstantIslands::runOnMachineFunction(MachineFunction &mf) {
+  assert(!mf.hasVirtRegs() && "Registers Allocated");
   // The intention is for this to be a mips16 only pass for now
   // FIXME:
   MF = &mf;
   MCP = mf.getConstantPool();
   STI = &static_cast<const MipsSubtarget &>(mf.getSubtarget());
   DEBUG(dbgs() << "constant island machine function " << "\n");
   if (!STI->inMips16Mode() || !MipsSubtarget::useConstantIslands()) {
     return false;

lib/Target/Mips/MipsDelaySlotFiller.cpp

public:
     Filler(TargetMachine &tm)
       : MachineFunctionPass(ID), TM(tm) { }
 
     const char *getPassName() const override {
       return "Mips Delay Slot Filler";
     }
 
     bool runOnMachineFunction(MachineFunction &F) override {
+      assert(!F.hasVirtRegs() && "Registers Allocated");
       bool Changed = false;
       for (MachineFunction::iterator FI = F.begin(), FE = F.end();
            FI != FE; ++FI)
         Changed |= runOnMachineBasicBlock(*FI);
 
       // This pass invalidates liveness information when it reorders
       // instructions to fill delay slot. Without this, -verify-machineinstrs
       // will fail.
       if (Changed)
         F.getRegInfo().invalidateLiveness();
 
       return Changed;
     }
 
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
-
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.addRequired<MachineBranchProbabilityInfo>();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 
   private:
     bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
 

lib/Target/Mips/MipsHazardSchedule.cpp

 
 public:
   MipsHazardSchedule() : MachineFunctionPass(ID) {}
 
   const char *getPassName() const override { return "Mips Hazard Schedule"; }
 
   bool runOnMachineFunction(MachineFunction &F) override;
 
-  MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::AllVRegsAllocated);
-  }
-
 private:
   static char ID;
 };
 
 char MipsHazardSchedule::ID = 0;
 } // end of anonymous namespace
 
 /// Returns a pass that clears pipeline hazards.
 FunctionPass *llvm::createMipsHazardSchedule() {
   return new MipsHazardSchedule();
 }
 
 // Find the next real instruction from the current position.
 static Iter getNextMachineInstr(Iter Position) {
   Iter I = Position, E = Position->getParent()->end();
   I = std::find_if_not(I, E, [](const Iter &Insn) { return Insn->isTransient(); });
   assert(I != E);
   return I;
 }
 
 bool MipsHazardSchedule::runOnMachineFunction(MachineFunction &MF) {
-
+  assert(!MF.hasVirtRegs() && "Registers Allocated");
   const MipsSubtarget *STI =
       &static_cast<const MipsSubtarget &>(MF.getSubtarget());
 
   // Forbidden slot hazards are only defined for MIPSR6.
   if (!STI->hasMips32r6() || STI->inMicroMipsMode())
     return false;
 
   bool Changed = false;

lib/Target/Mips/MipsLongBranch.cpp

MipsLongBranch(TargetMachine &tm)
           ABI(static_cast<const MipsTargetMachine &>(TM).getABI()) {}
 
     const char *getPassName() const override {
       return "Mips Long Branch";
     }
 
     bool runOnMachineFunction(MachineFunction &F) override;
 
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
-
   private:
     void splitMBB(MachineBasicBlock *MBB);
     void initMBBInfo();
     int64_t computeOffset(const MachineInstr *Br);
     void replaceBranch(MachineBasicBlock &MBB, Iter Br, const DebugLoc &DL,
                        MachineBasicBlock *MBBOpnd);
     void expandToLongBranch(MBBInfo &Info);
 
static void emitGPDisp(MachineFunction &F, const MipsInstrInfo *TII) {
   BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0)
     .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI);
   BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0)
     .addReg(Mips::V0).addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
   MBB.removeLiveIn(Mips::V0);
 }
 
 bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) {
+  assert(!F.hasVirtRegs() && "Registers Allocated");
   const MipsSubtarget &STI =
       static_cast<const MipsSubtarget &>(F.getSubtarget());
   const MipsInstrInfo *TII =
       static_cast<const MipsInstrInfo *>(STI.getInstrInfo());
   LongBranchSeqSize =
       !IsPIC ? 2 : (ABI.IsN64() ? 10 : (!STI.isTargetNaCl() ? 9 : 10));
 
   if (STI.inMips16Mode() || !STI.enableLongBranchPass())

lib/Target/PowerPC/PPCBranchSelector.cpp

PPCBSel() : MachineFunctionPass(ID) {
       initializePPCBSelPass(*PassRegistry::getPassRegistry());
     }
 
     /// BlockSizes - The sizes of the basic blocks in the function.
     std::vector<unsigned> BlockSizes;
 
     bool runOnMachineFunction(MachineFunction &Fn) override;
 
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
-
     const char *getPassName() const override {
       return "PowerPC Branch Selector";
     }
   };
   char PPCBSel::ID = 0;
 }
 
 INITIALIZE_PASS(PPCBSel, "ppc-branch-select", "PowerPC Branch Selector",
                 false, false)
 
 /// createPPCBranchSelectionPass - returns an instance of the Branch Selection
 /// Pass
 ///
 FunctionPass *llvm::createPPCBranchSelectionPass() {
   return new PPCBSel();
 }
 
 bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
+  assert(!Fn.hasVirtRegs() && "Registers Allocated");
   const PPCInstrInfo *TII =
       static_cast<const PPCInstrInfo *>(Fn.getSubtarget().getInstrInfo());
   // Give the blocks of the function a dense, in-order, numbering.
   Fn.RenumberBlocks();
   BlockSizes.resize(Fn.getNumBlockIDs());
 
   auto GetAlignmentAdjustment =
     [TII](MachineBasicBlock &MBB, unsigned Offset) -> unsigned {

lib/Target/PowerPC/PPCEarlyReturn.cpp

bool processBlock(MachineBasicBlock &ReturnMBB) {
           ReturnMBB.eraseFromParent();
       }
 
       return Changed;
     }
 
 public:
     bool runOnMachineFunction(MachineFunction &MF) override {
+      assert(!MF.hasVirtRegs() && "Registers Allocated");
       if (skipFunction(*MF.getFunction()))
         return false;
 
       TII = MF.getSubtarget().getInstrInfo();
 
       bool Changed = false;
 
       // If the function does not have at least two blocks, then there is
       // nothing to do.
       if (MF.size() < 2)
         return Changed;
 
       for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
         MachineBasicBlock &B = *I++;
         if (processBlock(B))
           Changed = true;
       }
 
       return Changed;
     }
 
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
-
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       MachineFunctionPass::getAnalysisUsage(AU);
     }
   };
 }
 
 INITIALIZE_PASS(PPCEarlyReturn, DEBUG_TYPE,
                 "PowerPC Early-Return Creation", false, false)
 
 char PPCEarlyReturn::ID = 0;
 FunctionPass*
 llvm::createPPCEarlyReturnPass() { return new PPCEarlyReturn(); }

lib/Target/Sparc/DelaySlotFiller.cpp

struct Filler : public MachineFunctionPass {
     Filler() : MachineFunctionPass(ID) {}
 
     const char *getPassName() const override {
       return "SPARC Delay Slot Filler";
     }
 
     bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
     bool runOnMachineFunction(MachineFunction &F) override {
+      assert(!F.hasVirtRegs() && "Registers Allocated");
       bool Changed = false;
       Subtarget = &F.getSubtarget<SparcSubtarget>();
 
       // This pass invalidates liveness information when it reorders
       // instructions to fill delay slot.
       F.getRegInfo().invalidateLiveness();
 
       for (MachineFunction::iterator FI = F.begin(), FE = F.end();
            FI != FE; ++FI)
         Changed |= runOnMachineBasicBlock(*FI);
       return Changed;
     }
 
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
-
     void insertCallDefsUses(MachineBasicBlock::iterator MI,
                             SmallSet<unsigned, 32>& RegDefs,
                             SmallSet<unsigned, 32>& RegUses);
 
     void insertDefsUses(MachineBasicBlock::iterator MI,
                         SmallSet<unsigned, 32>& RegDefs,
                         SmallSet<unsigned, 32>& RegUses);
 

lib/Target/SystemZ/SystemZElimCompare.cpp

SystemZElimCompare(const SystemZTargetMachine &tm)
     : MachineFunctionPass(ID), TII(nullptr), TRI(nullptr) {}
 
   const char *getPassName() const override {
     return "SystemZ Comparison Elimination";
   }
 
   bool processBlock(MachineBasicBlock &MBB);
   bool runOnMachineFunction(MachineFunction &F) override;
-  MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::AllVRegsAllocated);
-  }
 
 private:
   Reference getRegReferences(MachineInstr &MI, unsigned Reg);
   bool convertToBRCT(MachineInstr &MI, MachineInstr &Compare,
                      SmallVectorImpl<MachineInstr *> &CCUsers);
   bool convertToLoadAndTest(MachineInstr &MI);
   bool adjustCCMasksForInstr(MachineInstr &MI, MachineInstr &Compare,
                              SmallVectorImpl<MachineInstr *> &CCUsers);
while (MBBI != MBB.begin()) {
     }
     if (MI.readsRegister(SystemZ::CC) && CompleteCCUsers)
       CCUsers.push_back(&MI);
   }
   return Changed;
 }
 
 bool SystemZElimCompare::runOnMachineFunction(MachineFunction &F) {
+  assert(!F.hasVirtRegs() && "Registers Allocated");
   if (skipFunction(*F.getFunction()))
     return false;
 
   TII = static_cast<const SystemZInstrInfo *>(F.getSubtarget().getInstrInfo());
   TRI = &TII->getRegisterInfo();
 
   bool Changed = false;
   for (auto &MBB : F)
     Changed |= processBlock(MBB);
 
   return Changed;
 }

lib/Target/SystemZ/SystemZLongBranch.cpp

public:
   SystemZLongBranch(const SystemZTargetMachine &tm)
     : MachineFunctionPass(ID), TII(nullptr) {}
 
   const char *getPassName() const override {
     return "SystemZ Long Branch";
   }
 
   bool runOnMachineFunction(MachineFunction &F) override;
-  MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::AllVRegsAllocated);
-  }
 
 private:
   void skipNonTerminators(BlockPosition &Position, MBBInfo &Block);
   void skipTerminator(BlockPosition &Position, TerminatorInfo &Terminator,
                       bool AssumeRelaxed);
   TerminatorInfo describeTerminator(MachineInstr &MI);
   uint64_t initMBBInfo();
   bool mustRelaxBranch(const TerminatorInfo &Terminator, uint64_t Address);
for (unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) {
         relaxBranch(*TI);
       skipTerminator(Position, *TI, false);
       ++TI;
     }
   }
 }
 
 bool SystemZLongBranch::runOnMachineFunction(MachineFunction &F) {
+  assert(!F.hasVirtRegs() && "Registers Allocated");
   TII = static_cast<const SystemZInstrInfo *>(F.getSubtarget().getInstrInfo());
   MF = &F;
   uint64_t Size = initMBBInfo();
   if (Size <= MaxForwardRange || !mustRelaxABranch())
     return false;
 
   setWorstCaseAddresses();
   relaxBranches();
   return true;
 }

lib/Target/SystemZ/SystemZShortenInst.cpp

public:
   SystemZShortenInst(const SystemZTargetMachine &tm);
 
   const char *getPassName() const override {
     return "SystemZ Instruction Shortening";
   }
 
   bool processBlock(MachineBasicBlock &MBB);
   bool runOnMachineFunction(MachineFunction &F) override;
-  MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::AllVRegsAllocated);
-  }
 
 private:
   bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH);
   bool shortenOn0(MachineInstr &MI, unsigned Opcode);
   bool shortenOn01(MachineInstr &MI, unsigned Opcode);
   bool shortenOn001(MachineInstr &MI, unsigned Opcode);
   bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);
   bool shortenFPConv(MachineInstr &MI, unsigned Opcode);
for (auto MBBI = MBB.rbegin(), MBBE = MBB.rend(); MBBI != MBBE; ++MBBI) {
 
     LiveRegs.stepBackward(MI);
   }
 
   return Changed;
 }
 
 bool SystemZShortenInst::runOnMachineFunction(MachineFunction &F) {
+  assert(!F.hasVirtRegs() && "Registers Allocated");
   if (skipFunction(*F.getFunction()))
     return false;
 
   const SystemZSubtarget &ST = F.getSubtarget<SystemZSubtarget>();
   TII = ST.getInstrInfo();
   TRI = ST.getRegisterInfo();
   LiveRegs.init(TRI);
 
   bool Changed = false;
   for (auto &MBB : F)
     Changed |= processBlock(MBB);
 
   return Changed;
 }

lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp

 void WebAssemblyPassConfig::addPostRegAlloc() {
   // TODO: The following CodeGen passes don't currently support code containing
   // virtual registers. Consider removing their restrictions and re-enabling
   // them.
 
   // Has no asserts of its own, but was not written to handle virtual regs.
   disablePass(&ShrinkWrapID);
 
-  // These functions all require the AllVRegsAllocated property.
+  // These passes do not support virtual registers.
   disablePass(&MachineCopyPropagationID);
   disablePass(&PostRASchedulerID);
   disablePass(&FuncletLayoutID);
   disablePass(&StackMapLivenessID);
   disablePass(&LiveDebugValuesID);
   disablePass(&PatchableFunctionID);
 
   TargetPassConfig::addPostRegAlloc();

lib/Target/X86/X86ExpandPseudo.cpp

public:
   const X86Subtarget *STI;
   const X86InstrInfo *TII;
   const X86RegisterInfo *TRI;
   const X86MachineFunctionInfo *X86FI;
   const X86FrameLowering *X86FL;
 
   bool runOnMachineFunction(MachineFunction &Fn) override;
 
-  MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::AllVRegsAllocated);
-  }
-
   const char *getPassName() const override {
     return "X86 pseudo instruction expansion pass";
   }
 
 private:
   bool ExpandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
   bool ExpandMBB(MachineBasicBlock &MBB);
 };
while (MBBI != E) {
     Modified |= ExpandMI(MBB, MBBI);
     MBBI = NMBBI;
   }
 
   return Modified;
 }
 
 bool X86ExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
+  assert(!MF.hasVirtRegs() && "Registers Allocated");
   STI = &static_cast<const X86Subtarget &>(MF.getSubtarget());
   TII = STI->getInstrInfo();
   TRI = STI->getRegisterInfo();
   X86FI = MF.getInfo<X86MachineFunctionInfo>();
   X86FL = STI->getFrameLowering();
 
   bool Modified = false;
   for (MachineBasicBlock &MBB : MF)
     Modified |= ExpandMBB(MBB);
   return Modified;
 }
 
 /// Returns an instance of the pseudo instruction expansion pass.
 FunctionPass *llvm::createX86ExpandPseudoPass() {
   return new X86ExpandPseudo();
 }

lib/Target/X86/X86FixupBWInsts.cpp

void getAnalysisUsage(AnalysisUsage &AU) const override {
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
   /// Loop over all of the basic blocks, replacing byte and word instructions by
   /// equivalent 32 bit instructions where performance or code size can be
   /// improved.
   bool runOnMachineFunction(MachineFunction &MF) override;
 
-  MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::AllVRegsAllocated);
-  }
-
 private:
   MachineFunction *MF;
 
   /// Machine instruction info used throughout the class.
   const X86InstrInfo *TII;
 
   /// Local member for function's OptForSize attribute.
   bool OptForSize;
 
   /// Machine loop info used for guiding some heruistics.
   MachineLoopInfo *MLI;
 
   /// Register Liveness information after the current instruction.
   LivePhysRegs LiveRegs;
 };
 char FixupBWInstPass::ID = 0;
 }
 
 INITIALIZE_PASS(FixupBWInstPass, FIXUPBW_NAME, FIXUPBW_DESC, false, false)
 
 FunctionPass *llvm::createX86FixupBWInsts() { return new FixupBWInstPass(); }
 
 bool FixupBWInstPass::runOnMachineFunction(MachineFunction &MF) {
+  assert(!MF.hasVirtRegs() && "Registers Allocated");
   if (!FixupBWInsts || skipFunction(*MF.getFunction()))
     return false;
 
   this->MF = &MF;
   TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
   OptForSize = MF.getFunction()->optForSize();
   MLI = &getAnalysis<MachineLoopInfo>();
   LiveRegs.init(&TII->getRegisterInfo());

lib/Target/X86/X86FixupLEAs.cpp

 public:
   FixupLEAPass() : MachineFunctionPass(ID) {}
 
   /// \brief Loop over all of the basic blocks,
   /// replacing instructions by equivalent LEA instructions
   /// if needed and when possible.
   bool runOnMachineFunction(MachineFunction &MF) override;
 
-  // This pass runs after regalloc and doesn't support VReg operands.
-  MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::AllVRegsAllocated);
-  }
-
 private:
   MachineFunction *MF;
   const X86InstrInfo *TII; // Machine instruction info.
   bool OptIncDec;
   bool OptLEA;
 };
 char FixupLEAPass::ID = 0;
 }
case X86::ADD16rr_DB:
     }
   }
   return TII->convertToThreeAddress(MFI, MI, nullptr);
 }
 
 FunctionPass *llvm::createX86FixupLEAs() { return new FixupLEAPass(); }
 
 bool FixupLEAPass::runOnMachineFunction(MachineFunction &Func) {
+  assert(!Func.hasVirtRegs() && "Registers Allocated");
   if (skipFunction(*Func.getFunction()))
     return false;
 
   MF = &Func;
   const X86Subtarget &ST = Func.getSubtarget<X86Subtarget>();
   OptIncDec = !ST.slowIncDec() || Func.getFunction()->optForMinSize();
   OptLEA = ST.LEAusesAG() || ST.slowLEA();
 

lib/Target/X86/X86FloatingPoint.cpp

void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.addRequired<EdgeBundles>();
       AU.addPreservedID(MachineLoopInfoID);
       AU.addPreservedID(MachineDominatorsID);
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 
     bool runOnMachineFunction(MachineFunction &MF) override;
 
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
-
     const char *getPassName() const override { return "X86 FP Stackifier"; }
 
   private:
     const TargetInstrInfo *TII; // Machine instruction info.
 
     // Two CFG edges are related if they leave the same block, or enter the same
     // block. The transitive closure of an edge under this relation is a
     // LiveBundle. It represents a set of CFG edges where the live FP stack
static unsigned getFPReg(const MachineOperand &MO) {
   assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
   return Reg - X86::FP0;
 }
 
 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
 /// register references into FP stack references.
 ///
 bool FPS::runOnMachineFunction(MachineFunction &MF) {
+  assert(!MF.hasVirtRegs() && "Registers Allocated");
   // We only need to run this pass if there are any FP registers used in this
   // function.  If it is all integer, there is nothing for us to do!
   bool FPIsUsed = false;
 
   static_assert(X86::FP6 == X86::FP0+6, "Register enums aren't sorted right!");
   const MachineRegisterInfo &MRI = MF.getRegInfo();
   for (unsigned i = 0; i <= 6; ++i)
     if (!MRI.reg_nodbg_empty(X86::FP0 + i)) {

lib/Target/X86/X86PadShortFunction.cpp

namespace {
 
   struct PadShortFunc : public MachineFunctionPass {
     static char ID;
     PadShortFunc() : MachineFunctionPass(ID)
                    , Threshold(4), STI(nullptr), TII(nullptr) {}
 
     bool runOnMachineFunction(MachineFunction &MF) override;
 
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
-
     const char *getPassName() const override {
       return "X86 Atom pad short functions";
     }
 
   private:
     void findReturns(MachineBasicBlock *MBB,
                      unsigned int Cycles = 0);
 

 
 FunctionPass *llvm::createX86PadShortFunctions() {
   return new PadShortFunc();
 }
 
 /// runOnMachineFunction - Loop over all of the basic blocks, inserting
 /// NOOP instructions before early exits.
 bool PadShortFunc::runOnMachineFunction(MachineFunction &MF) {
+  assert(!MF.hasVirtRegs() && "Registers Allocated");
   if (skipFunction(*MF.getFunction()))
     return false;
 
   if (MF.getFunction()->optForSize()) {
     return false;
   }
 
   STI = &MF.getSubtarget<X86Subtarget>();

lib/Target/X86/X86VZeroUpper.cpp

 
 namespace {
 
   class VZeroUpperInserter : public MachineFunctionPass {
   public:
 
     VZeroUpperInserter() : MachineFunctionPass(ID) {}
     bool runOnMachineFunction(MachineFunction &MF) override;
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
     const char *getPassName() const override {return "X86 vzeroupper inserter";}
 
   private:
 
     void processBasicBlock(MachineBasicBlock &MBB);
     void insertVZeroUpper(MachineBasicBlock::iterator I,
                           MachineBasicBlock &MBB);
     void addDirtySuccessor(MachineBasicBlock &MBB);
for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
       addDirtySuccessor(**SI);
 
   BlockStates[MBB.getNumber()].ExitState = CurState;
 }
 
 /// Loop over all of the basic blocks, inserting vzeroupper instructions before
 /// function calls.
 bool VZeroUpperInserter::runOnMachineFunction(MachineFunction &MF) {
+  assert(!MF.hasVirtRegs() && "Registers Allocated");
   const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
   if (!ST.hasAVX() || ST.hasAVX512() || ST.hasFastPartialYMMWrite())
     return false;
   TII = ST.getInstrInfo();
   MachineRegisterInfo &MRI = MF.getRegInfo();
   EverMadeChange = false;
   IsX86INTR = MF.getFunction()->getCallingConv() == CallingConv::X86_INTR;
 

lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp

 using namespace llvm;
 
 namespace {
   struct XCoreFTAOElim : public MachineFunctionPass {
     static char ID;
     XCoreFTAOElim() : MachineFunctionPass(ID) {}
 
     bool runOnMachineFunction(MachineFunction &Fn) override;
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::AllVRegsAllocated);
-    }
 
     const char *getPassName() const override {
       return "XCore FRAME_TO_ARGS_OFFSET Elimination";
     }
   };
   char XCoreFTAOElim::ID = 0;
 }
 
 /// createXCoreFrameToArgsOffsetEliminationPass - returns an instance of the
 /// Frame to args offset elimination pass
 FunctionPass *llvm::createXCoreFrameToArgsOffsetEliminationPass() {
   return new XCoreFTAOElim();
 }
 
 bool XCoreFTAOElim::runOnMachineFunction(MachineFunction &MF) {
+  assert(!MF.hasVirtRegs() && "Registers Allocated");
   const XCoreInstrInfo &TII =
       *static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo());
   unsigned StackSize = MF.getFrameInfo()->getStackSize();
   for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
        ++MFI) {
     MachineBasicBlock &MBB = *MFI;
     for (MachineBasicBlock::iterator MBBI = MBB.begin(), EE = MBB.end();
          MBBI != EE; ++MBBI) {

test/CodeGen/AArch64/movimm-wzr.mir

--- |
   }
 
 ...
 ---
 name:            test_mov_0
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
-allVRegsAllocated: true
 isSSA:           false
 tracksRegLiveness: false
 tracksSubRegLiveness: false
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false

test/CodeGen/ARM/ARMLoadStoreDBG.mir

--- |
   !34 = !DILocation(line: 15, scope: !4)
 
 ...
 ---
 name:            f
 alignment:       1
 exposesReturnsTwice: false
 hasInlineAsm:    false
-allVRegsAllocated: true
 isSSA:           false
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 liveins:
   - { reg: '%r0' }
   - { reg: '%r1' }
   - { reg: '%r2' }
   - { reg: '%r3' }

test/CodeGen/MIR/AArch64/machine-dead-copy.mir

 
 # RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass machine-cp  -verify-machineinstrs  -o - %s | FileCheck %s
 
 --- |
   define i32 @copyprop1(i32 %a, i32 %b) { ret i32 %a }
   define i32 @copyprop2(i32 %a, i32 %b) { ret i32 %a }
   define i32 @copyprop3(i32 %a, i32 %b) { ret i32 %a }
   define i32 @copyprop4(i32 %a, i32 %b) { ret i32 %a }
   declare i32 @foo(i32)
 ...
 ---
 # The first copy is dead copy which is not used.
 # CHECK-LABEL: name: copyprop1
 # CHECK: bb.0:
 # CHECK-NOT: %w20 = COPY
 name:            copyprop1
-allVRegsAllocated: true
 body:             |
   bb.0:
     liveins: %w0,  %w1
     %w20 = COPY %w1
     BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0
     RET_ReallyLR implicit %w0
 ...
 ---
 # The first copy is not a dead copy which is used in the second copy after the
 # call.
 # CHECK-LABEL: name: copyprop2
 # CHECK: bb.0:
 # CHECK: %w20 = COPY
 name:            copyprop2
-allVRegsAllocated: true
 body:             |
   bb.0:
     liveins: %w0,  %w1
     %w20 = COPY %w1
     BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0
     %w0 = COPY %w20
     RET_ReallyLR implicit %w0
 ...
 ---
 # Both the first and second copy are dead copies which are not used.
 # CHECK-LABEL: name: copyprop3
 # CHECK: bb.0:
 # CHECK-NOT: COPY
 name:            copyprop3
-allVRegsAllocated: true
 body:             |
   bb.0:
     liveins: %w0,  %w1
     %w20 = COPY %w1
     BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0
     %w20 = COPY %w0
     RET_ReallyLR implicit %w0
 ...
 # The second copy is removed as a NOP copy, after then the first copy become
 # dead which should be removed as well.
 # CHECK-LABEL: name: copyprop4
 # CHECK: bb.0:
 # CHECK-NOT: COPY
 name:            copyprop4
-allVRegsAllocated: true
 body:             |
   bb.0:
     liveins: %w0,  %w1
     %w20 = COPY %w0
     %w0 = COPY %w20
     BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0
     RET_ReallyLR implicit %w0
 ...
 

test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir

--- |
   !34 = !DILocation(line: 15, scope: !4)
 
 ...
 ---
 name:            f
 alignment:       1
 exposesReturnsTwice: false
 hasInlineAsm:    false
-allVRegsAllocated: true
 isSSA:           false
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 liveins:
   - { reg: '%r0' }
   - { reg: '%r1' }
   - { reg: '%r2' }
   - { reg: '%r3' }

test/CodeGen/MIR/Hexagon/anti-dep-partial.mir

 # RUN: llc -march=hexagon -post-RA-scheduler -run-pass post-RA-sched %s -o - | FileCheck %s
 
 --- |
   declare void @check(i64, i32, i32, i64)
   define void @foo() {
     ret void
   }
 ...
 
 ---
 name: foo
 tracksRegLiveness: true
-allVRegsAllocated: true
 body: |
   bb.0:
     successors:
     liveins: %r0, %r1, %d1, %d2, %r16, %r17, %r19, %r22, %r23
         %r2 = A2_add %r23, killed %r17
         %r6 = M2_mpyi %r16, %r16
         %r22 = M2_accii %r22, killed %r2, 2
         %r7 = A2_tfrsi 12345678

test/CodeGen/MIR/Lanai/peephole-compare.mir

--- |
   !3 = !{!"Simple C/C++ TBAA"}
 
 ...
 ---
 name:            test0a
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
-allVRegsAllocated: false
 isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
bb.0.entry:
     RET implicit %rca, implicit %rv
 
 ...
 ---
 name:            test0b
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
-allVRegsAllocated: false
 isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
bb.0.entry:
     RET implicit %rca, implicit %rv
 
 ...
 ---
 name:            test1a
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
-allVRegsAllocated: false
 isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
bb.0.entry:
     RET implicit %rca, implicit %rv
 
 ...
 ---
 name:            test1b
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
-allVRegsAllocated: false
 isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
bb.0.entry:
     RET implicit %rca, implicit %rv
 
 ...
 ---
 name:            test2a
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
-allVRegsAllocated: false
 isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
bb.0.entry:
     RET implicit %rca, implicit %rv
 
 ...
 ---
 name:            test2b
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
-allVRegsAllocated: false
 isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
bb.0.entry:
     RET implicit %rca, implicit %rv
 
 ...
 ---
 name:            test3
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
-allVRegsAllocated: false
 isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
bb.0.entry:
     RET implicit %rca, implicit %rv
 
 ...
 ---
 name:            test4
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
-allVRegsAllocated: false
 isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
bb.4.return:
     RET implicit %rca, implicit %rv
 
 ...
 ---
 name:            testBB
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
-allVRegsAllocated: false
 isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }

test/CodeGen/PowerPC/aantidep-def-ec.mir

--- |
   attributes #1 = { nounwind }
 
 ...
 ---
 name:            mm_update_next_owner
 alignment:       4
 exposesReturnsTwice: false
 hasInlineAsm:    true
-allVRegsAllocated: true
 isSSA:           false
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 liveins:         
   - { reg: '%x3' }
   - { reg: '%x4' }
 calleeSavedRegisters: [ '%cr2', '%cr3', '%cr4', '%f14', '%f15', '%f16', 
                         '%f17', '%f18', '%f19', '%f20', '%f21', '%f22', 

test/CodeGen/PowerPC/addisdtprelha-nonr3.mir

--- |
   !0 = !{i32 1, !"PIC Level", i32 2}
 
 ...
 ---
 name:            test1
 alignment:       4
 exposesReturnsTwice: false
 hasInlineAsm:    false
-allVRegsAllocated: true
 isSSA:           false
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 frameInfo:       
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false

test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir

--- |
   attributes #1 = { nounwind }
 
 ...
 ---
 name:            fn1
 alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
-allVRegsAllocated: false
 isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:
   - { id: 0, class: g8rc }
   - { id: 1, class: g8rc }
   - { id: 2, class: g8rc }
   - { id: 3, class: g8rc }

test/CodeGen/X86/eflags-copy-expansion.mir

--- |
   false:
     ret void
   }
 
 ...
 
 ---
 name:            foo
-allVRegsAllocated: true
 isSSA:           false
 tracksRegLiveness: true
 liveins:
   - { reg: '%edi' }
 body:             |
   bb.0.entry:
     liveins: %edi
     successors: %bb.1.false

test/CodeGen/X86/fixup-bw-copy.mir

--- |
   define i16 @test_movw_impdef_gr64(i16 %a0) {
     ret i16 %a0
   }
 
 ...
 
 ---
 name:            test_movb_killed
-allVRegsAllocated: true
 isSSA:           false
 tracksRegLiveness: true
 liveins:
   - { reg: '%edi' }
 body:             |
   bb.0 (%ir-block.0):
     liveins: %edi
 
     ; CHECK: %eax = MOV32rr undef %edi, implicit %dil
     %al = MOV8rr killed %dil
     RETQ killed %al
 
 ...
 
 ---
 name:            test_movb_impuse
-allVRegsAllocated: true
 isSSA:           false
 tracksRegLiveness: true
 liveins:
   - { reg: '%edi' }
 body:             |
   bb.0 (%ir-block.0):
     liveins: %edi
 
     ; CHECK: %eax = MOV32rr undef %edi, implicit %dil
     %al = MOV8rr %dil, implicit %edi
     RETQ killed %al
 
 ...
 
 ---
 name:            test_movb_impdef_gr64
-allVRegsAllocated: true
 isSSA:           false
 tracksRegLiveness: true
 liveins:
   - { reg: '%edi' }
 body:             |
   bb.0 (%ir-block.0):
     liveins: %edi
 
     ; CHECK: %eax = MOV32rr undef %edi, implicit %dil, implicit-def %rax
     %al = MOV8rr %dil, implicit-def %rax
     RETQ killed %al
 
 ...
 
 ---
 name:            test_movb_impdef_gr32
-allVRegsAllocated: true
 isSSA:           false
 tracksRegLiveness: true
 liveins:
   - { reg: '%edi' }
 body:             |
   bb.0 (%ir-block.0):
     liveins: %edi
 
     ; CHECK: %eax = MOV32rr undef %edi, implicit %dil
     %al = MOV8rr %dil, implicit-def %eax
     RETQ killed %al
 
 ...
 
 ---
 name:            test_movb_impdef_gr16
-allVRegsAllocated: true
 isSSA:           false
 tracksRegLiveness: true
 liveins:
   - { reg: '%edi' }
 body:             |
   bb.0 (%ir-block.0):
     liveins: %edi
 
     ; CHECK: %eax = MOV32rr undef %edi, implicit %dil
     %al = MOV8rr %dil, implicit-def %ax
     RETQ killed %al
 
 ...
 
 ---
 name:            test_movw_impdef_gr32
-allVRegsAllocated: true
 isSSA:           false
 tracksRegLiveness: true
 liveins:
   - { reg: '%edi' }
 body:             |
   bb.0 (%ir-block.0):
     liveins: %edi
 
     ; CHECK: %eax = MOV32rr undef %edi, implicit %di
     %ax = MOV16rr %di, implicit-def %eax
     RETQ killed %ax
 
 ...
 
 ---
 name:            test_movw_impdef_gr64
-allVRegsAllocated: true
 isSSA:           false
 tracksRegLiveness: true
 liveins:
   - { reg: '%edi' }
 body:             |
   bb.0 (%ir-block.0):
     liveins: %edi
 
     ; CHECK: %eax = MOV32rr undef %edi, implicit %di, implicit-def %rax
     %ax = MOV16rr %di, implicit-def %rax
     RETQ killed %ax
 
 ...

test/CodeGen/X86/implicit-null-checks.mir

--- |
   }
 
   !0 = !{}
 ...
 ---
 name:            imp_null_check_with_bitwise_op_0
 # CHECK-LABEL: name:            imp_null_check_with_bitwise_op_0
 alignment:       4
-allVRegsAllocated: true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 liveins:
   - { reg: '%rdi' }
   - { reg: '%esi' }
 # CHECK:  bb.0.entry:
 # CHECK:    %eax = MOV32ri 2200000
 # CHECK-NEXT:    %eax = FAULTING_LOAD_OP %bb.3.is_null, {{[0-9]+}}, killed %eax, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
body:             |
   bb.4.ret_100:
     %eax = MOV32ri 100
     RET 0, %eax
 
 ...
 ---
 name:            imp_null_check_with_bitwise_op_1
 alignment:       4
-allVRegsAllocated: true
 isSSA:           false
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 liveins:
   - { reg: '%rdi' }
   - { reg: '%esi' }
   - { reg: '%rdx' }
 # CHECK: bb.0.entry:
bb.4.ret_100:
     %eax = MOV32ri 100
     RET 0, %eax
 
 ...
 ---
 name:            imp_null_check_with_bitwise_op_2
 # CHECK-LABEL: name:            imp_null_check_with_bitwise_op_2
 alignment:       4
-allVRegsAllocated: true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 liveins:
   - { reg: '%rdi' }
   - { reg: '%esi' }
 # CHECK:  bb.0.entry:
 # CHECK:    TEST64rr %rdi, %rdi, implicit-def %eflags
 # CHECK-NEXT:    JE_1 %bb.3.is_null, implicit %eflags
bb.4.ret_100:
     %eax = MOV32ri 100
     RET 0, %eax
 
 ...
 ---
 name:            imp_null_check_with_bitwise_op_3
 # CHECK-LABEL: name:            imp_null_check_with_bitwise_op_3
 alignment:       4
-allVRegsAllocated: true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 liveins:
   - { reg: '%rdi' }
   - { reg: '%rsi' }
 # CHECK:  bb.0.entry:
 # CHECK:    TEST64rr %rdi, %rdi, implicit-def %eflags
 # CHECK-NEXT:    JE_1 %bb.3.is_null, implicit %eflags

test/CodeGen/X86/machine-copy-prop.mir

 # the kill flag of intermediate instructions.
 # CHECK-LABEL: name: copyprop_remove_kill0
 # CHECK: bb.0:
 # CHECK-NEXT: %rax = COPY %rdi
 # CHECK-NEXT: NOOP implicit %rdi
 # CHECK-NOT: COPY
 # CHECK-NEXT: NOOP implicit %rax, implicit %rdi
 name: copyprop_remove_kill0
-allVRegsAllocated: true
 body: |
   bb.0:
     %rax = COPY %rdi
     NOOP implicit killed %rdi
     %rdi = COPY %rax
     NOOP implicit %rax, implicit %rdi
 ...
 ---
 # The second copy is redundant and will be removed, check that we also remove
 # the kill flag of intermediate instructions.
 # CHECK-LABEL: name: copyprop_remove_kill1
 # CHECK: bb.0:
 # CHECK-NEXT: %rax = COPY %rdi
 # CHECK-NEXT: NOOP implicit %edi
 # CHECK-NOT: COPY
 # CHECK-NEXT: NOOP implicit %rax, implicit %rdi
 name: copyprop_remove_kill1
-allVRegsAllocated: true
 body: |
   bb.0:
     %rax = COPY %rdi
     NOOP implicit killed %edi
     %rdi = COPY %rax
     NOOP implicit %rax, implicit %rdi
 ...
 ---
 # The second copy is redundant and will be removed, check that we also remove
 # the kill flag of intermediate instructions.
 # CHECK-LABEL: name: copyprop_remove_kill2
 # CHECK: bb.0:
 # CHECK-NEXT: %ax = COPY %di
 # CHECK-NEXT: NOOP implicit %rdi
 # CHECK-NOT: COPY
 # CHECK-NEXT: NOOP implicit %rax, implicit %rdi
 name: copyprop_remove_kill2
-allVRegsAllocated: true
 body: |
   bb.0:
     %ax = COPY %di
     NOOP implicit killed %rdi
     %di = COPY %ax
     NOOP implicit %rax, implicit %rdi
 ...
 ---
 # The second copy is redundant; the call preserves the source and dest register.
 # CHECK-LABEL: name: copyprop0
 # CHECK: bb.0:
 # CHECK-NEXT: %rax = COPY %rdi
 # CHECK-NEXT: CALL64pcrel32 @foo, csr_64_rt_mostregs
 # CHECK-NEXT: NOOP implicit %edi
 # CHECK-NOT: COPY
 # CHECK-NEXT: NOOP implicit %rax, implicit %rdi
 name: copyprop0
-allVRegsAllocated: true
 body: |
   bb.0:
     %rax = COPY %rdi
     CALL64pcrel32 @foo, csr_64_rt_mostregs
     NOOP implicit killed %edi
     %rdi = COPY %rax
     NOOP implicit %rax, implicit %rdi
 ...
 ---
 # The 2nd copy is redundant; The call preserves the source and dest register.
 # CHECK-LABEL: name: copyprop1
 # CHECK: bb.0:
 # CHECK-NEXT: %rax = COPY %rdi
 # CHECK-NEXT: NOOP implicit %rax
 # CHECK-NEXT: NOOP implicit %rax, implicit %rdi
 name: copyprop1
-allVRegsAllocated: true
 body: |
   bb.0:
     %rax = COPY %rdi
     NOOP implicit killed %rax
     %rax = COPY %rdi
     NOOP implicit %rax, implicit %rdi
 ...
 ---
 # CHECK-LABEL: name: copyprop2
 # CHECK: bb.0:
 # CHECK-NEXT: %rax = COPY %rdi
 # CHECK-NEXT: NOOP implicit %ax
 # CHECK-NEXT: CALL64pcrel32 @foo, csr_64_rt_mostregs
 # CHECK-NOT: %rax = COPY %rdi
 # CHECK-NEXT: NOOP implicit %rax, implicit %rdi
 name: copyprop2
-allVRegsAllocated: true
 body: |
   bb.0:
     %rax = COPY %rdi
     NOOP implicit killed %ax
     CALL64pcrel32 @foo, csr_64_rt_mostregs
     %rax = COPY %rdi
     NOOP implicit %rax, implicit %rdi
 ...
 ---
 # The second copy is not redundant if the source register (%rax) is clobbered
 # even if the dest (%rbp) is not.
 # CHECK-LABEL: name: nocopyprop0
 # CHECK: bb.0:
 # CHECK-NEXT: %rax = COPY %rbp
 # CHECK-NEXT: CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp
 # CHECK-NEXT: %rbp = COPY %rax
 # CHECK-NEXT: NOOP implicit %rax, implicit %rbp
 name: nocopyprop0
-allVRegsAllocated: true
 body: |
   bb.0:
     %rax = COPY %rbp
     CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp
     %rbp = COPY %rax
     NOOP implicit %rax, implicit %rbp
 ...
 ---
 # The second copy is not redundant if the dest register (%rax) is clobbered
 # even if the source (%rbp) is not.
 # CHECK-LABEL: name: nocopyprop1
 # CHECK: bb.0:
 # CHECK-NEXT: %rbp = COPY %rax
 # CHECK-NEXT: CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp
 # CHECK-NEXT: %rax = COPY %rbp
 # CHECK-NEXT: NOOP implicit %rax, implicit %rbp
 name: nocopyprop1
-allVRegsAllocated: true
 body: |
   bb.0:
     %rbp = COPY %rax
     CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp
     %rax = COPY %rbp
     NOOP implicit %rax, implicit %rbp
 ...
 ---
 # The second copy is not redundant if the source register (%rax) is clobbered
 # even if the dest (%rbp) is not.
 # CHECK-LABEL: name: nocopyprop2
 # CHECK: bb.0:
 # CHECK-NEXT: %rax = COPY %rbp
 # CHECK-NEXT: CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp
 # CHECK-NEXT: %rax = COPY %rbp
 # CHECK-NEXT: NOOP implicit %rax, implicit %rbp
 name: nocopyprop2
-allVRegsAllocated: true
 body: |
   bb.0:
     %rax = COPY %rbp
     CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp
     %rax = COPY %rbp
     NOOP implicit %rax, implicit %rbp
 ...
 ---
 # The second copy is not redundant if the dest register (%rax) is clobbered
 # even if the source (%rbp) is not.
 # CHECK-LABEL: name: nocopyprop3
 # CHECK: bb.0:
 # CHECK-NEXT: %rbp = COPY %rax
 # CHECK-NEXT: CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp
 # CHECK-NEXT: %rbp = COPY %rax
 # CHECK-NEXT: NOOP implicit %rax, implicit %rbp
 name: nocopyprop3
-allVRegsAllocated: true
 body: |
   bb.0:
     %rbp = COPY %rax
     CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp
     %rbp = COPY %rax
     NOOP implicit %rax, implicit %rbp
 ...
 ---
 # A reserved register may change its value so the 2nd copy is not redundant.
 # CHECK-LABEL: name: nocopyprop4
 # CHECK: bb.0:
 # CHECK-NEXT: %rax = COPY %rip
 # CHECK-NEXT: NOOP implicit %rax
 # CHECK-NEXT: %rax = COPY %rip
 # CHECK-NEXT: NOOP implicit %rax
 name: nocopyprop4
-allVRegsAllocated: true
 body: |
   bb.0:
     %rax = COPY %rip
     NOOP implicit %rax
     %rax = COPY %rip
     NOOP implicit %rax
 ...
 ---
 # Writing to a reserved register may have additional effects (slightly illegal
 # testcase because writing to %rip like this should make the instruction a jump)
 # CHECK-LABEL: name: nocopyprop5
 # CHECK: bb.0:
 # CHECK-NEXT: %rip = COPY %rax
 # CHECK-NEXT: %rip = COPY %rax
 name: nocopyprop5
-allVRegsAllocated: true
 body: |
   bb.0:
     %rip = COPY %rax
     %rip = COPY %rax
 ...

test/CodeGen/X86/pr27681.mir

 # RUN: llc -mtriple=i386-unknown-linux-gnu -mcpu=slm -run-pass post-RA-sched -o - %s | FileCheck %s
 #
 # Verify that the critical antidependence breaker does not consider
 # a high byte register as available as a replacement register
 # in a certain context.
 --- |
 
   define void @main() { ret void }
 
 ...
 ---
 # CHECK-LABEL: main
 name:            main
-allVRegsAllocated: true
 tracksRegLiveness: true
 frameInfo:
   stackSize:       52
 fixedStack:
   - { id: 0, type: spill-slot, offset: -20, size: 4, alignment: 4, callee-saved-register: '%esi' }
   - { id: 1, type: spill-slot, offset: -16, size: 4, alignment: 4, callee-saved-register: '%edi' }
   - { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4, callee-saved-register: '%ebx' }
   - { id: 3, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%ebp' }

test/DebugInfo/MIR/X86/live-debug-values-3preds.mir

--- |
   !50 = !DILocation(line: 17, column: 3, scope: !4)
 
 ...
 ---
 name:            add
 alignment:       4
 exposesReturnsTwice: false
 hasInlineAsm:    false
-allVRegsAllocated: true
 isSSA:           false
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 liveins:         
   - { reg: '%edi' }
   - { reg: '%esi' }
   - { reg: '%edx' }
   - { reg: '%ecx' }

test/DebugInfo/MIR/X86/live-debug-values.mir

--- |
   !47 = !DILocation(line: 20, column: 3, scope: !4)
 
 ...
 ---
 name:            main
 alignment:       4
 exposesReturnsTwice: false
 hasInlineAsm:    false
-allVRegsAllocated: true
 isSSA:           false
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 liveins:         
   - { reg: '%edi' }
   - { reg: '%rsi' }
 calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx', 
                         '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15',