[AArch64] Cache line size and PredictableSelectIsExpensive for Vulcan

[pgode]

Summary

Adding Cache line size and PredictableSelectIsExpensive for Vulcan

[MatzeB]

I can't comment on whether this is the right thing for Vulcan (not sure if any of the reviewers can). The changes to the backend are obviously fine.

[flyingforyou]

lib/Target/AArch64/AArch64Subtarget.cpp

78

CacheLineSize is only used for LoopDataPrefetch. Is there any reason that you define this vaule only?

Without defining PrefetchDistance, MinPrefetchStride, MaxPrefetchIterationsAhead, it's not worth it right now.

[pgode]

lib/Target/AArch64/AArch64Subtarget.cpp

78

I agree that apart from CacheLineSize, we need the other parameters for LoopDataPrefetch to be effective.
We are still working on defining other values. So I think, I better ignore this change from the patch & submit it as separate patch when I have other parameters as well.

The 2nd change i.e.PredictableSelectIsExpensive, still hold true for Vulcan. So, I am updating the diff.
Please suggest, if this change is fine.

[pgode]

Removed the CacheLineSize (set to 64) for Vulcan, as three other parameters are required for LoopDataPrefetch to be effective.
Will include CacheLineSize & 3 other parameters in another patch, after they are finalized.

[mcrosier]

LGTM.

[t.p.northover]

Sorry, yep I can't see any problem with putting it on 3.9.

lib/Target/AArch64/AArch64.td

 def ProcVulcan  : SubtargetFeature<"vulcan", "ARMProcFamily", "Vulcan",
                                    "Broadcom Vulcan processors", [
                                    FeatureCRC,
                                    FeatureCrypto,
                                    FeatureFPARMv8,
                                    FeatureMacroOpFusion,
                                    FeatureNEON,
                                    FeaturePostRAScheduler,
+                                   FeaturePredictableSelectIsExpensive,
                                    HasV8_1aOps]>;
 
 def : ProcessorModel<"generic", NoSchedModel, [
                      FeatureCRC,
                      FeatureFPARMv8,
                      FeatureNEON,
                      FeaturePerfMon,
                      FeaturePostRAScheduler

lib/Target/AArch64/AArch64Subtarget.cpp

case Kryo:
     MaxInterleaveFactor = 4;
     VectorInsertExtractBaseCost = 2;
     CacheLineSize = 128;
     PrefetchDistance = 740;
     MinPrefetchStride = 1024;
     MaxPrefetchIterationsAhead = 11;
     break;
   case Vulcan:
+    CacheLineSize = 64;
     MaxInterleaveFactor = 4;
     break;
   case CortexA35: break;
   case CortexA53: break;
   case CortexA72: break;
   case CortexA73: break;
   case Others: break;
   }