Add RenderScript ArchType

[pirama]

Summary

Add renderscript32 and renderscript64 ArchTypes. This is to configure
the ABI requirement on 32-bit RenderScript that 'long' types have 64-bit
size and alignment. 64-bit RenderScript is the same as AArch64, but is
added here for completeness.

[pirama]

D21334 is the corresponding patch to Clang.

[pirama]

This patch is based on the discussion in D20709.

[pirama]

Ping...

[echristo]

This is fine, thanks!

-eric

[pirama]

Rebased with a conflicting change.

llvm/trunk/include/llvm/ADT/Triple.h

 ///
 /// See autoconf/config.guess for a glimpse into what configuration names
 /// look like in practice.
 class Triple {
 public:
   enum ArchType {
     UnknownArch,
 
-    arm,        // ARM (little endian): arm, armv.*, xscale
-    armeb,      // ARM (big endian): armeb
-    aarch64,    // AArch64 (little endian): aarch64
-    aarch64_be, // AArch64 (big endian): aarch64_be
-    avr,        // AVR: Atmel AVR microcontroller
-    bpfel,      // eBPF or extended BPF or 64-bit BPF (little endian)
-    bpfeb,      // eBPF or extended BPF or 64-bit BPF (big endian)
-    hexagon,    // Hexagon: hexagon
-    mips,       // MIPS: mips, mipsallegrex
-    mipsel,     // MIPSEL: mipsel, mipsallegrexel
-    mips64,     // MIPS64: mips64
-    mips64el,   // MIPS64EL: mips64el
-    msp430,     // MSP430: msp430
-    ppc,        // PPC: powerpc
-    ppc64,      // PPC64: powerpc64, ppu
-    ppc64le,    // PPC64LE: powerpc64le
-    r600,       // R600: AMD GPUs HD2XXX - HD6XXX
-    amdgcn,     // AMDGCN: AMD GCN GPUs
-    sparc,      // Sparc: sparc
-    sparcv9,    // Sparcv9: Sparcv9
-    sparcel,    // Sparc: (endianness = little). NB: 'Sparcle' is a CPU variant
-    systemz,    // SystemZ: s390x
-    tce,        // TCE (http://tce.cs.tut.fi/): tce
-    thumb,      // Thumb (little endian): thumb, thumbv.*
-    thumbeb,    // Thumb (big endian): thumbeb
-    x86,        // X86: i[3-9]86
-    x86_64,     // X86-64: amd64, x86_64
-    xcore,      // XCore: xcore
-    nvptx,      // NVPTX: 32-bit
-    nvptx64,    // NVPTX: 64-bit
-    le32,       // le32: generic little-endian 32-bit CPU (PNaCl)
-    le64,       // le64: generic little-endian 64-bit CPU (PNaCl)
-    amdil,      // AMDIL
-    amdil64,    // AMDIL with 64-bit pointers
-    hsail,      // AMD HSAIL
-    hsail64,    // AMD HSAIL with 64-bit pointers
-    spir,       // SPIR: standard portable IR for OpenCL 32-bit version
-    spir64,     // SPIR: standard portable IR for OpenCL 64-bit version
-    kalimba,    // Kalimba: generic kalimba
-    shave,      // SHAVE: Movidius vector VLIW processors
-    lanai,      // Lanai: Lanai 32-bit
-    wasm32,     // WebAssembly with 32-bit pointers
-    wasm64,     // WebAssembly with 64-bit pointers
-    LastArchType = wasm64
+    arm,            // ARM (little endian): arm, armv.*, xscale
+    armeb,          // ARM (big endian): armeb
+    aarch64,        // AArch64 (little endian): aarch64
+    aarch64_be,     // AArch64 (big endian): aarch64_be
+    avr,            // AVR: Atmel AVR microcontroller
+    bpfel,          // eBPF or extended BPF or 64-bit BPF (little endian)
+    bpfeb,          // eBPF or extended BPF or 64-bit BPF (big endian)
+    hexagon,        // Hexagon: hexagon
+    mips,           // MIPS: mips, mipsallegrex
+    mipsel,         // MIPSEL: mipsel, mipsallegrexel
+    mips64,         // MIPS64: mips64
+    mips64el,       // MIPS64EL: mips64el
+    msp430,         // MSP430: msp430
+    ppc,            // PPC: powerpc
+    ppc64,          // PPC64: powerpc64, ppu
+    ppc64le,        // PPC64LE: powerpc64le
+    r600,           // R600: AMD GPUs HD2XXX - HD6XXX
+    amdgcn,         // AMDGCN: AMD GCN GPUs
+    sparc,          // Sparc: sparc
+    sparcv9,        // Sparcv9: Sparcv9
+    sparcel,        // Sparc: (endianness = little). NB: 'Sparcle' is a CPU variant
+    systemz,        // SystemZ: s390x
+    tce,            // TCE (http://tce.cs.tut.fi/): tce
+    thumb,          // Thumb (little endian): thumb, thumbv.*
+    thumbeb,        // Thumb (big endian): thumbeb
+    x86,            // X86: i[3-9]86
+    x86_64,         // X86-64: amd64, x86_64
+    xcore,          // XCore: xcore
+    nvptx,          // NVPTX: 32-bit
+    nvptx64,        // NVPTX: 64-bit
+    le32,           // le32: generic little-endian 32-bit CPU (PNaCl)
+    le64,           // le64: generic little-endian 64-bit CPU (PNaCl)
+    amdil,          // AMDIL
+    amdil64,        // AMDIL with 64-bit pointers
+    hsail,          // AMD HSAIL
+    hsail64,        // AMD HSAIL with 64-bit pointers
+    spir,           // SPIR: standard portable IR for OpenCL 32-bit version
+    spir64,         // SPIR: standard portable IR for OpenCL 64-bit version
+    kalimba,        // Kalimba: generic kalimba
+    shave,          // SHAVE: Movidius vector VLIW processors
+    lanai,          // Lanai: Lanai 32-bit
+    wasm32,         // WebAssembly with 32-bit pointers
+    wasm64,         // WebAssembly with 64-bit pointers
+    renderscript32, // 32-bit RenderScript
+    renderscript64, // 64-bit RenderScript
+    LastArchType = renderscript64
   };
   enum SubArchType {
     NoSubArch,
 
     ARMSubArch_v8_2a,
     ARMSubArch_v8_1a,
     ARMSubArch_v8,
     ARMSubArch_v8m_baseline,

llvm/trunk/lib/Support/Triple.cpp

 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetParser.h"
 #include "llvm/Support/Host.h"
 #include <cstring>
 using namespace llvm;
 
 const char *Triple::getArchTypeName(ArchType Kind) {
   switch (Kind) {
-  case UnknownArch: return "unknown";
+  case UnknownArch:    return "unknown";
 
-  case aarch64:     return "aarch64";
-  case aarch64_be:  return "aarch64_be";
-  case arm:         return "arm";
-  case armeb:       return "armeb";
-  case avr:         return "avr";
-  case bpfel:       return "bpfel";
-  case bpfeb:       return "bpfeb";
-  case hexagon:     return "hexagon";
-  case mips:        return "mips";
-  case mipsel:      return "mipsel";
-  case mips64:      return "mips64";
-  case mips64el:    return "mips64el";
-  case msp430:      return "msp430";
-  case ppc64:       return "powerpc64";
-  case ppc64le:     return "powerpc64le";
-  case ppc:         return "powerpc";
-  case r600:        return "r600";
-  case amdgcn:      return "amdgcn";
-  case sparc:       return "sparc";
-  case sparcv9:     return "sparcv9";
-  case sparcel:     return "sparcel";
-  case systemz:     return "s390x";
-  case tce:         return "tce";
-  case thumb:       return "thumb";
-  case thumbeb:     return "thumbeb";
-  case x86:         return "i386";
-  case x86_64:      return "x86_64";
-  case xcore:       return "xcore";
-  case nvptx:       return "nvptx";
-  case nvptx64:     return "nvptx64";
-  case le32:        return "le32";
-  case le64:        return "le64";
-  case amdil:       return "amdil";
-  case amdil64:     return "amdil64";
-  case hsail:       return "hsail";
-  case hsail64:     return "hsail64";
-  case spir:        return "spir";
-  case spir64:      return "spir64";
-  case kalimba:     return "kalimba";
-  case lanai:       return "lanai";
-  case shave:       return "shave";
-  case wasm32:      return "wasm32";
-  case wasm64:      return "wasm64";
+  case aarch64:        return "aarch64";
+  case aarch64_be:     return "aarch64_be";
+  case arm:            return "arm";
+  case armeb:          return "armeb";
+  case avr:            return "avr";
+  case bpfel:          return "bpfel";
+  case bpfeb:          return "bpfeb";
+  case hexagon:        return "hexagon";
+  case mips:           return "mips";
+  case mipsel:         return "mipsel";
+  case mips64:         return "mips64";
+  case mips64el:       return "mips64el";
+  case msp430:         return "msp430";
+  case ppc64:          return "powerpc64";
+  case ppc64le:        return "powerpc64le";
+  case ppc:            return "powerpc";
+  case r600:           return "r600";
+  case amdgcn:         return "amdgcn";
+  case sparc:          return "sparc";
+  case sparcv9:        return "sparcv9";
+  case sparcel:        return "sparcel";
+  case systemz:        return "s390x";
+  case tce:            return "tce";
+  case thumb:          return "thumb";
+  case thumbeb:        return "thumbeb";
+  case x86:            return "i386";
+  case x86_64:         return "x86_64";
+  case xcore:          return "xcore";
+  case nvptx:          return "nvptx";
+  case nvptx64:        return "nvptx64";
+  case le32:           return "le32";
+  case le64:           return "le64";
+  case amdil:          return "amdil";
+  case amdil64:        return "amdil64";
+  case hsail:          return "hsail";
+  case hsail64:        return "hsail64";
+  case spir:           return "spir";
+  case spir64:         return "spir64";
+  case kalimba:        return "kalimba";
+  case lanai:          return "lanai";
+  case shave:          return "shave";
+  case wasm32:         return "wasm32";
+  case wasm64:         return "wasm64";
+  case renderscript32: return "renderscript32";
+  case renderscript64: return "renderscript64";
   }
 
   llvm_unreachable("Invalid ArchType!");
 }
 
 const char *Triple::getArchTypePrefix(ArchType Kind) {
   switch (Kind) {
   default:
return StringSwitch<Triple::ArchType>(Name)
     .Case("hsail64", hsail64)
     .Case("spir", spir)
     .Case("spir64", spir64)
     .Case("kalimba", kalimba)
     .Case("lanai", lanai)
     .Case("shave", shave)
     .Case("wasm32", wasm32)
     .Case("wasm64", wasm64)
+    .Case("renderscript32", renderscript32)
+    .Case("renderscript64", renderscript64)
     .Default(UnknownArch);
 }
 
 static Triple::ArchType parseARMArch(StringRef ArchName) {
   unsigned ISA = ARM::parseArchISA(ArchName);
   unsigned ENDIAN = ARM::parseArchEndian(ArchName);
 
   Triple::ArchType arch = Triple::UnknownArch;
auto AT = StringSwitch<Triple::ArchType>(ArchName)
     .Case("hsail64", Triple::hsail64)
     .Case("spir", Triple::spir)
     .Case("spir64", Triple::spir64)
     .StartsWith("kalimba", Triple::kalimba)
     .Case("lanai", Triple::lanai)
     .Case("shave", Triple::shave)
     .Case("wasm32", Triple::wasm32)
     .Case("wasm64", Triple::wasm64)
+    .Case("renderscript32", Triple::renderscript32)
+    .Case("renderscript64", Triple::renderscript64)
     .Default(Triple::UnknownArch);
 
   // Some architectures require special parsing logic just to compute the
   // ArchType result.
   if (AT == Triple::UnknownArch) {
     if (ArchName.startswith("arm") || ArchName.startswith("thumb") ||
         ArchName.startswith("aarch64"))
       return parseARMArch(ArchName);
static Triple::ObjectFormatType getDefaultFormat(const Triple &T) {
   case Triple::mips64:
   case Triple::mips64el:
   case Triple::mipsel:
   case Triple::msp430:
   case Triple::nvptx:
   case Triple::nvptx64:
   case Triple::ppc64le:
   case Triple::r600:
+  case Triple::renderscript32:
+  case Triple::renderscript64:
   case Triple::shave:
   case Triple::sparc:
   case Triple::sparcel:
   case Triple::sparcv9:
   case Triple::spir:
   case Triple::spir64:
   case Triple::systemz:
   case Triple::tce:
static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
   case llvm::Triple::xcore:
   case llvm::Triple::amdil:
   case llvm::Triple::hsail:
   case llvm::Triple::spir:
   case llvm::Triple::kalimba:
   case llvm::Triple::lanai:
   case llvm::Triple::shave:
   case llvm::Triple::wasm32:
+  case llvm::Triple::renderscript32:
     return 32;
 
   case llvm::Triple::aarch64:
   case llvm::Triple::aarch64_be:
   case llvm::Triple::amdgcn:
   case llvm::Triple::bpfel:
   case llvm::Triple::bpfeb:
   case llvm::Triple::le64:
   case llvm::Triple::mips64:
   case llvm::Triple::mips64el:
   case llvm::Triple::nvptx64:
   case llvm::Triple::ppc64:
   case llvm::Triple::ppc64le:
   case llvm::Triple::sparcv9:
   case llvm::Triple::systemz:
   case llvm::Triple::x86_64:
   case llvm::Triple::amdil64:
   case llvm::Triple::hsail64:
   case llvm::Triple::spir64:
   case llvm::Triple::wasm64:
+  case llvm::Triple::renderscript64:
     return 64;
   }
   llvm_unreachable("Invalid architecture value");
 }
 
 bool Triple::isArch64Bit() const {
   return getArchPointerBitWidth(getArch()) == 64;
 }
Triple Triple::get32BitArchVariant() const {
   case Triple::tce:
   case Triple::thumb:
   case Triple::thumbeb:
   case Triple::x86:
   case Triple::xcore:
   case Triple::lanai:
   case Triple::shave:
   case Triple::wasm32:
+  case Triple::renderscript32:
     // Already 32-bit.
     break;
 
-  case Triple::aarch64:    T.setArch(Triple::arm);     break;
-  case Triple::aarch64_be: T.setArch(Triple::armeb);   break;
-  case Triple::le64:       T.setArch(Triple::le32);    break;
-  case Triple::mips64:     T.setArch(Triple::mips);    break;
-  case Triple::mips64el:   T.setArch(Triple::mipsel);  break;
-  case Triple::nvptx64:    T.setArch(Triple::nvptx);   break;
-  case Triple::ppc64:      T.setArch(Triple::ppc);     break;
-  case Triple::sparcv9:    T.setArch(Triple::sparc);   break;
-  case Triple::x86_64:     T.setArch(Triple::x86);     break;
-  case Triple::amdil64:    T.setArch(Triple::amdil);   break;
-  case Triple::hsail64:    T.setArch(Triple::hsail);   break;
-  case Triple::spir64:     T.setArch(Triple::spir);    break;
-  case Triple::wasm64:     T.setArch(Triple::wasm32);  break;
+  case Triple::aarch64:        T.setArch(Triple::arm);     break;
+  case Triple::aarch64_be:     T.setArch(Triple::armeb);   break;
+  case Triple::le64:           T.setArch(Triple::le32);    break;
+  case Triple::mips64:         T.setArch(Triple::mips);    break;
+  case Triple::mips64el:       T.setArch(Triple::mipsel);  break;
+  case Triple::nvptx64:        T.setArch(Triple::nvptx);   break;
+  case Triple::ppc64:          T.setArch(Triple::ppc);     break;
+  case Triple::sparcv9:        T.setArch(Triple::sparc);   break;
+  case Triple::x86_64:         T.setArch(Triple::x86);     break;
+  case Triple::amdil64:        T.setArch(Triple::amdil);   break;
+  case Triple::hsail64:        T.setArch(Triple::hsail);   break;
+  case Triple::spir64:         T.setArch(Triple::spir);    break;
+  case Triple::wasm64:         T.setArch(Triple::wasm32);  break;
+  case Triple::renderscript64: T.setArch(Triple::renderscript32); break;
   }
   return T;
 }
 
 Triple Triple::get64BitArchVariant() const {
   Triple T(*this);
   switch (getArch()) {
   case Triple::UnknownArch:
Triple Triple::get64BitArchVariant() const {
   case Triple::mips64el:
   case Triple::nvptx64:
   case Triple::ppc64:
   case Triple::ppc64le:
   case Triple::sparcv9:
   case Triple::systemz:
   case Triple::x86_64:
   case Triple::wasm64:
+  case Triple::renderscript64:
     // Already 64-bit.
     break;
 
-  case Triple::arm:     T.setArch(Triple::aarch64);    break;
-  case Triple::armeb:   T.setArch(Triple::aarch64_be); break;
-  case Triple::le32:    T.setArch(Triple::le64);       break;
-  case Triple::mips:    T.setArch(Triple::mips64);     break;
-  case Triple::mipsel:  T.setArch(Triple::mips64el);   break;
-  case Triple::nvptx:   T.setArch(Triple::nvptx64);    break;
-  case Triple::ppc:     T.setArch(Triple::ppc64);      break;
-  case Triple::sparc:   T.setArch(Triple::sparcv9);    break;
-  case Triple::x86:     T.setArch(Triple::x86_64);     break;
-  case Triple::amdil:   T.setArch(Triple::amdil64);    break;
-  case Triple::hsail:   T.setArch(Triple::hsail64);    break;
-  case Triple::spir:    T.setArch(Triple::spir64);     break;
-  case Triple::thumb:   T.setArch(Triple::aarch64);    break;
-  case Triple::thumbeb: T.setArch(Triple::aarch64_be); break;
-  case Triple::wasm32:  T.setArch(Triple::wasm64);     break;
+  case Triple::arm:             T.setArch(Triple::aarch64);    break;
+  case Triple::armeb:           T.setArch(Triple::aarch64_be); break;
+  case Triple::le32:            T.setArch(Triple::le64);       break;
+  case Triple::mips:            T.setArch(Triple::mips64);     break;
+  case Triple::mipsel:          T.setArch(Triple::mips64el);   break;
+  case Triple::nvptx:           T.setArch(Triple::nvptx64);    break;
+  case Triple::ppc:             T.setArch(Triple::ppc64);      break;
+  case Triple::sparc:           T.setArch(Triple::sparcv9);    break;
+  case Triple::x86:             T.setArch(Triple::x86_64);     break;
+  case Triple::amdil:           T.setArch(Triple::amdil64);    break;
+  case Triple::hsail:           T.setArch(Triple::hsail64);    break;
+  case Triple::spir:            T.setArch(Triple::spir64);     break;
+  case Triple::thumb:           T.setArch(Triple::aarch64);    break;
+  case Triple::thumbeb:         T.setArch(Triple::aarch64_be); break;
+  case Triple::wasm32:          T.setArch(Triple::wasm64);     break;
+  case Triple::renderscript32:  T.setArch(Triple::renderscript64);     break;
   }
   return T;
 }
 
 Triple Triple::getBigEndianArchVariant() const {
   Triple T(*this);
   // Already big endian.
   if (!isLittleEndian())
Triple Triple::getBigEndianArchVariant() const {
   case Triple::shave:
   case Triple::spir64:
   case Triple::spir:
   case Triple::wasm32:
   case Triple::wasm64:
   case Triple::x86:
   case Triple::x86_64:
   case Triple::xcore:
+  case Triple::renderscript32:
+  case Triple::renderscript64:
 
   // ARM is intentionally unsupported here, changing the architecture would
   // drop any arch suffixes.
   case Triple::arm:
   case Triple::thumb:
     T.setArch(UnknownArch);
     break;
 
bool Triple::isLittleEndian() const {
   case Triple::spir64:
   case Triple::spir:
   case Triple::thumb:
   case Triple::wasm32:
   case Triple::wasm64:
   case Triple::x86:
   case Triple::x86_64:
   case Triple::xcore:
+  case Triple::renderscript32:
+  case Triple::renderscript64:
     return true;
   default:
     return false;
   }
 }
 
 StringRef Triple::getARMCPUForArch(StringRef MArch) const {
   if (MArch.empty())