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Differential D19857

[mips][microMIPS] Add CodeGen support for microMIPSr6 ROTR and ROTRV and add tests for LL, SC, SYSCALL, ROTR, ROTRV, LWM32, SWM32 and MOVEP instructions
ClosedPublic

Authored by zbuljan on May 3 2016, 12:08 AM.

Details

Reviewers
dsanders
sdardis
vkalintiris
zoran.jovanovic
hvarga
Commits
rL268491: [mips][microMIPS] Add CodeGen support for microMIPSr6 ROTR and ROTRV and add…
Summary

The patch adds CodeGen support for microMIPSr6 ROTR and ROTRV instructions and also adds the standard tests for existing microMIPS LL, SC, SYSCALL, ROTR, ROTRV, LWM32, SWM32 and MOVEP instruction definitions:

  • separated microMIPS LL, SC, ROTR and ROTRV instructions from equivalent MIPS instructions using NotInMicroMips predicate
  • added alias definitions for ROTR and SYSCALL instructions
  • added DAG patterns to description classes for proper selection of ROTR and ROTRV instructions
  • updated isMovePRegPair() method (MipsAsmParser.cpp) for MOVEP instruction
  • updated CodeGen tests for microMIPSr6 (rotate.ll)
  • added tests for the standard encodings
  • added invalid tests

There was a problem with commit rL266977 of the previous patch D19150.
Test-suite failed with error message:

fatal error: error in backend: Cannot select: t17: i32 = rotr t2, t11
...

The problem was with selecting microMIPS ROTR and ROTRV instructions in LLVM backend.
For that reason I decided to revert commit rL266977 and make this patch which besides standard regression tests also includes CodeGen support for ROTR and ROTRV instructions.

Diff Detail

Event Timeline

zbuljan updated this revision to Diff 55951.May 3 2016, 12:08 AM
zbuljan retitled this revision from to [mips][microMIPS] Add CodeGen support for microMIPSr6 ROTR and ROTRV and add tests for LL, SC, SYSCALL, ROTR, ROTRV, LWM32, SWM32 and MOVEP instructions.
zbuljan updated this object.
zbuljan added reviewers: dsanders, sdardis, hvarga, zoran.jovanovic.
zbuljan added subscribers: petarj, llvm-commits.
Herald added a reviewer: vkalintiris. · View Herald TranscriptMay 3 2016, 12:09 AM
Herald added subscribers: sdardis, dsanders. · View Herald Transcript
sdardis accepted this revision.May 3 2016, 2:57 AM
sdardis edited edge metadata.

LGTM. Apologies, I should have caught the failure to select rotr.

This revision is now accepted and ready to land.May 3 2016, 2:57 AM
Closed by commit rL268491: [mips][microMIPS] Add CodeGen support for microMIPSr6 ROTR and ROTRV and add… (authored by zbuljan). · Explain WhyMay 4 2016, 5:08 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Mips/
AsmParser/
10 lines
13 lines
6 lines
16 lines
test/
CodeGen/
Mips/
10 lines
MC/
Disassembler/
Mips/
micromips32r3/
2 lines
2 lines
micromips32r6/
10 lines
micromips64r6/
10 lines
Mips/
micromips/
1 line
4 lines
micromips32r6/
3 lines
16 lines
22 lines
micromips64r6/
3 lines
16 lines
22 lines

Diff 55951

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Show First 20 Lines • Show All 1,134 Lines • ▼ Show 20 Lines bool isMovePRegPair() const {
if ((R0 == Mips::A1 && R1 == Mips::A2) || if ((R0 == Mips::A1 && R1 == Mips::A2) ||
(R0 == Mips::A1 && R1 == Mips::A3) || (R0 == Mips::A1 && R1 == Mips::A3) ||
(R0 == Mips::A2 && R1 == Mips::A3) || (R0 == Mips::A2 && R1 == Mips::A3) ||
(R0 == Mips::A0 && R1 == Mips::S5) || (R0 == Mips::A0 && R1 == Mips::S5) ||
(R0 == Mips::A0 && R1 == Mips::S6) || (R0 == Mips::A0 && R1 == Mips::S6) ||
(R0 == Mips::A0 && R1 == Mips::A1) || (R0 == Mips::A0 && R1 == Mips::A1) ||
(R0 == Mips::A0 && R1 == Mips::A2) || (R0 == Mips::A0 && R1 == Mips::A2) ||
(R0 == Mips::A0 && R1 == Mips::A3)) (R0 == Mips::A0 && R1 == Mips::A3) ||
(R0 == Mips::A1_64 && R1 == Mips::A2_64) ||
(R0 == Mips::A1_64 && R1 == Mips::A3_64) ||
(R0 == Mips::A2_64 && R1 == Mips::A3_64) ||
(R0 == Mips::A0_64 && R1 == Mips::S5_64) ||
(R0 == Mips::A0_64 && R1 == Mips::S6_64) ||
(R0 == Mips::A0_64 && R1 == Mips::A1_64) ||
(R0 == Mips::A0_64 && R1 == Mips::A2_64) ||
(R0 == Mips::A0_64 && R1 == Mips::A3_64))
return true; return true;
return false; return false;
} }
StringRef getToken() const { StringRef getToken() const {
assert(Kind == k_Token && "Invalid access!"); assert(Kind == k_Token && "Invalid access!");
return StringRef(Tok.Data, Tok.Length); return StringRef(Tok.Data, Tok.Length);
▲ Show 20 Lines • Show All 5,194 Lines • Show Last 20 Lines

lib/Target/Mips/MicroMipsInstrInfo.td

Show First 20 Lines • Show All 711 Lines • ▼ Show 20 Lines def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
SRA_FM_MM<0x80, 0>; SRA_FM_MM<0x80, 0>;
def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>, def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
SRLV_FM_MM<0x10, 0>; SRLV_FM_MM<0x10, 0>;
def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>, def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
SRLV_FM_MM<0x50, 0>; SRLV_FM_MM<0x50, 0>;
def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>, def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
SRLV_FM_MM<0x90, 0>; SRLV_FM_MM<0x90, 0>;
def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>, def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
SRA_FM_MM<0xc0, 0>; SRA_FM_MM<0xc0, 0> {
list<dag> Pattern = [(set GPR32Opnd:$rd,
(rotr GPR32Opnd:$rt, immZExt5:$shamt))];
}
def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>, def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
SRLV_FM_MM<0xd0, 0>; SRLV_FM_MM<0xd0, 0> {
list<dag> Pattern = [(set GPR32Opnd:$rd,
(rotr GPR32Opnd:$rt, GPR32Opnd:$rs))];
}
/// Load and Store Instructions - aligned /// Load and Store Instructions - aligned
let DecoderMethod = "DecodeMemMMImm16" in { let DecoderMethod = "DecodeMemMMImm16" in {
def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>; def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>; def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>; def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>; def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>; def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
▲ Show 20 Lines • Show All 319 Lines • ▼ Show 20 Lines
def : MipsInstAlias<"srl $rd, $rt", def : MipsInstAlias<"srl $rd, $rt",
(SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>; (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
def : MipsInstAlias<"sll $rd, $shamt", def : MipsInstAlias<"sll $rd, $shamt",
(SLL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; (SLL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
def : MipsInstAlias<"sra $rd, $shamt", def : MipsInstAlias<"sra $rd, $shamt",
(SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; (SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
def : MipsInstAlias<"srl $rd, $shamt", def : MipsInstAlias<"srl $rd, $shamt",
(SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; (SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
def : MipsInstAlias<"rotr $rt, $imm",
(ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>;
def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>;
} }

lib/Target/Mips/Mips32r6InstrInfo.td

Show First 20 Lines • Show All 751 Lines • ▼ Show 20 Lines
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def DIV : R6MMR6Rel, DIV_ENC, DIV_DESC, ISA_MIPS32R6; def DIV : R6MMR6Rel, DIV_ENC, DIV_DESC, ISA_MIPS32R6;
def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, ISA_MIPS32R6; def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
} }
def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6; def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6; def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6;
def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6; def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6; def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in {
def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6; def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6;
}
def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6; def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6;
def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6; def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6;
def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6; def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6; def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT; def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT; def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT; def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
Show All 17 Lines
def MUHU : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6; def MUHU : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
def MUL_R6 : R6MMR6Rel, MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6; def MUL_R6 : R6MMR6Rel, MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
def MULU : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6; def MULU : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6;
def NAL; // BAL with rd=0 def NAL; // BAL with rd=0
def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6; def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT; def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT; def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6;
def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6; def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6;
} }
def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6;
def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6; def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32; def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6, HARDFLOAT; def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6, HARDFLOAT; def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6, HARDFLOAT;
} }
def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32; def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
▲ Show 20 Lines • Show All 102 Lines • Show Last 20 Lines

lib/Target/Mips/MipsInstrInfo.td

Show First 20 Lines • Show All 1,690 Lines • ▼ Show 20 Linesdef SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
SRLV_FM<4, 0>; SRLV_FM<4, 0>;
def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>, def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
SRLV_FM<6, 0>; SRLV_FM<6, 0>;
def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>, def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
SRLV_FM<7, 0>; SRLV_FM<7, 0>;
} }
// Rotate Instructions // Rotate Instructions
let AdditionalPredicates = [NotInMicroMips] in {
def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr, def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
immZExt5>, immZExt5>,
SRA_FM<2, 1>, ISA_MIPS32R2; SRA_FM<2, 1>, ISA_MIPS32R2;
def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>, def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
SRLV_FM<6, 1>, ISA_MIPS32R2; SRLV_FM<6, 1>, ISA_MIPS32R2;
}
/// Load and Store Instructions /// Load and Store Instructions
/// aligned /// aligned
def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>; def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel, def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
LW_FM<0x24>; LW_FM<0x24>;
def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel, def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
LW_FM<0x21>; LW_FM<0x21>;
▲ Show 20 Lines • Show All 498 Lines • ▼ Show 20 Lines
def : MipsInstAlias<"bnez $rs,$offset", def : MipsInstAlias<"bnez $rs,$offset",
(BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
def : MipsInstAlias<"bnezl $rs,$offset", def : MipsInstAlias<"bnezl $rs,$offset",
(BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
def : MipsInstAlias<"beqz $rs,$offset", def : MipsInstAlias<"beqz $rs,$offset",
(BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
def : MipsInstAlias<"beqzl $rs,$offset", def : MipsInstAlias<"beqzl $rs,$offset",
(BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"syscall", (SYSCALL 0), 1>; def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
}
def : MipsInstAlias<"break", (BREAK 0, 0), 1>; def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2; def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2; def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
} }
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
▲ Show 20 Lines • Show All 412 Lines • Show Last 20 Lines

test/CodeGen/Mips/rotate.ll

; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s ; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s
; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32r2 -mattr=+mips16 < %s | FileCheck %s -check-prefix=mips16 ; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32r2 -mattr=+mips16 < %s | FileCheck %s -check-prefix=mips16
; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips < %s | FileCheck %s \
; RUN: -check-prefix=MM32
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips < %s | FileCheck %s \
; RUN: -check-prefix=MM32
; CHECK: rotrv $2, $4 ; CHECK: rotrv $2, $4
; mips16: .ent rot0 ; mips16: .ent rot0
; MM32: li16 $2, 32
; MM32: subu16 $2, $2, $5
; MM32: rotrv $2, $4, $2
define i32 @rot0(i32 %a, i32 %b) nounwind readnone { define i32 @rot0(i32 %a, i32 %b) nounwind readnone {
entry: entry:
%shl = shl i32 %a, %b %shl = shl i32 %a, %b
%sub = sub i32 32, %b %sub = sub i32 32, %b
%shr = lshr i32 %a, %sub %shr = lshr i32 %a, %sub
%or = or i32 %shr, %shl %or = or i32 %shr, %shl
ret i32 %or ret i32 %or
} }
; CHECK: rotr $2, $4, 22 ; CHECK: rotr $2, $4, 22
; mips16: .ent rot1 ; mips16: .ent rot1
; MM32: rotr $2, $4, 22
define i32 @rot1(i32 %a) nounwind readnone { define i32 @rot1(i32 %a) nounwind readnone {
entry: entry:
%shl = shl i32 %a, 10 %shl = shl i32 %a, 10
%shr = lshr i32 %a, 22 %shr = lshr i32 %a, 22
%or = or i32 %shl, %shr %or = or i32 %shl, %shr
ret i32 %or ret i32 %or
} }
; CHECK: rotrv $2, $4, $5 ; CHECK: rotrv $2, $4, $5
; mips16: .ent rot2 ; mips16: .ent rot2
; MM32: rotrv $2, $4, $5
define i32 @rot2(i32 %a, i32 %b) nounwind readnone { define i32 @rot2(i32 %a, i32 %b) nounwind readnone {
entry: entry:
%shr = lshr i32 %a, %b %shr = lshr i32 %a, %b
%sub = sub i32 32, %b %sub = sub i32 32, %b
%shl = shl i32 %a, %sub %shl = shl i32 %a, %sub
%or = or i32 %shl, %shr %or = or i32 %shl, %shr
ret i32 %or ret i32 %or
} }
; CHECK: rotr $2, $4, 10 ; CHECK: rotr $2, $4, 10
; mips16: .ent rot3 ; mips16: .ent rot3
; MM32: rotr $2, $4, 10
define i32 @rot3(i32 %a) nounwind readnone { define i32 @rot3(i32 %a) nounwind readnone {
entry: entry:
%shr = lshr i32 %a, 10 %shr = lshr i32 %a, 10
%shl = shl i32 %a, 22 %shl = shl i32 %a, 22
%or = or i32 %shr, %shl %or = or i32 %shr, %shl
ret i32 %or ret i32 %or
} }

test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

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0xa4 0x60 0x08 0xaa # CHECK: she $5, 8($4) 0xa4 0x60 0x08 0xaa # CHECK: she $5, 8($4)
0xa4 0x60 0x08 0xae # CHECK: swe $5, 8($4) 0xa4 0x60 0x08 0xae # CHECK: swe $5, 8($4)
0x03 0x63 0x05 0xa2 # CHECK: swre $24, 5($3) 0x03 0x63 0x05 0xa2 # CHECK: swre $24, 5($3)
0x03 0x63 0x05 0xa0 # CHECK: swle $24, 5($3) 0x03 0x63 0x05 0xa0 # CHECK: swle $24, 5($3)
0x03 0x63 0x05 0x66 # CHECK: lwre $24, 5($3) 0x03 0x63 0x05 0x66 # CHECK: lwre $24, 5($3)
0x04 0x63 0x02 0x64 # CHECK: lwle $24, 2($4) 0x04 0x63 0x02 0x64 # CHECK: lwle $24, 2($4)
0x44 0x60 0x08 0x6c # CHECK: lle $2, 8($4) 0x44 0x60 0x08 0x6c # CHECK: lle $2, 8($4)
0x44 0x60 0x08 0xac # CHECK: sce $2, 8($4) 0x44 0x60 0x08 0xac # CHECK: sce $2, 8($4)
0x00 0x00 0x7c 0x8b # CHECK: syscall
0x8c 0x01 0x7c 0x8b # CHECK: syscall 396

test/MC/Disassembler/Mips/micromips32r3/valid.txt

Show First 20 Lines • Show All 183 Lines • ▼ Show 20 Lines
0x60 0xa4 0xaa 0x08 # CHECK: she $5, 8($4) 0x60 0xa4 0xaa 0x08 # CHECK: she $5, 8($4)
0x60 0xa4 0xae 0x08 # CHECK: swe $5, 8($4) 0x60 0xa4 0xae 0x08 # CHECK: swe $5, 8($4)
0x63 0x03 0xa2 0x05 # CHECK: swre $24, 5($3) 0x63 0x03 0xa2 0x05 # CHECK: swre $24, 5($3)
0x63 0x03 0xa0 0x05 # CHECK: swle $24, 5($3) 0x63 0x03 0xa0 0x05 # CHECK: swle $24, 5($3)
0x63 0x03 0x66 0x05 # CHECK: lwre $24, 5($3) 0x63 0x03 0x66 0x05 # CHECK: lwre $24, 5($3)
0x63 0x04 0x64 0x02 # CHECK: lwle $24, 2($4) 0x63 0x04 0x64 0x02 # CHECK: lwle $24, 2($4)
0x60 0x44 0x6c 0x08 # CHECK: lle $2, 8($4) 0x60 0x44 0x6c 0x08 # CHECK: lle $2, 8($4)
0x60 0x44 0xac 0x08 # CHECK: sce $2, 8($4) 0x60 0x44 0xac 0x08 # CHECK: sce $2, 8($4)
0x00 0x00 0x8b 0x7c # CHECK: syscall
0x01 0x8c 0x8b 0x7c # CHECK: syscall 396

test/MC/Disassembler/Mips/micromips32r6/valid.txt

Show All 15 Lines
0x45 0x23 # CHECK: jrc16 $9 0x45 0x23 # CHECK: jrc16 $9
0x44 0xb3 # CHECK: jrcaddiusp 20 0x44 0xb3 # CHECK: jrcaddiusp 20
0x65 0x88 # CHECK: lw $3, 32($gp) 0x65 0x88 # CHECK: lw $3, 32($gp)
0x48 0x66 # CHECK: lw $3, 24($sp) 0x48 0x66 # CHECK: lw $3, 24($sp)
0x6a 0x12 # CHECK: lw16 $4, 8($17) 0x6a 0x12 # CHECK: lw16 $4, 8($17)
0x29 0x82 # CHECK: lhu16 $3, 4($16) 0x29 0x82 # CHECK: lhu16 $3, 4($16)
0x09 0x94 # CHECK: lbu16 $3, 4($17) 0x09 0x94 # CHECK: lbu16 $3, 4($17)
0x09 0x9f # CHECK: lbu16 $3, -1($17) 0x09 0x9f # CHECK: lbu16 $3, -1($17)
0x84 0x34 # CHECK: movep $5, $6, $2, $3
0x04 0xcc # CHECK: addu16 $6, $17, $4 0x04 0xcc # CHECK: addu16 $6, $17, $4
0x44 0x21 # CHECK: and16 $16, $2 0x44 0x21 # CHECK: and16 $16, $2
0x2e 0x56 # CHECK: andi16 $4, $5, 8 0x2e 0x56 # CHECK: andi16 $4, $5, 8
0x46 0x70 # CHECK: not16 $4, $7 0x46 0x70 # CHECK: not16 $4, $7
0x45 0xf9 # CHECK: or16 $3, $7 0x45 0xf9 # CHECK: or16 $3, $7
0x25 0xe0 # CHECK: sll16 $3, $6, 8 0x25 0xe0 # CHECK: sll16 $3, $6, 8
0x25 0xe1 # CHECK: srl16 $3, $6, 8 0x25 0xe1 # CHECK: srl16 $3, $6, 8
0x00 0xa4 0x19 0x10 # CHECK: add $3, $4, $5 0x00 0xa4 0x19 0x10 # CHECK: add $3, $4, $5
Show All 32 Lines
0x00 0xa4 0x19 0x98 # CHECK: divu $3, $4, $5 0x00 0xa4 0x19 0x98 # CHECK: divu $3, $4, $5
0x00 0x00 0x18 0x00 # CHECK: ehb 0x00 0x00 0x18 0x00 # CHECK: ehb
0x00 0x00 0x57 0x7c # CHECK: ei 0x00 0x00 0x57 0x7c # CHECK: ei
0x00 0x0a 0x57 0x7c # CHECK: ei $10 0x00 0x0a 0x57 0x7c # CHECK: ei $10
0x00 0x00 0xf3 0x7c # CHECK: eret 0x00 0x00 0xf3 0x7c # CHECK: eret
0x00 0x01 0xf3 0x7c # CHECK: eretnc 0x00 0x01 0xf3 0x7c # CHECK: eretnc
0x80 0x05 0x01 0x00 # CHECK: jialc $5, 256 0x80 0x05 0x01 0x00 # CHECK: jialc $5, 256
0xa0 0x05 0x01 0x00 # CHECK: jic $5, 256 0xa0 0x05 0x01 0x00 # CHECK: jic $5, 256
0x60 0x44 0x30 0x08 # CHECK: ll $2, 8($4)
0x20 0x44 0x50 0x08 # CHECK: lwm32 $16, $17, 8($4)
0x21 0x3b 0x59 0x84 # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, -1660($27)
0x01 0x26 0x38 0xc0 # CHECK: rotr $9, $6, 7
0x00 0xc7 0x48 0xd0 # CHECK: rotrv $9, $6, $7
0x60 0x44 0xb0 0x08 # CHECK: sc $2, 8($4)
0x20 0x44 0xd0 0x08 # CHECK: swm32 $16, $17, 8($4)
0x00 0x00 0x8b 0x7c # CHECK: syscall
0x01 0x8c 0x8b 0x7c # CHECK: syscall 396
0x78 0x48 0x00 0x43 # CHECK: lwpc $2, 268 0x78 0x48 0x00 0x43 # CHECK: lwpc $2, 268
0x00 0x43 0x26 0x0f # CHECK: lsa $2, $3, $4, 4 0x00 0x43 0x26 0x0f # CHECK: lsa $2, $3, $4, 4
0x00 0xa4 0x19 0x58 # CHECK: mod $3, $4, $5 0x00 0xa4 0x19 0x58 # CHECK: mod $3, $4, $5
0x00 0xa4 0x19 0xd8 # CHECK: modu $3, $4, $5 0x00 0xa4 0x19 0xd8 # CHECK: modu $3, $4, $5
0x00 0xa4 0x18 0x18 # CHECK: mul $3, $4, $5 0x00 0xa4 0x18 0x18 # CHECK: mul $3, $4, $5
0x00 0xa4 0x18 0x58 # CHECK: muh $3, $4, $5 0x00 0xa4 0x18 0x58 # CHECK: muh $3, $4, $5
0x00 0xa4 0x18 0x98 # CHECK: mulu $3, $4, $5 0x00 0xa4 0x18 0x98 # CHECK: mulu $3, $4, $5
0x00 0xa4 0x18 0xd8 # CHECK: muhu $3, $4, $5 0x00 0xa4 0x18 0xd8 # CHECK: muhu $3, $4, $5
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test/MC/Disassembler/Mips/micromips64r6/valid.txt

Show All 15 Lines
0x48 0x66 # CHECK: lw $3, 24($sp) 0x48 0x66 # CHECK: lw $3, 24($sp)
0x6a 0x12 # CHECK: lw16 $4, 8($17) 0x6a 0x12 # CHECK: lw16 $4, 8($17)
0x29 0x82 # CHECK: lhu16 $3, 4($16) 0x29 0x82 # CHECK: lhu16 $3, 4($16)
0x09 0x94 # CHECK: lbu16 $3, 4($17) 0x09 0x94 # CHECK: lbu16 $3, 4($17)
0x09 0x9f # CHECK: lbu16 $3, -1($17) 0x09 0x9f # CHECK: lbu16 $3, -1($17)
0x45 0x2b # CHECK: jalr $9 0x45 0x2b # CHECK: jalr $9
0x45 0x23 # CHECK: jrc16 $9 0x45 0x23 # CHECK: jrc16 $9
0x44 0xb3 # CHECK: jrcaddiusp 20 0x44 0xb3 # CHECK: jrcaddiusp 20
0x84 0x34 # CHECK: movep $5, $6, $2, $3
0x60 0x44 0x30 0x08 # CHECK: ll $2, 8($4)
0x20 0x44 0x50 0x08 # CHECK: lwm32 $16, $17, 8($4)
0x21 0x3b 0x59 0x84 # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, -1660($27)
0x01 0x26 0x38 0xc0 # CHECK: rotr $9, $6, 7
0x00 0xc7 0x48 0xd0 # CHECK: rotrv $9, $6, $7
0x60 0x44 0xb0 0x08 # CHECK: sc $2, 8($4)
0x20 0x44 0xd0 0x08 # CHECK: swm32 $16, $17, 8($4)
0x00 0x00 0x8b 0x7c # CHECK: syscall
0x01 0x8c 0x8b 0x7c # CHECK: syscall 396
0xf0 0x64 0x00 0x05 # CHECK: daui $3, $4, 5 0xf0 0x64 0x00 0x05 # CHECK: daui $3, $4, 5
0x42 0x23 0x00 0x04 # CHECK: dahi $3, 4 0x42 0x23 0x00 0x04 # CHECK: dahi $3, 4
0x42 0x03 0x00 0x04 # CHECK: dati $3, 4 0x42 0x03 0x00 0x04 # CHECK: dati $3, 4
0x59 0x26 0x30 0xec # CHECK: dext $9, $6, 3, 7 0x59 0x26 0x30 0xec # CHECK: dext $9, $6, 3, 7
0x59 0x26 0x30 0xe4 # CHECK: dextm $9, $6, 3, 39 0x59 0x26 0x30 0xe4 # CHECK: dextm $9, $6, 3, 39
0x59 0x26 0x30 0xd4 # CHECK: dextu $9, $6, 35, 7 0x59 0x26 0x30 0xd4 # CHECK: dextu $9, $6, 35, 7
0x58 0x43 0x25 0x1c # CHECK: dalign $4, $2, $3, 5 0x58 0x43 0x25 0x1c # CHECK: dalign $4, $2, $3, 5
0x58 0xa4 0x19 0x18 # CHECK: ddiv $3, $4, $5 0x58 0xa4 0x19 0x18 # CHECK: ddiv $3, $4, $5
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test/MC/Mips/micromips/invalid-wrong-error.s

# Instructions that are correctly rejected but emit a wrong or misleading error. # Instructions that are correctly rejected but emit a wrong or misleading error.
# RUN: not llvm-mc %s -triple=mips -show-encoding -mattr=micromips 2>%t1 # RUN: not llvm-mc %s -triple=mips -show-encoding -mattr=micromips 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
# The 20-bit immediate supported by the standard encodings cause us to emit # The 20-bit immediate supported by the standard encodings cause us to emit
# the diagnostic for the 20-bit form. This isn't exactly wrong but it is # the diagnostic for the 20-bit form. This isn't exactly wrong but it is
# misleading. Ideally, we'd emit every way to achieve a valid match instead # misleading. Ideally, we'd emit every way to achieve a valid match instead
# of picking only one. # of picking only one.
sdbbp -1 # CHECK: :[[@LINE]]:9: error: expected 20-bit unsigned immediate sdbbp -1 # CHECK: :[[@LINE]]:9: error: expected 20-bit unsigned immediate
sdbbp 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled sdbbp 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
syscall -1 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate syscall -1 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
syscall $4 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
syscall 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled syscall 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled

test/MC/Mips/micromips/invalid.s

Show All 33 Lines# RUN: FileCheck %s < %t1
jraddiusp 125 # CHECK: :[[@LINE]]:13: error: expected both 7-bit unsigned immediate and multiple of 4 jraddiusp 125 # CHECK: :[[@LINE]]:13: error: expected both 7-bit unsigned immediate and multiple of 4
jraddiusp 128 # CHECK: :[[@LINE]]:13: error: expected both 7-bit unsigned immediate and multiple of 4 jraddiusp 128 # CHECK: :[[@LINE]]:13: error: expected both 7-bit unsigned immediate and multiple of 4
li16 $4, -2 # CHECK: :[[@LINE]]:12: error: expected immediate in range -1 .. 126 li16 $4, -2 # CHECK: :[[@LINE]]:12: error: expected immediate in range -1 .. 126
li16 $4, 127 # CHECK: :[[@LINE]]:12: error: expected immediate in range -1 .. 126 li16 $4, 127 # CHECK: :[[@LINE]]:12: error: expected immediate in range -1 .. 126
pref -1, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate pref -1, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
pref 32, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate pref 32, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
prefe 0, -513($7) # CHECK: :[[@LINE]]:12: error: expected memory with 9-bit signed offset prefe 0, -513($7) # CHECK: :[[@LINE]]:12: error: expected memory with 9-bit signed offset
prefe 0, 512($7) # CHECK: :[[@LINE]]:12: error: expected memory with 9-bit signed offset prefe 0, 512($7) # CHECK: :[[@LINE]]:12: error: expected memory with 9-bit signed offset
rotr $2, -1 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
rotr $2, 32 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
rotr $2, $3, -1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
rotrv $9, $6, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
sdbbp16 -1 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate sdbbp16 -1 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate
sdbbp16 16 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate sdbbp16 16 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate
sll $2, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate sll $2, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
sll $2, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate sll $2, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
sra $2, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate sra $2, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
sra $2, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate sra $2, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
srl $2, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate srl $2, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
srl $2, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate srl $2, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
Show All 31 Lines

test/MC/Mips/micromips32r6/invalid-wrong-error.s

Show All 19 Lines# RUN: FileCheck %s < %t1
tlt $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate tlt $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
tlt $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled tlt $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
tltu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate tltu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate
tltu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate tltu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate
tltu $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled tltu $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
tne $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate tne $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
tne $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate tne $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
tne $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled tne $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
syscall -1 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
syscall $4 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
syscall 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled

test/MC/Mips/micromips32r6/invalid.s

Show First 20 Lines • Show All 166 Lines • ▼ Show 20 Lines# RUN: FileCheck %s < %t1
sce $4, 8($33) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset sce $4, 8($33) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
sce $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset sce $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
sce $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset sce $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
she $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction she $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
she $4, 8($33) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset she $4, 8($33) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
she $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset she $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
she $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset she $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
swe $5, -513($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset swe $5, -513($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
lwm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
lwm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
lwm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $24, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
movep $5, $6, $2, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
movep $5, $6, $5, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
movep $5, $21, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
movep $8, $6, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
rotr $2, -1 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
rotr $2, 32 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
rotr $2, $3, -1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
rotrv $9, $6, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
swm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand

test/MC/Mips/micromips32r6/valid.s

Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0x80,0x05,0x01,0x00] jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0x80,0x05,0x01,0x00]
jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xa0,0x05,0x01,0x00] jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xa0,0x05,0x01,0x00]
jrc16 $9 # CHECK: jrc16 $9 # encoding: [0x45,0x23] jrc16 $9 # CHECK: jrc16 $9 # encoding: [0x45,0x23]
jrcaddiusp 20 # CHECK: jrcaddiusp 20 # encoding: [0x44,0xb3] jrcaddiusp 20 # CHECK: jrcaddiusp 20 # encoding: [0x44,0xb3]
lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x43,0x24,0x0f] lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x43,0x24,0x0f]
lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0x78,0x48,0x00,0x43] lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0x78,0x48,0x00,0x43]
lwm $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22] lwm $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
lwm16 $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22] lwm16 $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
ll $2, 8($4) # CHECK: ll $2, 8($4) # encoding: [0x60,0x44,0x30,0x08]
lwm32 $16, $17, 8($4) # CHECK: lwm32 $16, $17, 8($4) # encoding: [0x20,0x44,0x50,0x08]
lwm32 $16, $17, 8($sp) # CHECK: lwm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0x50,0x08]
lwm32 $16, $17, $ra, 8($4) # CHECK: lwm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0x50,0x08]
lwm32 $16, $17, $ra, 64($sp) # CHECK: lwm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0x50,0x40]
lwm32 $16, $17, $18, $19, 8($4) # CHECK: lwm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0x50,0x08]
lwm32 $16, $17, $18, $19, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $ra, 8($4) # encoding: [0x22,0x84,0x50,0x08]
lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # encoding: [0x21,0x24,0x50,0x08]
lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x84,0x34]
rotr $2, 7 # CHECK: rotr $2, $2, 7 # encoding: [0x00,0x42,0x38,0xc0]
rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0]
rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
sc $2, 8($4) # CHECK: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08]
swm32 $16, $17, 8($4) # CHECK: swm32 $16, $17, 8($4) # encoding: [0x20,0x44,0xd0,0x08]
swm32 $16, $17, 8($sp) # CHECK: swm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0xd0,0x08]
swm32 $16, $17, $ra, 8($4) # CHECK: swm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0xd0,0x08]
swm32 $16, $17, $ra, 64($sp) # CHECK: swm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0xd0,0x40]
swm32 $16, $17, $18, $19, 8($4) # CHECK: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0xd0,0x08]
syscall # CHECK: syscall # encoding: [0x00,0x00,0x8b,0x7c]
syscall 396 # CHECK: syscall 396 # encoding: [0x01,0x8c,0x8b,0x7c]
mod $3, $4, $5 # CHECK: mod $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x58] mod $3, $4, $5 # CHECK: mod $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x58]
modu $3, $4, $5 # CHECK: modu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd8] modu $3, $4, $5 # CHECK: modu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd8]
mul $3, $4, $5 # CHECK mul $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x18] mul $3, $4, $5 # CHECK mul $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x18]
muh $3, $4, $5 # CHECK muh $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x58] muh $3, $4, $5 # CHECK muh $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x58]
mulu $3, $4, $5 # CHECK mulu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x98] mulu $3, $4, $5 # CHECK mulu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x98]
muhu $3, $4, $5 # CHECK muhu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xd8] muhu $3, $4, $5 # CHECK muhu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xd8]
nop # CHECK: nop # encoding: [0x00,0x00,0x00,0x00] nop # CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
nor $3, $4, $5 # CHECK: nor $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0xd0] nor $3, $4, $5 # CHECK: nor $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0xd0]
▲ Show 20 Lines • Show All 232 Lines • Show Last 20 Lines

test/MC/Mips/micromips64r6/invalid-wrong-error.s

Show All 21 Lines# RUN: FileCheck %s < %t1
tltu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate tltu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate
tltu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate tltu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate
tltu $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled tltu $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
tne $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate tne $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
tne $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate tne $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
tne $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled tne $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
dins $2, $3, -1, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate dins $2, $3, -1, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
dins $2, $3, 32, 1 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled dins $2, $3, 32, 1 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
syscall -1 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
syscall $4 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
syscall 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled

test/MC/Mips/micromips64r6/invalid.s

Show First 20 Lines • Show All 198 Lines • ▼ Show 20 Lines# RUN: FileCheck %s < %t1
she $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction she $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
she $4, 8($33) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset she $4, 8($33) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
she $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset she $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
she $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset she $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
swe $33, 8($4) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction swe $33, 8($4) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
swe $5, 8($34) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset swe $5, 8($34) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
swe $5, 512($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset swe $5, 512($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
swe $5, -513($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset swe $5, -513($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
lwm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
lwm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
lwm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $24, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
movep $5, $6, $2, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
movep $5, $6, $5, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
movep $5, $21, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
movep $8, $6, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
rotr $2, -1 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
rotr $2, 32 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
rotr $2, $3, -1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
rotrv $9, $6, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
swm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand

test/MC/Mips/micromips64r6/valid.s

Show All 22 Linesa:
dalign $4, $2, $3, 5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x58,0x43,0x25,0x1c] dalign $4, $2, $3, 5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x58,0x43,0x25,0x1c]
ldpc $2, 16 # CHECK: ldpc $2, 16 # encoding: [0x78,0x58,0x00,0x02] ldpc $2, 16 # CHECK: ldpc $2, 16 # encoding: [0x78,0x58,0x00,0x02]
lw $3, 32($gp) # CHECK: lw $3, 32($gp) # encoding: [0x65,0x88] lw $3, 32($gp) # CHECK: lw $3, 32($gp) # encoding: [0x65,0x88]
lw $3, 24($sp) # CHECK: lw $3, 24($sp) # encoding: [0x48,0x66] lw $3, 24($sp) # CHECK: lw $3, 24($sp) # encoding: [0x48,0x66]
lw16 $4, 8($17) # CHECK: lw16 $4, 8($17) # encoding: [0x6a,0x12] lw16 $4, 8($17) # CHECK: lw16 $4, 8($17) # encoding: [0x6a,0x12]
lhu16 $3, 4($16) # CHECK: lhu16 $3, 4($16) # encoding: [0x29,0x82] lhu16 $3, 4($16) # CHECK: lhu16 $3, 4($16) # encoding: [0x29,0x82]
lbu16 $3, 4($17) # CHECK: lbu16 $3, 4($17) # encoding: [0x09,0x94] lbu16 $3, 4($17) # CHECK: lbu16 $3, 4($17) # encoding: [0x09,0x94]
lbu16 $3, -1($17) # CHECK: lbu16 $3, -1($17) # encoding: [0x09,0x9f] lbu16 $3, -1($17) # CHECK: lbu16 $3, -1($17) # encoding: [0x09,0x9f]
movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x84,0x34]
ll $2, 8($4) # CHECK: ll $2, 8($4) # encoding: [0x60,0x44,0x30,0x08]
lwm32 $16, $17, 8($4) # CHECK: lwm32 $16, $17, 8($4) # encoding: [0x20,0x44,0x50,0x08]
lwm32 $16, $17, 8($sp) # CHECK: lwm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0x50,0x08]
lwm32 $16, $17, $ra, 8($4) # CHECK: lwm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0x50,0x08]
lwm32 $16, $17, $ra, 64($sp) # CHECK: lwm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0x50,0x40]
lwm32 $16, $17, $18, $19, 8($4) # CHECK: lwm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0x50,0x08]
lwm32 $16, $17, $18, $19, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $ra, 8($4) # encoding: [0x22,0x84,0x50,0x08]
lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # encoding: [0x21,0x24,0x50,0x08]
lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
rotr $2, 7 # CHECK: rotr $2, $2, 7 # encoding: [0x00,0x42,0x38,0xc0]
rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0]
rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
sc $2, 8($4) # CHECK: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08]
swm32 $16, $17, 8($4) # CHECK: swm32 $16, $17, 8($4) # encoding: [0x20,0x44,0xd0,0x08]
swm32 $16, $17, 8($sp) # CHECK: swm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0xd0,0x08]
swm32 $16, $17, $ra, 8($4) # CHECK: swm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0xd0,0x08]
swm32 $16, $17, $ra, 64($sp) # CHECK: swm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0xd0,0x40]
swm32 $16, $17, $18, $19, 8($4) # CHECK: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0xd0,0x08]
syscall # CHECK: syscall # encoding: [0x00,0x00,0x8b,0x7c]
syscall 396 # CHECK: syscall 396 # encoding: [0x01,0x8c,0x8b,0x7c]
ddiv $3, $4, $5 # CHECK: ddiv $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x18] ddiv $3, $4, $5 # CHECK: ddiv $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x18]
dmod $3, $4, $5 # CHECK: dmod $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x58] dmod $3, $4, $5 # CHECK: dmod $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x58]
ddivu $3, $4, $5 # CHECK: ddivu $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x98] ddivu $3, $4, $5 # CHECK: ddivu $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x98]
dmodu $3, $4, $5 # CHECK: dmodu $3, $4, $5 # encoding: [0x58,0xa4,0x19,0xd8] dmodu $3, $4, $5 # CHECK: dmodu $3, $4, $5 # encoding: [0x58,0xa4,0x19,0xd8]
add.s $f3, $f4, $f5 # CHECK: add.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x30] add.s $f3, $f4, $f5 # CHECK: add.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x30]
add.d $f2, $f4, $f6 # CHECK: add.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x30] add.d $f2, $f4, $f6 # CHECK: add.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x30]
sub.s $f3, $f4, $f5 # CHECK: sub.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x70] sub.s $f3, $f4, $f5 # CHECK: sub.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x70]
sub.d $f2, $f4, $f6 # CHECK: sub.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x70] sub.d $f2, $f4, $f6 # CHECK: sub.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x70]
▲ Show 20 Lines • Show All 195 Lines • Show Last 20 Lines