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Differential D18687

[mips][microMIPS] Implement DVP, EVP and JALRC.HB instructions
ClosedPublic

Authored by zbuljan on Apr 1 2016, 1:46 AM.

Details

Reviewers
dsanders
sdardis
vkalintiris
zoran.jovanovic
hvarga
Commits
rL267114: [mips][microMIPS] Implement DVP, EVP and JALRC.HB instructions
Summary

The patch implements microMIPSr6 DVP, EVP and JALRC.HB instructions.

Diff Detail

Repository
rL LLVM

Event Timeline

zbuljan updated this revision to Diff 52337.Apr 1 2016, 1:46 AM
zbuljan retitled this revision from to [mips][microMIPS] Implement DVP, EVP and JALRC.HB instructions.
zbuljan updated this object.
zbuljan added reviewers: dsanders, hvarga, zoran.jovanovic.
zbuljan added subscribers: petarj, llvm-commits.
Herald added a reviewer: vkalintiris. · View Herald TranscriptApr 1 2016, 1:46 AM
Herald added subscribers: sdardis, dsanders. · View Herald Transcript
sdardis accepted this revision.Apr 13 2016, 8:19 AM
sdardis added a reviewer: sdardis.

LGTM with some nits (inlined).

The isCTI is only required for MIPSR6 instructions which cannot be placed in a forbidden slot. Since microMIPSR6 doesn't have forbidden slots and cannot be mixed inside MIPSR6 code without going through an ISA change it isn't required.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp
3653 ↗(On Diff #52337)

Add a note here that it also applies to microMIPSR6.

lib/Target/Mips/MicroMips32r6InstrInfo.td
1020 ↗(On Diff #52337)

The 'isCTI' bit isn't required. The only code that cares about the 'isCTI' bit is the SafeInForbiddenSlot predicate which is only used for MIPSR6, not microMIPSR6.

test/MC/Mips/micromips32r6/invalid.s
118 ↗(On Diff #52337)

Add evp and dvp with immediate operands here to test that they are rejected.

test/MC/Mips/micromips64r6/invalid.s
148 ↗(On Diff #52337)

Here as well.

This revision is now accepted and ready to land.Apr 13 2016, 8:19 AM
Closed by commit rL267114: [mips][microMIPS] Implement DVP, EVP and JALRC.HB instructions (authored by zbuljan). · Explain WhyApr 21 2016, 11:50 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
AsmParser/
3 lines
26 lines
32 lines
test/
MC/
Disassembler/
Mips/
micromips32r6/
6 lines
micromips64r6/
6 lines
Mips/
micromips32r6/
6 lines
6 lines
micromips64r6/
6 lines
6 lines

Diff 54614

llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Show First 20 Lines • Show All 3,663 Lines • ▼ Show 20 Linesvoid MipsAsmParser::createCpRestoreMemOp(bool IsLoad, int StackOffset,
emitRRI(IsLoad ? Mips::LW : Mips::SW, Mips::GP, Mips::SP, StackOffset, IDLoc, emitRRI(IsLoad ? Mips::LW : Mips::SW, Mips::GP, Mips::SP, StackOffset, IDLoc,
Out, STI); Out, STI);
} }
unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) { unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
// As described by the Mips32r2 spec, the registers Rd and Rs for // As described by the Mips32r2 spec, the registers Rd and Rs for
// jalr.hb must be different. // jalr.hb must be different.
// It also applies for registers Rt and Rs of microMIPSr6 jalrc.hb instruction
unsigned Opcode = Inst.getOpcode(); unsigned Opcode = Inst.getOpcode();
if (Opcode == Mips::JALR_HB && if ((Opcode == Mips::JALR_HB || Opcode == Mips::JALRC_HB_MMR6) &&
(Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg())) (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()))
return Match_RequiresDifferentSrcAndDst; return Match_RequiresDifferentSrcAndDst;
return Match_Success; return Match_Success;
} }
static SMLoc RefineErrorLoc(const SMLoc Loc, const OperandVector &Operands, static SMLoc RefineErrorLoc(const SMLoc Loc, const OperandVector &Operands,
uint64_t ErrorInfo) { uint64_t ErrorInfo) {
▲ Show 20 Lines • Show All 2,728 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td

Show First 20 Lines • Show All 488 Lines • ▼ Show 20 Linesclass CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<string instr_asm, bits<6> funct>
bits<32> Inst; bits<32> Inst;
let Inst{31-26} = funct; let Inst{31-26} = funct;
let Inst{25-21} = rt; let Inst{25-21} = rt;
let Inst{20-16} = rt; let Inst{20-16} = rt;
let Inst{15-0} = offset; let Inst{15-0} = offset;
} }
class POOL32A_JALRC_FM_MMR6<string instr_asm, bits<10> funct>
: MipsR6Inst, MMR6Arch<instr_asm> {
bits<5> rt;
bits<5> rs;
bits<32> Inst;
let Inst{31-26} = 0;
let Inst{25-21} = rt;
let Inst{20-16} = rs;
let Inst{15-6} = funct;
let Inst{5-0} = 0b111100;
}
class POOL32A_ERET_FM_MMR6<string instr_asm, bits<10> funct> class POOL32A_ERET_FM_MMR6<string instr_asm, bits<10> funct>
: MMR6Arch<instr_asm> { : MMR6Arch<instr_asm> {
bits<32> Inst; bits<32> Inst;
let Inst{31-26} = 0x00; let Inst{31-26} = 0x00;
let Inst{25-16} = 0x00; let Inst{25-16} = 0x00;
let Inst{15-6} = funct; let Inst{15-6} = funct;
let Inst{5-0} = 0x3c; let Inst{5-0} = 0x3c;
▲ Show 20 Lines • Show All 474 Lines • ▼ Show 20 Linesclass CMP_BRANCH_2R_OFF16_FM_MMR6<string opstr, bits<6> funct>
bits<32> Inst; bits<32> Inst;
let Inst{31-26} = funct; let Inst{31-26} = funct;
let Inst{25-21} = rt; let Inst{25-21} = rt;
let Inst{20-16} = rs; let Inst{20-16} = rs;
let Inst{15-0} = offset; let Inst{15-0} = offset;
} }
class POOL32A_DVPEVP_FM_MMR6<string instr_asm, bits<10> funct>
: MMR6Arch<instr_asm>, MipsR6Inst {
bits<5> rs;
bits<32> Inst;
let Inst{31-26} = 0b000000;
let Inst{25-21} = 0b00000;
let Inst{20-16} = rs;
let Inst{15-6} = funct;
let Inst{5-0} = 0b111100;
}

llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td

Show First 20 Lines • Show All 158 Lines • ▼ Show 20 Lines
class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>; class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>;
class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>; class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>;
class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>; class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b101>; class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b101>;
class LLE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b110>; class LLE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b110>;
class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>; class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>;
class LW_MMR6_ENC : LOAD_WORD_FM_MMR6; class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6; class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
class JALRC_HB_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc.hb", 0b0001111100>;
class RECIP_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.s", 0, 0b01001000>; class RECIP_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.s", 0, 0b01001000>;
class RECIP_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.d", 1, 0b01001000>; class RECIP_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.d", 1, 0b01001000>;
class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>; class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>;
class RINT_D_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>; class RINT_D_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>;
class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0, class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0,
0b11001100>; 0b11001100>;
class ROUND_L_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.d", 1, class ROUND_L_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.d", 1,
0b11001100>; 0b11001100>;
Show All 20 Lines
class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>; class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
class LI16_MMR6_ENC : LI_FM_MM16; class LI16_MMR6_ENC : LI_FM_MM16;
class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>; class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>; class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6; class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>; class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
class TLBINV_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinv", 0x10d>; class TLBINV_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinv", 0x10d>;
class TLBINVF_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinvf", 0x14d>; class TLBINVF_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinvf", 0x14d>;
class DVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"dvp", 0b0001100101>;
class EVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"evp", 0b0011100101>;
class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd, class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
RegisterOperand GPROpnd> RegisterOperand GPROpnd>
: BRANCH_DESC_BASE { : BRANCH_DESC_BASE {
dag InOperandList = (ins GPROpnd:$rt, opnd:$offset); dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
dag OutOperandList = (outs); dag OutOperandList = (outs);
string AsmString = !strconcat(instr_asm, "\t$rt, $offset"); string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
list<Register> Defs = [AT]; list<Register> Defs = [AT];
▲ Show 20 Lines • Show All 917 Lines • ▼ Show 20 Lines
class SWSP_MMR6_DESC class SWSP_MMR6_DESC
: MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset), : MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset),
!strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>, !strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>,
MMR6Arch<"sw">, MicroMipsR6Inst16 { MMR6Arch<"sw">, MicroMipsR6Inst16 {
let DecoderMethod = "DecodeMemMMSPImm5Lsl2"; let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
let mayStore = 1; let mayStore = 1;
} }
class JALRC_HB_MMR6_DESC {
dag OutOperandList = (outs GPR32Opnd:$rt);
dag InOperandList = (ins GPR32Opnd:$rs);
string AsmString = !strconcat("jalrc.hb", "\t$rt, $rs");
list<dag> Pattern = [];
InstrItinClass Itinerary = NoItinerary;
Format Form = FrmJ;
bit isIndirectBranch = 1;
bit hasDelaySlot = 0;
}
class TLBINV_MMR6_DESC_BASE<string opstr> { class TLBINV_MMR6_DESC_BASE<string opstr> {
dag OutOperandList = (outs); dag OutOperandList = (outs);
dag InOperandList = (ins); dag InOperandList = (ins);
string AsmString = opstr; string AsmString = opstr;
list<dag> Pattern = []; list<dag> Pattern = [];
} }
class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv">; class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv">;
class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf">; class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf">;
class DVPEVP_MMR6_DESC_BASE<string opstr> {
dag OutOperandList = (outs);
dag InOperandList = (ins GPR32Opnd:$rs);
string AsmString = !strconcat(opstr, "\t$rs");
list<dag> Pattern = [];
}
class DVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"dvp">;
class EVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"evp">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Instruction Definitions // Instruction Definitions
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let DecoderNamespace = "MicroMipsR6" in { let DecoderNamespace = "MicroMipsR6" in {
def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6; def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
▲ Show 20 Lines • Show All 258 Lines • ▼ Show 20 Lines
def MOVE16_MMR6 : StdMMR6Rel, MOVE16_MMR6_DESC, MOVE16_MMR6_ENC, def MOVE16_MMR6 : StdMMR6Rel, MOVE16_MMR6_DESC, MOVE16_MMR6_ENC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def SDBBP16_MMR6 : StdMMR6Rel, SDBBP16_MMR6_DESC, SDBBP16_MMR6_ENC, def SDBBP16_MMR6 : StdMMR6Rel, SDBBP16_MMR6_DESC, SDBBP16_MMR6_ENC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC, def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC, def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def JALRC_HB_MMR6 : R6MMR6Rel, JALRC_HB_MMR6_ENC, JALRC_HB_MMR6_DESC,
ISA_MICROMIPS32R6;
def RECIP_S_MMR6 : StdMMR6Rel, RECIP_S_MMR6_ENC, RECIP_S_MMR6_DESC, def RECIP_S_MMR6 : StdMMR6Rel, RECIP_S_MMR6_ENC, RECIP_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def RECIP_D_MMR6 : StdMMR6Rel, RECIP_D_MMR6_ENC, RECIP_D_MMR6_DESC, ISA_MICROMIPS32R6; def RECIP_D_MMR6 : StdMMR6Rel, RECIP_D_MMR6_ENC, RECIP_D_MMR6_DESC, ISA_MICROMIPS32R6;
def RINT_S_MMR6 : StdMMR6Rel, RINT_S_MMR6_ENC, RINT_S_MMR6_DESC, def RINT_S_MMR6 : StdMMR6Rel, RINT_S_MMR6_ENC, RINT_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC, ISA_MICROMIPS32R6; def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC, ISA_MICROMIPS32R6;
def ROUND_L_S_MMR6 : StdMMR6Rel, ROUND_L_S_MMR6_ENC, ROUND_L_S_MMR6_DESC, def ROUND_L_S_MMR6 : StdMMR6Rel, ROUND_L_S_MMR6_ENC, ROUND_L_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
Show All 16 Lines
def CLASS_S_MMR6 : StdMMR6Rel, CLASS_S_MMR6_ENC, CLASS_S_MMR6_DESC, def CLASS_S_MMR6 : StdMMR6Rel, CLASS_S_MMR6_ENC, CLASS_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def CLASS_D_MMR6 : StdMMR6Rel, CLASS_D_MMR6_ENC, CLASS_D_MMR6_DESC, def CLASS_D_MMR6 : StdMMR6Rel, CLASS_D_MMR6_ENC, CLASS_D_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def TLBINV_MMR6 : StdMMR6Rel, TLBINV_MMR6_ENC, TLBINV_MMR6_DESC, def TLBINV_MMR6 : StdMMR6Rel, TLBINV_MMR6_ENC, TLBINV_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def TLBINVF_MMR6 : StdMMR6Rel, TLBINVF_MMR6_ENC, TLBINVF_MMR6_DESC, def TLBINVF_MMR6 : StdMMR6Rel, TLBINVF_MMR6_ENC, TLBINVF_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def DVP_MMR6 : R6MMR6Rel, DVP_MMR6_ENC, DVP_MMR6_DESC, ISA_MICROMIPS32R6;
def EVP_MMR6 : R6MMR6Rel, EVP_MMR6_ENC, EVP_MMR6_DESC, ISA_MICROMIPS32R6;
} }
def BGEC_MMR6 : R6MMR6Rel, BGEC_MMR6_ENC, BGEC_MMR6_DESC, ISA_MICROMIPS32R6; def BGEC_MMR6 : R6MMR6Rel, BGEC_MMR6_ENC, BGEC_MMR6_DESC, ISA_MICROMIPS32R6;
def BGEUC_MMR6 : R6MMR6Rel, BGEUC_MMR6_ENC, BGEUC_MMR6_DESC, ISA_MICROMIPS32R6; def BGEUC_MMR6 : R6MMR6Rel, BGEUC_MMR6_ENC, BGEUC_MMR6_DESC, ISA_MICROMIPS32R6;
def BLTC_MMR6 : R6MMR6Rel, BLTC_MMR6_ENC, BLTC_MMR6_DESC, ISA_MICROMIPS32R6; def BLTC_MMR6 : R6MMR6Rel, BLTC_MMR6_ENC, BLTC_MMR6_DESC, ISA_MICROMIPS32R6;
def BLTUC_MMR6 : R6MMR6Rel, BLTUC_MMR6_ENC, BLTUC_MMR6_DESC, ISA_MICROMIPS32R6; def BLTUC_MMR6 : R6MMR6Rel, BLTUC_MMR6_ENC, BLTUC_MMR6_DESC, ISA_MICROMIPS32R6;
def BEQC_MMR6 : R6MMR6Rel, BEQC_MMR6_ENC, BEQC_MMR6_DESC, ISA_MICROMIPS32R6; def BEQC_MMR6 : R6MMR6Rel, BEQC_MMR6_ENC, BEQC_MMR6_DESC, ISA_MICROMIPS32R6;
def BNEC_MMR6 : R6MMR6Rel, BNEC_MMR6_ENC, BNEC_MMR6_DESC, ISA_MICROMIPS32R6; def BNEC_MMR6 : R6MMR6Rel, BNEC_MMR6_ENC, BNEC_MMR6_DESC, ISA_MICROMIPS32R6;
Show All 31 Linesdef : MipsInstAlias<"mthc0 $rt, $rs",
(MTHC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>, (MTHC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def : MipsInstAlias<"mfc0 $rt, $rs", def : MipsInstAlias<"mfc0 $rt, $rs",
(MFC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>, (MFC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def : MipsInstAlias<"mfhc0 $rt, $rs", def : MipsInstAlias<"mfhc0 $rt, $rs",
(MFHC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>, (MFHC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def : MipsInstAlias<"jalrc.hb $rs", (JALRC_HB_MMR6 RA, GPR32Opnd:$rs), 1>,
ISA_MICROMIPS32R6;
def : MipsInstAlias<"dvp", (DVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
def : MipsInstAlias<"evp", (EVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// MicroMips arbitrary patterns that map to one or more instructions // MicroMips arbitrary patterns that map to one or more instructions
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr), def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
(SW16_MMR6 GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS32R6; (SW16_MMR6 GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS32R6;

llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt

Show First 20 Lines • Show All 296 Lines • ▼ Show 20 Lines
0x02 0x95 0x00 0xf4 # CHECK: mfhc0 $20, $21, 0 0x02 0x95 0x00 0xf4 # CHECK: mfhc0 $20, $21, 0
0x00 0x22 0x08 0xf4 # CHECK: mfhc0 $1, $2, 1 0x00 0x22 0x08 0xf4 # CHECK: mfhc0 $1, $2, 1
0x54 0x06 0x30 0x3b # CHECK: mfhc1 $zero, $f6 0x54 0x06 0x30 0x3b # CHECK: mfhc1 $zero, $f6
0x02 0xf0 0x8d 0x3c # CHECK: mfhc2 $23, $16 0x02 0xf0 0x8d 0x3c # CHECK: mfhc2 $23, $16
0x00 0x00 0x03 0x7c # CHECK: tlbp 0x00 0x00 0x03 0x7c # CHECK: tlbp
0x00 0x00 0x13 0x7c # CHECK: tlbr 0x00 0x00 0x13 0x7c # CHECK: tlbr
0x00 0x00 0x23 0x7c # CHECK: tlbwi 0x00 0x00 0x23 0x7c # CHECK: tlbwi
0x00 0x00 0x33 0x7c # CHECK: tlbwr 0x00 0x00 0x33 0x7c # CHECK: tlbwr
0x00 0x00 0x19 0x7c # CHECK: dvp
0x00 0x04 0x19 0x7c # CHECK: dvp $4
0x00 0x00 0x39 0x7c # CHECK: evp
0x00 0x04 0x39 0x7c # CHECK: evp $4
0x03 0xe4 0x1f 0x3c # CHECK: jalrc.hb $4
0x00 0x85 0x1f 0x3c # CHECK: jalrc.hb $4, $5

llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt

Show First 20 Lines • Show All 224 Lines • ▼ Show 20 Lines
0x5e 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943 0x5e 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943
0x5f 0x02 0x46 0x9f # CHECK: daddiu $24, $2, 18079 0x5f 0x02 0x46 0x9f # CHECK: daddiu $24, $2, 18079
0x5c 0x63 0xff 0xfb # CHECK: daddiu $3, $3, -5 0x5c 0x63 0xff 0xfb # CHECK: daddiu $3, $3, -5
0x5c 0x64 0xff 0xfb # CHECK: daddiu $3, $4, -5 0x5c 0x64 0xff 0xfb # CHECK: daddiu $3, $4, -5
0x00 0x00 0x03 0x7c # CHECK: tlbp 0x00 0x00 0x03 0x7c # CHECK: tlbp
0x00 0x00 0x13 0x7c # CHECK: tlbr 0x00 0x00 0x13 0x7c # CHECK: tlbr
0x00 0x00 0x23 0x7c # CHECK: tlbwi 0x00 0x00 0x23 0x7c # CHECK: tlbwi
0x00 0x00 0x33 0x7c # CHECK: tlbwr 0x00 0x00 0x33 0x7c # CHECK: tlbwr
0x00 0x00 0x19 0x7c # CHECK: dvp
0x00 0x04 0x19 0x7c # CHECK: dvp $4
0x00 0x00 0x39 0x7c # CHECK: evp
0x00 0x04 0x39 0x7c # CHECK: evp $4
0x03 0xe4 0x1f 0x3c # CHECK: jalrc.hb $4
0x00 0x85 0x1f 0x3c # CHECK: jalrc.hb $4, $5

llvm/trunk/test/MC/Mips/micromips32r6/invalid.s

Show First 20 Lines • Show All 143 Lines • ▼ Show 20 Lines# RUN: FileCheck %s < %t1
tlbr 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction tlbr 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbr $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction tlbr $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbwi $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwi $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
tlbwi 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwi 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
tlbwi $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwi $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
tlbwr $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwr $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
tlbwr 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwr 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
tlbwr $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwr $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
dvp 3 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
dvp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
evp 3 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
evp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
jalrc.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
jalrc.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different

llvm/trunk/test/MC/Mips/micromips32r6/valid.s

Show First 20 Lines • Show All 307 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
mfhc0 $20, $21 # CHECK: mfhc0 $20, $21, 0 # encoding: [0x02,0x95,0x00,0xf4] mfhc0 $20, $21 # CHECK: mfhc0 $20, $21, 0 # encoding: [0x02,0x95,0x00,0xf4]
mfhc0 $1, $2, 1 # CHECK: mfhc0 $1, $2, 1 # encoding: [0x00,0x22,0x08,0xf4] mfhc0 $1, $2, 1 # CHECK: mfhc0 $1, $2, 1 # encoding: [0x00,0x22,0x08,0xf4]
mfhc1 $zero, $f6 # CHECK: mfhc1 $zero, $f6 # encoding: [0x54,0x06,0x30,0x3b] mfhc1 $zero, $f6 # CHECK: mfhc1 $zero, $f6 # encoding: [0x54,0x06,0x30,0x3b]
mfhc2 $23, $16 # CHECK: mfhc2 $23, $16 # encoding: [0x02,0xf0,0x8d,0x3c] mfhc2 $23, $16 # CHECK: mfhc2 $23, $16 # encoding: [0x02,0xf0,0x8d,0x3c]
tlbp # CHECK: tlbp # encoding: [0x00,0x00,0x03,0x7c] tlbp # CHECK: tlbp # encoding: [0x00,0x00,0x03,0x7c]
tlbr # CHECK: tlbr # encoding: [0x00,0x00,0x13,0x7c] tlbr # CHECK: tlbr # encoding: [0x00,0x00,0x13,0x7c]
tlbwi # CHECK: tlbwi # encoding: [0x00,0x00,0x23,0x7c] tlbwi # CHECK: tlbwi # encoding: [0x00,0x00,0x23,0x7c]
tlbwr # CHECK: tlbwr # encoding: [0x00,0x00,0x33,0x7c] tlbwr # CHECK: tlbwr # encoding: [0x00,0x00,0x33,0x7c]
dvp # CHECK: dvp $zero # encoding: [0x00,0x00,0x19,0x7c]
dvp $4 # CHECK: dvp $4 # encoding: [0x00,0x04,0x19,0x7c]
evp # CHECK: evp $zero # encoding: [0x00,0x00,0x39,0x7c]
evp $4 # CHECK: evp $4 # encoding: [0x00,0x04,0x39,0x7c]
jalrc.hb $4 # CHECK: jalrc.hb $4 # encoding: [0x03,0xe4,0x1f,0x3c]
jalrc.hb $4, $5 # CHECK: jalrc.hb $4, $5 # encoding: [0x00,0x85,0x1f,0x3c]

llvm/trunk/test/MC/Mips/micromips64r6/invalid.s

Show First 20 Lines • Show All 168 Lines • ▼ Show 20 Lines# RUN: FileCheck %s < %t1
tlbr 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction tlbr 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbr $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction tlbr $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbwi $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwi $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
tlbwi 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwi 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
tlbwi $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwi $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
tlbwr $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwr $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
tlbwr 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwr 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
tlbwr $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwr $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
dvp 3 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
dvp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
evp 3 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
evp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
jalrc.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
jalrc.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different

llvm/trunk/test/MC/Mips/micromips64r6/valid.s

Show First 20 Lines • Show All 219 Lines • ▼ Show 20 Linesa:
daddu $19, 26943 # CHECK: daddiu $19, $19, 26943 # encoding: [0x5e,0x73,0x69,0x3f] daddu $19, 26943 # CHECK: daddiu $19, $19, 26943 # encoding: [0x5e,0x73,0x69,0x3f]
daddu $24, $2, 18079 # CHECK: daddiu $24, $2, 18079 # encoding: [0x5f,0x02,0x46,0x9f] daddu $24, $2, 18079 # CHECK: daddiu $24, $2, 18079 # encoding: [0x5f,0x02,0x46,0x9f]
dsubu $3, 5 # CHECK: daddiu $3, $3, -5 # encoding: [0x5c,0x63,0xff,0xfb] dsubu $3, 5 # CHECK: daddiu $3, $3, -5 # encoding: [0x5c,0x63,0xff,0xfb]
dsubu $3, $4, 5 # CHECK: daddiu $3, $4, -5 # encoding: [0x5c,0x64,0xff,0xfb] dsubu $3, $4, 5 # CHECK: daddiu $3, $4, -5 # encoding: [0x5c,0x64,0xff,0xfb]
tlbp # CHECK: tlbp # encoding: [0x00,0x00,0x03,0x7c] tlbp # CHECK: tlbp # encoding: [0x00,0x00,0x03,0x7c]
tlbr # CHECK: tlbr # encoding: [0x00,0x00,0x13,0x7c] tlbr # CHECK: tlbr # encoding: [0x00,0x00,0x13,0x7c]
tlbwi # CHECK: tlbwi # encoding: [0x00,0x00,0x23,0x7c] tlbwi # CHECK: tlbwi # encoding: [0x00,0x00,0x23,0x7c]
tlbwr # CHECK: tlbwr # encoding: [0x00,0x00,0x33,0x7c] tlbwr # CHECK: tlbwr # encoding: [0x00,0x00,0x33,0x7c]
dvp # CHECK: dvp $zero # encoding: [0x00,0x00,0x19,0x7c]
dvp $4 # CHECK: dvp $4 # encoding: [0x00,0x04,0x19,0x7c]
evp # CHECK: evp $zero # encoding: [0x00,0x00,0x39,0x7c]
evp $4 # CHECK: evp $4 # encoding: [0x00,0x04,0x39,0x7c]
jalrc.hb $4 # CHECK: jalrc.hb $4 # encoding: [0x03,0xe4,0x1f,0x3c]
jalrc.hb $4, $5 # CHECK: jalrc.hb $4, $5 # encoding: [0x00,0x85,0x1f,0x3c]
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