[mips][microMIPS] Implement DVP, EVP and JALRC.HB instructions

[zbuljan]

Summary

The patch implements microMIPSr6 DVP, EVP and JALRC.HB instructions.

[sdardis]

LGTM with some nits (inlined).

The isCTI is only required for MIPSR6 instructions which cannot be placed in a forbidden slot. Since microMIPSR6 doesn't have forbidden slots and cannot be mixed inside MIPSR6 code without going through an ISA change it isn't required.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

3653

Add a note here that it also applies to microMIPSR6.

lib/Target/Mips/MicroMips32r6InstrInfo.td

1020

The 'isCTI' bit isn't required. The only code that cares about the 'isCTI' bit is the SafeInForbiddenSlot predicate which is only used for MIPSR6, not microMIPSR6.

test/MC/Mips/micromips32r6/invalid.s

118

Add evp and dvp with immediate operands here to test that they are rejected.

test/MC/Mips/micromips64r6/invalid.s

148

Here as well.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

if (!isInt<16>(StackOffset)) {
     return;
   }
 
   emitRRI(IsLoad ? Mips::LW : Mips::SW, Mips::GP, Mips::SP, StackOffset, IDLoc,
           Instructions);
 }
 
 unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
   // As described by the Mips32r2 spec, the registers Rd and Rs for
   // jalr.hb must be different.
   unsigned Opcode = Inst.getOpcode();
 
-  if (Opcode == Mips::JALR_HB &&
+  if ((Opcode == Mips::JALR_HB || Opcode == Mips::JALRC_HB_MMR6) &&
       (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()))
     return Match_RequiresDifferentSrcAndDst;
 
   return Match_Success;
 }
 
 static SMLoc RefineErrorLoc(const SMLoc Loc, const OperandVector &Operands,
                             uint64_t ErrorInfo) {

lib/Target/Mips/MicroMips32r6InstrFormats.td

class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
   bits<32> Inst;
 
   let Inst{31-26} = funct;
   let Inst{25-21} = rt;
   let Inst{20-16} = rt;
   let Inst{15-0}  = offset;
 }
 
+class POOL32A_JALRC_FM_MMR6<string instr_asm, bits<10> funct>
+    : MipsR6Inst, MMR6Arch<instr_asm> {
+  bits<5> rt;
+  bits<5> rs;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rs;
+  let Inst{15-6} = funct;
+  let Inst{5-0} = 0b111100;
+}
+
 class POOL32A_ERET_FM_MMR6<string instr_asm, bits<10> funct>
     : MMR6Arch<instr_asm> {
   bits<32> Inst;
 
   let Inst{31-26} = 0x00;
   let Inst{25-16} = 0x00;
   let Inst{15-6}  = funct;
   let Inst{5-0}   = 0x3c;
class POOL32A_MFTC2_FM_MMR6<string instr_asm, bits<10> funct>
   bits<32> Inst;
 
   let Inst{31-26} = 0b000000;
   let Inst{25-21} = rt;
   let Inst{20-16} = impl;
   let Inst{15-6}  = funct;
   let Inst{5-0}   = 0b111100;
 }
+
+class POOL32A_DVPEVP_FM_MMR6<string instr_asm, bits<10> funct>
+    : MMR6Arch<instr_asm>, MipsR6Inst {
+  bits<5> rs;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b000000;
+  let Inst{25-21} = 0b00000;
+  let Inst{20-16} = rs;
+  let Inst{15-6}  = funct;
+  let Inst{5-0}   = 0b111100;
+}

lib/Target/Mips/MicroMips32r6InstrInfo.td

 class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>;
 class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>;
 class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
 class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b101>;
 class LLE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b110>;
 class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>;
 class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
 class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
+class JALRC_HB_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc.hb", 0b0001111100>;
 class RECIP_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.s", 0, 0b01001000>;
 class RECIP_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.d", 1, 0b01001000>;
 class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>;
 class RINT_D_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>;
 class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0,
                                                        0b11001100>;
 class ROUND_L_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.d", 1,
                                                        0b11001100>;

 class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
 class LI16_MMR6_ENC : LI_FM_MM16;
 class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
 class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
 class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
 class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
 class TLBINV_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinv", 0x10d>;
 class TLBINVF_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinvf", 0x14d>;
+class DVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"dvp", 0b0001100101>;
+class EVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"evp", 0b0011100101>;
 
 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
                                   RegisterOperand GPROpnd>
     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
   dag OutOperandList = (outs);
   string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
   list<Register> Defs = [AT];

 class SWSP_MMR6_DESC
     : MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset),
                       !strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>,
       MMR6Arch<"sw">, MicroMipsR6Inst16 {
   let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
   let mayStore = 1;
 }
 
+class JALRC_HB_MMR6_DESC {
+  dag OutOperandList = (outs GPR32Opnd:$rt);
+  dag InOperandList = (ins GPR32Opnd:$rs);
+  string AsmString = !strconcat("jalrc.hb", "\t$rt, $rs");
+  list<dag> Pattern = [];
+  InstrItinClass Itinerary = NoItinerary;
+  Format Form = FrmJ;
+  bit isIndirectBranch = 1;
+  bit hasDelaySlot = 0;
+  bit isCTI = 1;
+}
+
 class TLBINV_MMR6_DESC_BASE<string opstr> {
   dag OutOperandList = (outs);
   dag InOperandList = (ins);
   string AsmString = opstr;
   list<dag> Pattern = [];
 }
 
 class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv">;
 class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf">;
 
+class DVPEVP_MMR6_DESC_BASE<string opstr> {
+  dag OutOperandList = (outs);
+  dag InOperandList = (ins GPR32Opnd:$rs);
+  string AsmString = !strconcat(opstr, "\t$rs");
+  list<dag> Pattern = [];
+}
+
+class DVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"dvp">;
+class EVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"evp">;
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
 let DecoderNamespace = "MicroMipsR6" in {
 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;

 def MOVE16_MMR6 : StdMMR6Rel, MOVE16_MMR6_DESC, MOVE16_MMR6_ENC,
                   ISA_MICROMIPS32R6;
 def SDBBP16_MMR6 : StdMMR6Rel, SDBBP16_MMR6_DESC, SDBBP16_MMR6_ENC,
                    ISA_MICROMIPS32R6;
 def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC,
                   ISA_MICROMIPS32R6;
 def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC,
                  ISA_MICROMIPS32R6;
+def JALRC_HB_MMR6 : R6MMR6Rel, JALRC_HB_MMR6_ENC, JALRC_HB_MMR6_DESC,
+                    ISA_MICROMIPS32R6;
 def RECIP_S_MMR6 : StdMMR6Rel, RECIP_S_MMR6_ENC, RECIP_S_MMR6_DESC,
                    ISA_MICROMIPS32R6;
 def RECIP_D_MMR6 : StdMMR6Rel, RECIP_D_MMR6_ENC, RECIP_D_MMR6_DESC, ISA_MICROMIPS32R6;
 def RINT_S_MMR6 : StdMMR6Rel, RINT_S_MMR6_ENC, RINT_S_MMR6_DESC,
                   ISA_MICROMIPS32R6;
 def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC, ISA_MICROMIPS32R6;
 def ROUND_L_S_MMR6 : StdMMR6Rel, ROUND_L_S_MMR6_ENC, ROUND_L_S_MMR6_DESC,
                      ISA_MICROMIPS32R6;

 def CLASS_S_MMR6 : StdMMR6Rel, CLASS_S_MMR6_ENC, CLASS_S_MMR6_DESC,
                    ISA_MICROMIPS32R6;
 def CLASS_D_MMR6 : StdMMR6Rel, CLASS_D_MMR6_ENC, CLASS_D_MMR6_DESC,
                    ISA_MICROMIPS32R6;
 def TLBINV_MMR6 : StdMMR6Rel, TLBINV_MMR6_ENC, TLBINV_MMR6_DESC,
                   ISA_MICROMIPS32R6;
 def TLBINVF_MMR6 : StdMMR6Rel, TLBINVF_MMR6_ENC, TLBINVF_MMR6_DESC,
                    ISA_MICROMIPS32R6;
+def DVP_MMR6 : R6MMR6Rel, DVP_MMR6_ENC, DVP_MMR6_DESC, ISA_MICROMIPS32R6;
+def EVP_MMR6 : R6MMR6Rel, EVP_MMR6_ENC, EVP_MMR6_DESC, ISA_MICROMIPS32R6;
 }
 
 //===----------------------------------------------------------------------===//
 //
 // MicroMips instruction aliases
 //
 //===----------------------------------------------------------------------===//
 
def : MipsInstAlias<"rdhwr $rt, $rs",
                     (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>,
                     ISA_MICROMIPS32R6;
 def : MipsInstAlias<"mtc0 $rt, $rs",
                     (MTC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
                     ISA_MICROMIPS32R6;
 def : MipsInstAlias<"mthc0 $rt, $rs",
                     (MTHC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
                     ISA_MICROMIPS32R6;
+def : MipsInstAlias<"jalrc.hb $rs", (JALRC_HB_MMR6 RA, GPR32Opnd:$rs), 1>,
+                    ISA_MICROMIPS32R6;
+def : MipsInstAlias<"dvp", (DVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
+def : MipsInstAlias<"evp", (EVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
 
 //===----------------------------------------------------------------------===//
 //
 // MicroMips arbitrary patterns that map to one or more instructions
 //
 //===----------------------------------------------------------------------===//
 
 def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
               (SW16_MMR6 GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS32R6;

test/MC/Disassembler/Mips/micromips32r6/valid.txt

 0x00 0x22 0x3a 0xfc # CHECK: mtc0 $1, $2, 7
 0x54 0x64 0x28 0x3b # CHECK: mtc1 $3, $f4
 0x00 0xa6 0x5d 0x3c # CHECK: mtc2 $5, $6
 0x00 0xe8 0x02 0xf4 # CHECK: mthc0 $7, $8, 0
 0x00 0xe8 0x02 0xf4 # CHECK: mthc0 $7, $8
 0x01 0x2a 0x0a 0xf4 # CHECK: mthc0 $9, $10, 1
 0x55 0x6c 0x38 0x3b # CHECK: mthc1 $11, $f12
 0x01 0xae 0x9d 0x3c # CHECK: mthc2 $13, $14
+0x03 0xe4 0x1f 0x3c # CHECK: jalrc.hb $4
+0x00 0x85 0x1f 0x3c # CHECK: jalrc.hb $4, $5
+0x00 0x00 0x19 0x7c # CHECK: dvp
+0x00 0x04 0x19 0x7c # CHECK: dvp $4
+0x00 0x00 0x39 0x7c # CHECK: evp
+0x00 0x04 0x39 0x7c # CHECK: evp $4

test/MC/Disassembler/Mips/micromips64r6/valid.txt

 0x01 0x2a 0x0a 0xf4 # CHECK: mthc0 $9, $10, 1
 0x55 0x6c 0x38 0x3b # CHECK: mthc1 $11, $f12
 0x01 0xae 0x9d 0x3c # CHECK: mthc2 $13, $14
 0x59 0xf0 0x02 0xfc # CHECK: dmtc0 $15, $16, 0
 0x59 0xf0 0x02 0xfc # CHECK: dmtc0 $15, $16
 0x5a 0x32 0x2a 0xfc # CHECK: dmtc0 $17, $18, 5
 0x56 0x74 0x2c 0x3b # CHECK: dmtc1 $19, $f20
 0x02 0xb6 0x7d 0x3c # CHECK: dmtc2 $21, $22
+0x03 0xe4 0x1f 0x3c # CHECK: jalrc.hb $4
+0x00 0x85 0x1f 0x3c # CHECK: jalrc.hb $4, $5
+0x00 0x00 0x19 0x7c # CHECK: dvp
+0x00 0x04 0x19 0x7c # CHECK: dvp $4
+0x00 0x00 0x39 0x7c # CHECK: evp
+0x00 0x04 0x39 0x7c # CHECK: evp $4

test/MC/Mips/micromips32r6/invalid.s

# RUN: FileCheck %s < %t1
   swm16 $16, $17, 8($sp)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16-$20, 8($sp)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16, $17, $ra, 8($fp)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   mtc0  $4, $3, -1         # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
   mtc0  $4, $3, 8          # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
   mthc0 $4, $3, -1         # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
   mthc0 $4, $3, 8          # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
+  jalrc.hb $31             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
+  jalrc.hb $31, $31        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different

test/MC/Mips/micromips32r6/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
   mtc0 $5, $9              # CHECK: mtc0 $5, $9, 0      # encoding: [0x00,0xa9,0x02,0xfc]
   mtc0 $1, $2, 7           # CHECK: mtc0 $1, $2, 7      # encoding: [0x00,0x22,0x3a,0xfc]
   mtc1 $3, $f4             # CHECK: mtc1 $3, $f4        # encoding: [0x54,0x64,0x28,0x3b]
   mtc2 $5, $6              # CHECK: mtc2 $5, $6         # encoding: [0x00,0xa6,0x5d,0x3c]
   mthc0 $7, $8             # CHECK: mthc0 $7, $8, 0     # encoding: [0x00,0xe8,0x02,0xf4]
   mthc0 $9, $10, 1         # CHECK: mthc0 $9, $10, 1    # encoding: [0x01,0x2a,0x0a,0xf4]
   mthc1 $11, $f12          # CHECK: mthc1 $11, $f12     # encoding: [0x55,0x6c,0x38,0x3b]
   mthc2 $13, $14           # CHECK: mthc2 $13, $14      # encoding: [0x01,0xae,0x9d,0x3c]
+  jalrc.hb $4              # CHECK: jalrc.hb $4         # encoding: [0x03,0xe4,0x1f,0x3c]
+  jalrc.hb $4, $5          # CHECK: jalrc.hb $4, $5     # encoding: [0x00,0x85,0x1f,0x3c]
+  dvp                      # CHECK: dvp $zero           # encoding: [0x00,0x00,0x19,0x7c]
+  dvp $4                   # CHECK: dvp $4              # encoding: [0x00,0x04,0x19,0x7c]
+  evp                      # CHECK: evp $zero           # encoding: [0x00,0x00,0x39,0x7c]
+  evp $4                   # CHECK: evp $4              # encoding: [0x00,0x04,0x39,0x7c]

test/MC/Mips/micromips64r6/invalid.s

# RUN: FileCheck %s < %t1
   swm16 $16, $17, $ra, 8($fp)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   mtc0  $4, $3, -1         # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
   mtc0  $4, $3, 8          # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
   mthc0 $4, $3, -1         # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
   mthc0 $4, $3, 8          # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
   dmtc0  $4, $3, -1        # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
   dmtc0  $4, $3, 8         # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
+  jalrc.hb $31             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
+  jalrc.hb $31, $31        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different

test/MC/Mips/micromips64r6/valid.s

a:
         mthc0 $7, $8             # CHECK: mthc0 $7, $8, 0         # encoding: [0x00,0xe8,0x02,0xf4]
         mthc0 $9, $10, 1         # CHECK: mthc0 $9, $10, 1        # encoding: [0x01,0x2a,0x0a,0xf4]
         mthc1 $11, $f12          # CHECK: mthc1 $11, $f12         # encoding: [0x55,0x6c,0x38,0x3b]
         mthc2 $13, $14           # CHECK: mthc2 $13, $14          # encoding: [0x01,0xae,0x9d,0x3c]
         dmtc0 $15, $16           # CHECK: dmtc0 $15, $16, 0       # encoding: [0x59,0xf0,0x02,0xfc]
         dmtc0 $17, $18, 5        # CHECK: dmtc0 $17, $18, 5       # encoding: [0x5a,0x32,0x2a,0xfc]
         dmtc1 $19, $f20          # CHECK: dmtc1 $19, $f20         # encoding: [0x56,0x74,0x2c,0x3b]
         dmtc2 $21, $22           # CHECK: dmtc2 $21, $22          # encoding: [0x02,0xb6,0x7d,0x3c]
+        jalrc.hb $4              # CHECK: jalrc.hb $4             # encoding: [0x03,0xe4,0x1f,0x3c]
+        jalrc.hb $4, $5          # CHECK: jalrc.hb $4, $5         # encoding: [0x00,0x85,0x1f,0x3c]
+        dvp                      # CHECK: dvp $zero               # encoding: [0x00,0x00,0x19,0x7c]
+        dvp $4                   # CHECK: dvp $4                  # encoding: [0x00,0x04,0x19,0x7c]
+        evp                      # CHECK: evp $zero               # encoding: [0x00,0x00,0x39,0x7c]
+        evp $4                   # CHECK: evp $4                  # encoding: [0x00,0x04,0x39,0x7c]
 
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