[mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions

[zbuljan]

Summary

The patch adds CodeGen support for microMIPSr6 DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions:

• fixed order of registers in encoding definition class for microMIPS64 DDIV, DMOD, DDIVU and DMODU instructions
• updated tests for the standard encodings of DDIV, DMOD, DDIVU and DMODU instructions
• changed description class for microMIPSr6 DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions:
  • enabled insert of "teq $divisor_reg, $zero, 7" instruction in case of division by zero
• added DAG patterns for proper selection of instructions
• separated microMIPSr6 instructions from equivalent MIPS instructions using NotInMicroMips predicate
• added microMIPS pseudo DIV and DIVU instructions with explicit accumulator register operands
• updated .ll files with tests for microMIPSr6 DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions
• fixed "Cannot copy registers" assertion:
  • added GPRMM16_64 register class and updated selection of register class for microMIPS64

[sdardis]

Some nits. You're checking for nops in some cases. Checking for these in my view renders these tests fragile as microMIPS has the 'jrc' instruction which does not have a delay slot and hence a nop would not be required.

lib/Target/Mips/MipsISelLowering.cpp

912 ↗

(On Diff #47635)

Nit: should be IsMicromips.

[sdardis]

Also, this patch should a diff relevant to http://reviews.llvm.org/D17068 .

[zbuljan]

• rebased to work with top of the tree
• removed fix for "Cannot copy registers" as this patch depends on D17068 (rebased on D17068 patch)
• removed checkings for nop instructions (they are not needed for microMIPS)

[sdardis]

LGTM.

llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td

class RDHWR_MMR6_DESC : MMR6Arch<"rdhwr">, MipsR6Inst {
   list<dag> Pattern = [];
   InstrItinClass Itinerary = II_RDHWR;
   Format Form = FrmR;
 }
 
 class WAIT_MMR6_DESC : WaitMM<"wait">;
 class SSNOP_MMR6_DESC : Barrier<"ssnop">;
 class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
-class DIV_MMR6_DESC : ArithLogicR<"div", GPR32Opnd>;
-class DIVU_MMR6_DESC : ArithLogicR<"divu", GPR32Opnd>;
-class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>;
-class MODU_MMR6_DESC : ArithLogicR<"modu", GPR32Opnd>;
+
+class DIVMOD_MMR6_DESC_BASE<string opstr, RegisterOperand GPROpnd,
+                            SDPatternOperator OpNode=null_frag>
+    : MipsR6Inst {
+  dag OutOperandList = (outs GPROpnd:$rd);
+  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
+  string AsmString = !strconcat(opstr, "\t$rd, $rs, $rt");
+  list<dag> Pattern = [(set GPROpnd:$rd, (OpNode GPROpnd:$rs, GPROpnd:$rt))];
+  string BaseOpcode = opstr;
+  Format f = FrmR;
+  let isCommutable = 0;
+  let isReMaterializable = 1;
+
+  // This instruction doesn't trap division by zero itself. We must insert
+  // teq instructions as well.
+  bit usesCustomInserter = 1;
+}
+class DIV_MMR6_DESC  : DIVMOD_MMR6_DESC_BASE<"div", GPR32Opnd, sdiv>;
+class DIVU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"divu", GPR32Opnd, udiv>;
+class MOD_MMR6_DESC  : DIVMOD_MMR6_DESC_BASE<"mod", GPR32Opnd, srem>;
+class MODU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"modu", GPR32Opnd, urem>;
 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>;
 class ANDI_MMR6_DESC : ArithLogicI<"andi", uimm16, GPR32Opnd>;
 class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>;
 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd>;
 class ORI_MMR6_DESC : ArithLogicI<"ori", uimm16, GPR32Opnd>;
 class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>;
 class XORI_MMR6_DESC : ArithLogicI<"xori", uimm16, GPR32Opnd>;
 

llvm/trunk/lib/Target/Mips/MicroMips64r6InstrFormats.td

class POOL32S_DALIGN_FM_MMR6 {
   let Inst{15-11} = rd;
   let Inst{10-8}  = bp;
   let Inst{7-6}   = 0b00;
   let Inst{5-0}   = 0b011100;
 }
 
 class POOL32A_DIVMOD_FM_MMR6<string instr_asm, bits<9> funct>
     : MMR6Arch<instr_asm> {
-  bits<5> rd;
-  bits<5> rs;
   bits<5> rt;
+  bits<5> rs;
+  bits<5> rd;
 
   bits<32> Inst;
 
   let Inst{31-26} = 0b010110;
-  let Inst{25-21} = rd;
+  let Inst{25-21} = rt;
   let Inst{20-16} = rs;
-  let Inst{15-11} = rt;
+  let Inst{15-11} = rd;
   let Inst{10-9}  = 0b00;
   let Inst{8-0}  = funct;
 }
 
 class POOL32S_DMFTC0_FM_MMR6<string instr_asm, bits<5> funct>
     : MMR6Arch<instr_asm>, MipsR6Inst {
   bits<5> rt;
   bits<5> rs;

llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td

class DALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
   dag OutOperandList = (outs GPROpnd:$rd);
   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
   list<dag> Pattern = [];
 }
 
 class DALIGN_MMR6_DESC : DALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
 
-class DDIV_MM64R6_DESC : ArithLogicR<"ddiv", GPR32Opnd>;
-class DMOD_MM64R6_DESC : ArithLogicR<"dmod", GPR32Opnd>;
-class DDIVU_MM64R6_DESC : ArithLogicR<"ddivu", GPR32Opnd>;
-class DMODU_MM64R6_DESC : ArithLogicR<"dmodu", GPR32Opnd>;
+class DDIV_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddiv", GPR64Opnd, sdiv>;
+class DMOD_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"dmod", GPR64Opnd, srem>;
+class DDIVU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddivu", GPR64Opnd, udiv>;
+class DMODU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"dmodu", GPR64Opnd, urem>;
 
 class DINSU_MM64R6_DESC : InsBase<"dinsu", GPR64Opnd, uimm5_plus32,
                                   uimm5_inssize_plus1, MipsIns>;
 class DINSM_MM64R6_DESC : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64>;
 class DINS_MM64R6_DESC : InsBase<"dins", GPR64Opnd, uimm5, uimm5_inssize_plus1,
                                  MipsIns>;
 class DMTC0_MM64R6_DESC : MTC0_MMR6_DESC_BASE<"dmtc0", COP0Opnd, GPR64Opnd>;
 class DMTC1_MM64R6_DESC : MTC1_MMR6_DESC_BASE<"dmtc1", FGR64Opnd, GPR64Opnd,

llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td

let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
   def XOR_MM   : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
                  ADD_FM_MM<0, 0x310>;
   def NOR_MM   : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
   def MULT_MM  : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
                  MULT_FM_MM<0x22c>;
   def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
                  MULT_FM_MM<0x26c>;
   def SDIV_MM  : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
-                 MULT_FM_MM<0x2ac>;
+                 MULT_FM_MM<0x2ac>, ISA_MIPS1_NOT_32R6_64R6;
   def UDIV_MM  : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
-                 MULT_FM_MM<0x2ec>;
+                 MULT_FM_MM<0x2ec>, ISA_MIPS1_NOT_32R6_64R6;
 
   /// Arithmetic Instructions with PC and Immediate
   def ADDIUPC_MM : AddImmUPC<"addiupc", GPRMM16Opnd>, ADDIUPC_FM_MM;
 
   /// Shift Instructions
   def SLL_MM   : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
                  SRA_FM_MM<0, 0>;
   def SRL_MM   : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,

 //===----------------------------------------------------------------------===//
 
 class UncondBranchMMPseudo<string opstr> :
   MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
                     !strconcat(opstr, "\t$offset")>;
 
 def B_MM_Pseudo : UncondBranchMMPseudo<"b">, ISA_MICROMIPS;
 
+def SDIV_MM_Pseudo : MultDivPseudo<SDIV_MM, ACC64, GPR32Opnd, MipsDivRem,
+                                   II_DIV, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
+def UDIV_MM_Pseudo : MultDivPseudo<UDIV_MM, ACC64, GPR32Opnd, MipsDivRemU,
+                                   II_DIVU, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
+
   def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;
   def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>;
   def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>;
 }
 
 let Predicates = [InMicroMips] in {
 def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MIPS32R2;
 def : MipsInstAlias<"di", (DI_MM ZERO), 1>, ISA_MIPS32R2;

llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td

 let AdditionalPredicates = [NotInMicroMips] in {
   def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6, HARDFLOAT;
   def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6, HARDFLOAT;
 }
 def CLO_R6 : R6MMR6Rel, CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6;
 def CLZ_R6 : R6MMR6Rel, CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6;
 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
+let AdditionalPredicates = [NotInMicroMips] in {
   def DIV : R6MMR6Rel, DIV_ENC, DIV_DESC, ISA_MIPS32R6;
   def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
+}
 def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
 def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6;
 def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
 def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;
 def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6;
 def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6;
 def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6;
 def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
 def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
 let AdditionalPredicates = [NotInMicroMips] in {
   def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6, HARDFLOAT;
 }
+let AdditionalPredicates = [NotInMicroMips] in {
   def MOD : R6MMR6Rel, MOD_ENC, MOD_DESC, ISA_MIPS32R6;
   def MODU : R6MMR6Rel, MODU_ENC, MODU_DESC, ISA_MIPS32R6;
+}
 let AdditionalPredicates = [NotInMicroMips] in {
   def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
 }
 def MUH    : R6MMR6Rel, MUH_ENC, MUH_DESC, ISA_MIPS32R6;
 def MUHU   : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
 def MUL_R6 : R6MMR6Rel, MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
 def MULU   : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6;

llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td

 def DMULT  : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>,
              MULT_FM<0, 0x1c>, ISA_MIPS3_NOT_32R6_64R6;
 def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>,
              MULT_FM<0, 0x1d>, ISA_MIPS3_NOT_32R6_64R6;
 def PseudoDMULT  : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
                                  II_DMULT>, ISA_MIPS3_NOT_32R6_64R6;
 def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
                                  II_DMULTU>, ISA_MIPS3_NOT_32R6_64R6;
+let AdditionalPredicates = [NotInMicroMips] in {
   def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>,
               MULT_FM<0, 0x1e>, ISA_MIPS3_NOT_32R6_64R6;
   def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>,
               MULT_FM<0, 0x1f>, ISA_MIPS3_NOT_32R6_64R6;
+}
 def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem,
                                 II_DDIV, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6;
 def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU,
                                 II_DDIVU, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6;
 
 let isCodeGenOnly = 1 in {
 def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>,
              ISA_MIPS3_NOT_32R6_64R6;

llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td

let AdditionalPredicates = [NotInMicroMips] in {
   def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
   def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
   def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
   def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
 }
 def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
 def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
 def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
+let AdditionalPredicates = [NotInMicroMips] in {
   def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
   def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
-def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
   def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
   def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
+}
+def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
 def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
 def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
 def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
 def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
 def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
 def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS32R6;
 def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
 let DecoderNamespace = "Mips32r6_64r6_GP64" in {

llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
   unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
   MF.getRegInfo().addLiveIn(PReg, VReg);
   return VReg;
 }
 
 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr *MI,
                                               MachineBasicBlock &MBB,
                                               const TargetInstrInfo &TII,
-                                              bool Is64Bit) {
+                                              bool Is64Bit, bool IsMicroMips) {
   if (NoZeroDivCheck)
     return &MBB;
 
   // Insert instruction "teq $divisor_reg, $zero, 7".
   MachineBasicBlock::iterator I(MI);
   MachineInstrBuilder MIB;
   MachineOperand &Divisor = MI->getOperand(2);
-  MIB = BuildMI(MBB, std::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ))
+  MIB = BuildMI(MBB, std::next(I), MI->getDebugLoc(),
+                TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
     .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
     .addReg(Mips::ZERO).addImm(7);
 
   // Use the 32-bit sub-register if this is a 64-bit division.
   if (Is64Bit)
     MIB->getOperand(0).setSubReg(Mips::sub_32);
 
   // Clear Divisor's kill flag.
MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
   case Mips::ATOMIC_CMP_SWAP_I64:
     return emitAtomicCmpSwap(MI, BB, 8);
   case Mips::PseudoSDIV:
   case Mips::PseudoUDIV:
   case Mips::DIV:
   case Mips::DIVU:
   case Mips::MOD:
   case Mips::MODU:
-    return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false);
+    return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false,
+                               false);
+  case Mips::SDIV_MM_Pseudo:
+  case Mips::UDIV_MM_Pseudo:
+  case Mips::SDIV_MM:
+  case Mips::UDIV_MM:
+  case Mips::DIV_MMR6:
+  case Mips::DIVU_MMR6:
+  case Mips::MOD_MMR6:
+  case Mips::MODU_MMR6:
+    return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true);
   case Mips::PseudoDSDIV:
   case Mips::PseudoDUDIV:
   case Mips::DDIV:
   case Mips::DDIVU:
   case Mips::DMOD:
   case Mips::DMODU:
-    return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true);
+    return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false);
+  case Mips::DDIV_MM64R6:
+  case Mips::DDIVU_MM64R6:
+  case Mips::DMOD_MM64R6:
+  case Mips::DMODU_MM64R6:
+    return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, true);
   case Mips::SEL_D:
     return emitSEL_D(MI, BB);
 
   case Mips::PseudoSELECT_I:
   case Mips::PseudoSELECT_I64:
   case Mips::PseudoSELECT_S:
   case Mips::PseudoSELECT_D32:
   case Mips::PseudoSELECT_D64:

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
                                 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
 }
 
 /// Multiply and Divide Instructions.
 def MULT  : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
             MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
             MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
+let AdditionalPredicates = [NotInMicroMips] in {
   def SDIV  : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
               MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
   def UDIV  : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
               MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
-
+}
 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
            ISA_MIPS1_NOT_32R6_64R6;
 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
            ISA_MIPS1_NOT_32R6_64R6;
 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
     AdditionalPredicates = [NotInMicroMips] in {
 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
            ISA_MIPS1_NOT_32R6_64R6;

 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
                   ISA_MIPS32_NOT_32R6_64R6;
 def PseudoMSUB  : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
                   ISA_MIPS32_NOT_32R6_64R6;
 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
                   ISA_MIPS32_NOT_32R6_64R6;
 }
 
+let AdditionalPredicates = [NotInMicroMips] in {
   def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
                                  0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
   def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
                                  0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
-let AdditionalPredicates = [NotInMicroMips] in {
   def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
 }
 // TODO: Add '0 < pos+size <= 32' constraint check to ext instruction
 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, immZExt5,
                          immZExt5Plus1, MipsExt>, EXT_FM<0>;
 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, uimm5_inssize_plus1, MipsIns>,
           EXT_FM<4>;
 
 /// Move Control Registers From/To CPU Registers

 // predicates needs to be restored.
 
 def SDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
                                   "div\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6;
 
 def UDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
                                   "divu\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6;
 
-def DSDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
+def DSDivMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
                                    "ddiv\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
 
-def DUDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
+def DUDivMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
                                    "ddivu\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
 
 def Ulh : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
                             "ulh\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
 
 def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
                              "ulhu\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
 

llvm/trunk/test/CodeGen/Mips/llvm-ir/sdiv.ll

 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
 ; RUN:    -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:    -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=R6 -check-prefix=64R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=MM -check-prefix=MMR3 -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=MM -check-prefix=MMR6 -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=MM -check-prefix=MMR6 -check-prefix=MM64
 
 define signext i1 @sdiv_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: sdiv_i1:
 
   ; NOT-R6:       div     $zero, $4, $5
   ; NOT-R6:       teq     $5, $zero, 7
   ; NOT-R6:       mflo    $[[T0:[0-9]+]]
   ; FIXME: The sll/sra instructions are redundant since div is signed.
   ; NOT-R6:       sll     $[[T1:[0-9]+]], $[[T0]], 31
   ; NOT-R6:       sra     $2, $[[T1]], 31
 
   ; R6:           div     $[[T0:[0-9]+]], $4, $5
   ; R6:           teq     $5, $zero, 7
   ; FIXME: The sll/sra instructions are redundant since div is signed.
   ; R6:           sll     $[[T1:[0-9]+]], $[[T0]], 31
   ; R6:           sra     $2, $[[T1]], 31
 
+  ; MMR3:         div     $zero, $4, $5
+  ; MMR3:         teq     $5, $zero, 7
+  ; MMR3:         mflo    $[[T0:[0-9]+]]
+  ; MMR3:         sll     $[[T1:[0-9]+]], $[[T0]], 31
+  ; MMR3:         sra     $2, $[[T1]], 31
+
+  ; MMR6:         div     $[[T0:[0-9]+]], $4, $5
+  ; MMR6:         teq     $5, $zero, 7
+  ; MMR6:         sll     $[[T1:[0-9]+]], $[[T0]], 31
+  ; MMR6:         sra     $2, $[[T1]], 31
+
   %r = sdiv i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @sdiv_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: sdiv_i8:
 
; ALL-LABEL: sdiv_i8:
   ; FIXME: This instruction is redundant.
   ; R2-R5:        seb     $2, $[[T0]]
 
   ; R6:           div     $[[T0:[0-9]+]], $4, $5
   ; R6:           teq     $5, $zero, 7
   ; FIXME: This instruction is redundant.
   ; R6:           seb     $2, $[[T0]]
 
+  ; MMR3:         div     $zero, $4, $5
+  ; MMR3:         teq     $5, $zero, 7
+  ; MMR3:         mflo    $[[T0:[0-9]+]]
+  ; MMR3:         seb     $2, $[[T0]]
+
+  ; MMR6:         div     $[[T0:[0-9]+]], $4, $5
+  ; MMR6:         teq     $5, $zero, 7
+  ; MMR6:         seb     $2, $[[T0]]
+
   %r = sdiv i8 %a, %b
   ret i8 %r
 }
 
 define signext i16 @sdiv_i16(i16 signext %a, i16 signext %b) {
 entry:
 ; ALL-LABEL: sdiv_i16:
 
; ALL-LABEL: sdiv_i16:
   ; FIXME: This is instruction is redundant since div is signed.
   ; R2-R5:        seh     $2, $[[T0]]
 
   ; R6:           div     $[[T0:[0-9]+]], $4, $5
   ; R6:           teq     $5, $zero, 7
   ; FIXME: This is instruction is redundant since div is signed.
   ; R6:           seh     $2, $[[T0]]
 
+  ; MMR3:         div     $zero, $4, $5
+  ; MMR3:         teq     $5, $zero, 7
+  ; MMR3:         mflo    $[[T0:[0-9]+]]
+  ; MMR3:         seh     $2, $[[T0]]
+
+  ; MMR6:         div     $[[T0:[0-9]+]], $4, $5
+  ; MMR6:         teq     $5, $zero, 7
+  ; MMR6:         seh     $2, $[[T0]]
+
   %r = sdiv i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @sdiv_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: sdiv_i32:
 
   ; NOT-R6:       div     $zero, $4, $5
   ; NOT-R6:       teq     $5, $zero, 7
   ; NOT-R6:       mflo    $2
 
   ; R6:           div     $2, $4, $5
   ; R6:           teq     $5, $zero, 7
 
+  ; MMR3:         div     $zero, $4, $5
+  ; MMR3:         teq     $5, $zero, 7
+  ; MMR3:         mflo    $2
+
+  ; MMR6:         div     $2, $4, $5
+  ; MMR6:         teq     $5, $zero, 7
+
   %r = sdiv i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @sdiv_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: sdiv_i64:
 
   ; GP32:         lw      $25, %call16(__divdi3)($gp)
 
   ; GP64-NOT-R6:  ddiv    $zero, $4, $5
   ; GP64-NOT-R6:  teq     $5, $zero, 7
   ; GP64-NOT-R6:  mflo    $2
 
   ; 64R6:         ddiv    $2, $4, $5
   ; 64R6:         teq     $5, $zero, 7
 
+  ; MM32:         lw      $25, %call16(__divdi3)($2)
+
+  ; MM64:         ddiv    $2, $4, $5
+  ; MM64:         teq     $5, $zero, 7
+
   %r = sdiv i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @sdiv_i128(i128 signext %a, i128 signext %b) {
 entry:
   ; ALL-LABEL: sdiv_i128:
 
-    ; GP32:         lw      $25, %call16(__divti3)($gp)
 
-    ; GP64-NOT-R6:  ld      $25, %call16(__divti3)($gp)
-    ; 64R6:         ld      $25, %call16(__divti3)($gp)
 
-    %r = sdiv i128 %a, %b
-    ret i128 %r
+  ; MM32:         lw      $25, %call16(__divti3)($2)
+
+  ; MM64:         ld      $25, %call16(__divti3)($2)
+
 }
+
+define signext i1 @sdiv_0_i1(i1 signext %a) {
+entry:
+; ALL-LABEL: sdiv_0_i8:
+
+  ; NOT-R6:       addiu   $[[T0:[0-9]+]], $zero, 0
+  ; NOT-R6:       div     $zero, $4, $[[T0]]
+  ; NOT-R6:       teq     $[[T0]], $zero, 7
+  ; NOT-R6:       mflo    $[[T1:[0-9]+]]
+  ; NOT-R6:       sll     $[[T2:[0-9]+]], $[[T1]], 31
+  ; NOT-R6:       sra     $2, $[[T2]], 31
+
+  ; R6:           div     $[[T0:[0-9]+]], $4, $zero
+  ; R6:           teq     $zero, $zero, 7
+  ; R6:           sll     $[[T1:[0-9]+]], $[[T0]], 31
+  ; R6:           sra     $2, $[[T1]], 31
+
+  ; MMR3:         lui     $[[T0:[0-9]+]], 0
+  ; MMR3:         div     $zero, $4, $[[T0]]
+  ; MMR3:         teq     $[[T0]], $zero, 7
+  ; MMR3:         mflo    $[[T1:[0-9]+]]
+  ; MMR3:         sll     $[[T2:[0-9]+]], $[[T1]], 31
+  ; MMR3:         sra     $2, $[[T2]], 31
+
+  ; MMR6:         lui     $[[T0:[0-9]+]], 0
+  ; MMR6:         div     $[[T1:[0-9]+]], $4, $[[T0]]
+  ; MMR6:         teq     $[[T0]], $zero, 7
+  ; MMR6:         sll     $[[T2:[0-9]+]], $[[T1]], 31
+  ; MMR6:         sra     $2, $[[T2]], 31
+
+  %r = sdiv i1 %a, 0
+  ret i1 %r
+}
+
+define signext i8 @sdiv_0_i8(i8 signext %a) {
+entry:
+; ALL-LABEL: sdiv_0_i8:
+
+  ; NOT-R2-R6:    addiu   $[[T0:[0-9]+]], $zero, 0
+  ; NOT-R2-R6:    div     $zero, $4, $[[T0]]
+  ; NOT-R2-R6:    teq     $[[T0]], $zero, 7
+  ; NOT-R2-R6:    mflo    $[[T1:[0-9]+]]
+  ; NOT-R2-R6:    sll     $[[T2:[0-9]+]], $[[T1]], 24
+  ; NOT-R2-R6:    sra     $2, $[[T2]], 24
+
+  ; R2-R5:        addiu   $[[T0:[0-9]+]], $zero, 0
+  ; R2-R5:        div     $zero, $4, $[[T0]]
+  ; R2-R5:        teq     $[[T0]], $zero, 7
+  ; R2-R5:        mflo    $[[T1:[0-9]+]]
+  ; R2-R5:        seb     $2, $[[T1]]
+
+  ; R6:           div     $[[T0:[0-9]+]], $4, $zero
+  ; R6:           teq     $zero, $zero, 7
+  ; R6:           seb     $2, $[[T0]]
+
+  ; MMR3:         lui     $[[T0:[0-9]+]], 0
+  ; MMR3:         div     $zero, $4, $[[T0]]
+  ; MMR3:         teq     $[[T0]], $zero, 7
+  ; MMR3:         mflo    $[[T1:[0-9]+]]
+  ; MMR3:         seb     $2, $[[T1]]
+
+  ; MMR6:         lui     $[[T0:[0-9]+]], 0
+  ; MMR6:         div     $[[T1:[0-9]+]], $4, $[[T0]]
+  ; MMR6:         teq     $[[T0]], $zero, 7
+  ; MMR6:         seb     $2, $[[T1]]
+
+  %r = sdiv i8 %a, 0
+  ret i8 %r
+}
+
+define signext i16 @sdiv_0_i16(i16 signext %a) {
+entry:
+; ALL-LABEL: sdiv_0_i16:
+
+  ; NOT-R2-R6:    addiu   $[[T0:[0-9]+]], $zero, 0
+  ; NOT-R2-R6:    div     $zero, $4, $[[T0]]
+  ; NOT-R2-R6:    teq     $[[T0]], $zero, 7
+  ; NOT-R2-R6:    mflo    $[[T1:[0-9]+]]
+  ; NOT-R2-R6:    sll     $[[T2:[0-9]+]], $[[T1]], 16
+  ; NOT-R2-R6:    sra     $2, $[[T2]], 16
+
+  ; R2-R5:        addiu   $[[T0:[0-9]+]], $zero, 0
+  ; R2-R5:        div     $zero, $4, $[[T0]]
+  ; R2-R5:        teq     $[[T0]], $zero, 7
+  ; R2-R5:        mflo    $[[T1:[0-9]+]]
+  ; R2-R5:        seh     $2, $[[T1]]
+
+  ; R6:           div     $[[T0:[0-9]+]], $4, $zero
+  ; R6:           teq     $zero, $zero, 7
+  ; R6:           seh     $2, $[[T0]]
+
+  ; MMR3:         lui     $[[T0:[0-9]+]], 0
+  ; MMR3:         div     $zero, $4, $[[T0]]
+  ; MMR3:         teq     $[[T0]], $zero, 7
+  ; MMR3:         mflo    $[[T1:[0-9]+]]
+  ; MMR3:         seh     $2, $[[T1]]
+
+  ; MMR6:         lui     $[[T0:[0-9]+]], 0
+  ; MMR6:         div     $[[T1:[0-9]+]], $4, $[[T0]]
+  ; MMR6:         teq     $[[T0]], $zero, 7
+  ; MMR6:         seh     $2, $[[T1]]
+
+  %r = sdiv i16 %a, 0
+  ret i16 %r
+}
+
+define signext i32 @sdiv_0_i32(i32 signext %a) {
+entry:
+; ALL-LABEL: sdiv_0_i32:
+
+  ; NOT-R6:       addiu   $[[T0:[0-9]+]], $zero, 0
+  ; NOT-R6:       div     $zero, $4, $[[T0]]
+  ; NOT-R6:       teq     $[[T0]], $zero, 7
+  ; NOT-R6:       mflo    $2
+
+  ; R6:           div     $2, $4, $zero
+  ; R6:           teq     $zero, $zero, 7
+
+  ; MMR3:         lui     $[[T0:[0-9]+]], 0
+  ; MMR3:         div     $zero, $4, $[[T0]]
+  ; MMR3:         teq     $[[T0]], $zero, 7
+  ; MMR3:         mflo    $2
+
+  ; MMR6:         lui     $[[T0:[0-9]+]], 0
+  ; MMR6:         div     $2, $4, $[[T0]]
+  ; MMR6:         teq     $[[T0]], $zero, 7
+
+  %r = sdiv i32 %a, 0
+  ret i32 %r
+}
+
+define signext i64 @sdiv_0_i64(i64 signext %a) {
+entry:
+; ALL-LABEL: sdiv_0_i64:
+
+  ; GP32:         lw      $25, %call16(__divdi3)($gp)
+
+  ; GP64-NOT-R6:  daddiu  $[[T0:[0-9]+]], $zero, 0
+  ; GP64-NOT-R6:  ddiv    $zero, $4, $[[T0]]
+  ; GP64-NOT-R6:  teq     $[[T0]], $zero, 7
+  ; GP64-NOT-R6:  mflo    $2
+
+  ; 64R6:         ddiv    $2, $4, $zero
+  ; 64R6:         teq     $zero, $zero, 7
+
+  ; MM32:         lw      $25, %call16(__divdi3)($2)
+
+  ; MM64:         ddiv    $2, $4, $zero
+  ; MM64:         teq     $zero, $zero, 7
+
+  %r = sdiv i64 %a, 0
+  ret i64 %r
+}
+
+define signext i128 @sdiv_0_i128(i128 signext %a) {
+entry:
+; ALL-LABEL: sdiv_0_i128:
+
+  ; GP32:         lw      $25, %call16(__divti3)($gp)
+
+  ; GP64-NOT-R6:  ld      $25, %call16(__divti3)($gp)
+  ; 64R6:         ld      $25, %call16(__divti3)($gp)
+
+  ; MM32:         lw      $25, %call16(__divti3)($2)
+
+  ; MM64:         ld      $25, %call16(__divti3)($2)
+
+  %r = sdiv i128 %a, 0
+  ret i128 %r
+}

llvm/trunk/test/CodeGen/Mips/llvm-ir/srem.ll

 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
 ; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
 ; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
 ; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:  -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=MM -check-prefix=MMR3 -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=MM -check-prefix=MMR6 -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=MM -check-prefix=MMR6 -check-prefix=MM64
 
 define signext i1 @srem_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: srem_i1:
 
   ; NOT-R6:       div     $zero, $4, $5
   ; NOT-R6:       teq     $5, $zero, 7
   ; NOT-R6:       mfhi    $[[T0:[0-9]+]]
   ; NOT-R6:       sll     $[[T1:[0-9]+]], $[[T0]], 31
   ; NOT-R6:       sra     $2, $[[T1]], 31
 
   ; R6:           mod     $[[T0:[0-9]+]], $4, $5
   ; R6:           teq     $5, $zero, 7
   ; R6:           sll     $[[T3:[0-9]+]], $[[T0]], 31
   ; R6:           sra     $2, $[[T3]], 31
 
+  ; MMR3:         div     $zero, $4, $5
+  ; MMR3:         teq     $5, $zero, 7
+  ; MMR3:         mfhi    $[[T0:[0-9]+]]
+  ; MMR3:         sll     $[[T1:[0-9]+]], $[[T0]], 31
+  ; MMR3:         sra     $2, $[[T1]], 31
+
+  ; MMR6:         mod     $[[T0:[0-9]+]], $4, $5
+  ; MMR6:         teq     $5, $zero, 7
+  ; MMR6:         sll     $[[T1:[0-9]+]], $[[T0]], 31
+  ; MMR6:         sra     $2, $[[T1]], 31
+
   %r = srem i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @srem_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: srem_i8:
 
   ; NOT-R2-R6:    div     $zero, $4, $5
   ; NOT-R2-R6:    teq     $5, $zero, 7
   ; NOT-R2-R6:    mfhi    $[[T0:[0-9]+]]
   ; NOT-R2-R6:    sll     $[[T1:[0-9]+]], $[[T0]], 24
   ; NOT-R2-R6:    sra     $2, $[[T1]], 24
 
   ; R2-R5:        div     $zero, $4, $5
   ; R2-R5:        teq     $5, $zero, 7
   ; R2-R5:        mfhi    $[[T0:[0-9]+]]
   ; R2-R5:        seb     $2, $[[T0]]
 
   ; R6:           mod     $[[T0:[0-9]+]], $4, $5
   ; R6:           teq     $5, $zero, 7
   ; R6:           seb     $2, $[[T0]]
 
+  ; MMR3:         div     $zero, $4, $5
+  ; MMR3:         teq     $5, $zero, 7
+  ; MMR3:         mfhi    $[[T0:[0-9]+]]
+  ; MMR3:         seb     $2, $[[T0]]
+
+  ; MMR6:         mod     $[[T0:[0-9]+]], $4, $5
+  ; MMR6:         teq     $5, $zero, 7
+  ; MMR6:         seb     $2, $[[T0]]
+
   %r = srem i8 %a, %b
   ret i8 %r
 }
 
 define signext i16 @srem_i16(i16 signext %a, i16 signext %b) {
 entry:
 ; ALL-LABEL: srem_i16:
 
   ; NOT-R2-R6:    div     $zero, $4, $5
   ; NOT-R2-R6:    teq     $5, $zero, 7
   ; NOT-R2-R6:    mfhi    $[[T0:[0-9]+]]
   ; NOT-R2-R6:    sll     $[[T1:[0-9]+]], $[[T0]], 16
   ; NOT-R2-R6:    sra     $2, $[[T1]], 16
 
   ; R2-R5:        div     $zero, $4, $5
   ; R2-R5:        teq     $5, $zero, 7
   ; R2-R5:        mfhi    $[[T0:[0-9]+]]
-  ; R2-R5:        seh     $2, $[[T1]]
+  ; R2-R5:        seh     $2, $[[T0]]
 
   ; R6:           mod     $[[T0:[0-9]+]], $4, $5
   ; R6:           teq     $5, $zero, 7
   ; R6:           seh     $2, $[[T0]]
 
+  ; MMR3:         div     $zero, $4, $5
+  ; MMR3:         teq     $5, $zero, 7
+  ; MMR3:         mfhi    $[[T0:[0-9]+]]
+  ; MMR3:         seh     $2, $[[T0]]
+
+  ; MMR6:         mod     $[[T0:[0-9]+]], $4, $5
+  ; MMR6:         teq     $5, $zero, 7
+  ; MMR6:         seh     $2, $[[T0]]
+
   %r = srem i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @srem_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: srem_i32:
 
   ; NOT-R6:       div     $zero, $4, $5
   ; NOT-R6:       teq     $5, $zero, 7
   ; NOT-R6:       mfhi    $2
 
   ; R6:           mod     $2, $4, $5
   ; R6:           teq     $5, $zero, 7
 
+  ; MMR3:         div     $zero, $4, $5
+  ; MMR3:         teq     $5, $zero, 7
+  ; MMR3:         mfhi    $2
+
+  ; MMR6:         mod     $2, $4, $5
+  ; MMR6:         teq     $5, $zero, 7
+
   %r = srem i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @srem_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: srem_i64:
 
   ; GP32:         lw      $25, %call16(__moddi3)($gp)
 
   ; GP64-NOT-R6:  ddiv    $zero, $4, $5
   ; GP64-NOT-R6:  teq     $5, $zero, 7
   ; GP64-NOT-R6:  mfhi    $2
 
   ; 64R6:         dmod    $2, $4, $5
   ; 64R6:         teq     $5, $zero, 7
 
+  ; MM32:         lw      $25, %call16(__moddi3)($2)
+
+  ; MM64:         dmod    $2, $4, $5
+  ; MM64:         teq     $5, $zero, 7
+
   %r = srem i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @srem_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: srem_i128:
 
   ; GP32:         lw      $25, %call16(__modti3)($gp)
 
   ; GP64-NOT-R6:  ld      $25, %call16(__modti3)($gp)
   ; 64-R6:        ld      $25, %call16(__modti3)($gp)
 
+  ; MM32:         lw      $25, %call16(__modti3)($2)
+
+  ; MM64:         ld      $25, %call16(__modti3)($2)
+
   %r = srem i128 %a, %b
   ret i128 %r
 }
+
+define signext i1 @srem_0_i1(i1 signext %a) {
+entry:
+; ALL-LABEL: srem_0_i1:
+
+  ; NOT-R6:       addiu   $[[T0:[0-9]+]], $zero, 0
+  ; NOT-R6:       div     $zero, $4, $[[T0]]
+  ; NOT-R6:       teq     $[[T0]], $zero, 7
+  ; NOT-R6:       mfhi    $[[T1:[0-9]+]]
+  ; NOT-R6:       sll     $[[T2:[0-9]+]], $[[T1]], 31
+  ; NOT-R6:       sra     $2, $[[T2]], 31
+
+  ; R6:           mod     $[[T0:[0-9]+]], $4, $zero
+  ; R6:           teq     $zero, $zero, 7
+  ; R6:           sll     $[[T1:[0-9]+]], $[[T0]], 31
+  ; R6:           sra     $2, $[[T1]], 31
+
+  ; MMR3:         lui     $[[T0:[0-9]+]], 0
+  ; MMR3:         div     $zero, $4, $[[T0]]
+  ; MMR3:         teq     $[[T0]], $zero, 7
+  ; MMR3:         mfhi    $[[T1:[0-9]+]]
+  ; MMR3:         sll     $[[T2:[0-9]+]], $[[T1]], 31
+  ; MMR3:         sra     $2, $[[T2]], 31
+
+  ; MMR6:         lui     $[[T0:[0-9]+]], 0
+  ; MMR6:         mod     $[[T1:[0-9]+]], $4, $[[T0]]
+  ; MMR6:         teq     $[[T0]], $zero, 7
+  ; MMR6:         sll     $[[T2:[0-9]+]], $[[T1]], 31
+  ; MMR6:         sra     $2, $[[T2]], 31
+
+  %r = srem i1 %a, 0
+  ret i1 %r
+}
+
+define signext i8 @srem_0_i8(i8 signext %a) {
+entry:
+; ALL-LABEL: srem_0_i8:
+
+  ; NOT-R2-R6:    addiu   $[[T0:[0-9]+]], $zero, 0
+  ; NOT-R2-R6:    div     $zero, $4, $[[T0]]
+  ; NOT-R2-R6:    teq     $[[T0]], $zero, 7
+  ; NOT-R2-R6:    mfhi    $[[T1:[0-9]+]]
+  ; NOT-R2-R6:    sll     $[[T2:[0-9]+]], $[[T1]], 24
+  ; NOT-R2-R6:    sra     $2, $[[T2]], 24
+
+  ; R2-R5:        addiu   $[[T0:[0-9]+]], $zero, 0
+  ; R2-R5:        div     $zero, $4, $[[T0]]
+  ; R2-R5:        teq     $[[T0]], $zero, 7
+  ; R2-R5:        mfhi    $[[T1:[0-9]+]]
+  ; R2-R5:        seb     $2, $[[T1]]
+
+  ; R6:           mod     $[[T0:[0-9]+]], $4, $zero
+  ; R6:           teq     $zero, $zero, 7
+  ; R6:           seb     $2, $[[T0]]
+
+  ; MMR3:         lui     $[[T0:[0-9]+]], 0
+  ; MMR3:         div     $zero, $4, $[[T0]]
+  ; MMR3:         teq     $[[T0]], $zero, 7
+  ; MMR3:         mfhi    $[[T1:[0-9]+]]
+  ; MMR3:         seb     $2, $[[T1]]
+
+  ; MMR6:         lui     $[[T0:[0-9]+]], 0
+  ; MMR6:         mod     $[[T1:[0-9]+]], $4, $[[T0]]
+  ; MMR6:         teq     $[[T0]], $zero, 7
+  ; MMR6:         seb     $2, $[[T1]]
+
+  %r = srem i8 %a, 0
+  ret i8 %r
+}
+
+define signext i16 @srem_0_i16(i16 signext %a) {
+entry:
+; ALL-LABEL: srem_0_i16:
+
+  ; NOT-R2-R6:    addiu   $[[T0:[0-9]+]], $zero, 0
+  ; NOT-R2-R6:    div     $zero, $4, $[[T0]]
+  ; NOT-R2-R6:    teq     $[[T0]], $zero, 7
+  ; NOT-R2-R6:    mfhi    $[[T1:[0-9]+]]
+  ; NOT-R2-R6:    sll     $[[T2:[0-9]+]], $[[T1]], 16
+  ; NOT-R2-R6:    sra     $2, $[[T2]], 16
+
+  ; R2-R5:        addiu   $[[T0:[0-9]+]], $zero, 0
+  ; R2-R5:        div     $zero, $4, $[[T0]]
+  ; R2-R5:        teq     $[[T0]], $zero, 7
+  ; R2-R5:        mfhi    $[[T1:[0-9]+]]
+  ; R2-R5:        seh     $2, $[[T1]]
+
+  ; R6:           mod     $[[T0:[0-9]+]], $4, $zero
+  ; R6:           teq     $zero, $zero, 7
+  ; R6:           seh     $2, $[[T0]]
+
+  ; MMR3:         lui     $[[T0:[0-9]+]], 0
+  ; MMR3:         div     $zero, $4, $[[T0]]
+  ; MMR3:         teq     $[[T0]], $zero, 7
+  ; MMR3:         mfhi    $[[T1:[0-9]+]]
+  ; MMR3:         seh     $2, $[[T1]]
+
+  ; MMR6:         lui     $[[T0:[0-9]+]], 0
+  ; MMR6:         mod     $[[T1:[0-9]+]], $4, $[[T0]]
+  ; MMR6:         teq     $[[T0]], $zero, 7
+  ; MMR6:         seh     $2, $[[T1]]
+
+  %r = srem i16 %a, 0
+  ret i16 %r
+}
+
+
+define signext i32 @srem_0_i32(i32 signext %a) {
+entry:
+; ALL-LABEL: srem_0_i32:
+
+  ; NOT-R6:       addiu   $[[T0:[0-9]+]], $zero, 0
+  ; NOT-R6:       div     $zero, $4, $[[T0]]
+  ; NOT-R6:       teq     $[[T0]], $zero, 7
+  ; NOT-R6:       mfhi    $2
+
+  ; R6:           mod     $2, $4, $zero
+  ; R6:           teq     $zero, $zero, 7
+
+  ; MMR3:         lui     $[[T0:[0-9]+]], 0
+  ; MMR3:         div     $zero, $4, $[[T0]]
+  ; MMR3:         teq     $[[T0]], $zero, 7
+  ; MMR3:         mfhi    $2
+
+  ; MMR6:         lui     $[[T0:[0-9]+]], 0
+  ; MMR6:         mod     $2, $4, $[[T0]]
+  ; MMR6:         teq     $[[T0]], $zero, 7
+
+  %r = srem i32 %a, 0
+  ret i32 %r
+}
+
+define signext i64 @srem_0_i64(i64 signext %a) {
+entry:
+; ALL-LABEL: srem_0_i64:
+
+  ; GP32:         lw      $25, %call16(__moddi3)($gp)
+
+  ; GP64-NOT-R6:  daddiu  $[[T0:[0-9]+]], $zero, 0
+  ; GP64-NOT-R6:  ddiv    $zero, $4, $[[T0]]
+  ; GP64-NOT-R6:  teq     $[[T0]], $zero, 7
+  ; GP64-NOT-R6:  mfhi    $2
+
+  ; 64R6:         dmod    $2, $4, $zero
+  ; 64R6:         teq     $zero, $zero, 7
+
+  ; MM32:         lw      $25, %call16(__moddi3)($2)
+
+  ; MM64:         dmod    $2, $4, $zero
+  ; MM64:         teq     $zero, $zero, 7
+
+  %r = srem i64 %a, 0
+  ret i64 %r
+}
+
+define signext i128 @srem_0_i128(i128 signext %a) {
+entry:
+; ALL-LABEL: srem_0_i128:
+
+  ; GP32:         lw      $25, %call16(__modti3)($gp)
+
+  ; GP64-NOT-R6:  ld      $25, %call16(__modti3)($gp)
+  ; 64R6:         ld      $25, %call16(__modti3)($gp)
+
+  ; MM32:         lw      $25, %call16(__modti3)($2)
+
+  ; MM64:         ld      $25, %call16(__modti3)($2)
+
+  %r = srem i128 %a, 0
+  ret i128 %r
+}

llvm/trunk/test/CodeGen/Mips/llvm-ir/udiv.ll

 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
 ; RUN:    -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:    -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=R6 -check-prefix=64R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=MM -check-prefix=MMR3 -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=MM -check-prefix=MMR6 -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=MM -check-prefix=MMR6 -check-prefix=MM64
 
 define zeroext i1 @udiv_i1(i1 zeroext %a, i1 zeroext %b) {
 entry:
 ; ALL-LABEL: udiv_i1:
 
   ; NOT-R6:       divu    $zero, $4, $5
   ; NOT-R6:       teq     $5, $zero, 7
   ; NOT-R6:       mflo    $2
 
   ; R6:           divu    $2, $4, $5
   ; R6:           teq     $5, $zero, 7
 
+  ; MMR3:         divu    $zero, $4, $5
+  ; MMR3:         teq     $5, $zero, 7
+  ; MMR3:         mflo    $2
+
+  ; MMR6:         divu    $2, $4, $5
+  ; MMR6:         teq     $5, $zero, 7
+
   %r = udiv i1 %a, %b
   ret i1 %r
 }
 
 define zeroext i8 @udiv_i8(i8 zeroext %a, i8 zeroext %b) {
 entry:
 ; ALL-LABEL: udiv_i8:
 
   ; NOT-R6:       divu    $zero, $4, $5
   ; NOT-R6:       teq     $5, $zero, 7
   ; NOT-R6:       mflo    $2
 
   ; R6:           divu    $2, $4, $5
   ; R6:           teq     $5, $zero, 7
 
+  ; MMR3:         divu    $zero, $4, $5
+  ; MMR3:         teq     $5, $zero, 7
+  ; MMR3:         mflo    $2
+
+  ; MMR6:         divu    $2, $4, $5
+  ; MMR6:         teq     $5, $zero, 7
+
   %r = udiv i8 %a, %b
   ret i8 %r
 }
 
 define zeroext i16 @udiv_i16(i16 zeroext %a, i16 zeroext %b) {
 entry:
 ; ALL-LABEL: udiv_i16:
 
   ; NOT-R6:       divu    $zero, $4, $5
   ; NOT-R6:       teq     $5, $zero, 7
   ; NOT-R6:       mflo    $2
 
   ; R6:           divu    $2, $4, $5
   ; R6:           teq     $5, $zero, 7
 
+  ; MMR3:         divu    $zero, $4, $5
+  ; MMR3:         teq     $5, $zero, 7
+  ; MMR3:         mflo    $2
+
+  ; MMR6:         divu    $2, $4, $5
+  ; MMR6:         teq     $5, $zero, 7
+
   %r = udiv i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @udiv_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: udiv_i32:
 
   ; NOT-R6:       divu    $zero, $4, $5
   ; NOT-R6:       teq     $5, $zero, 7
   ; NOT-R6:       mflo    $2
 
   ; R6:           divu    $2, $4, $5
   ; R6:           teq     $5, $zero, 7
 
+  ; MMR3:         divu    $zero, $4, $5
+  ; MMR3:         teq     $5, $zero, 7
+  ; MMR3:         mflo    $2
+
+  ; MMR6:         divu    $2, $4, $5
+  ; MMR6:         teq     $5, $zero, 7
+
   %r = udiv i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @udiv_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: udiv_i64:
 
   ; GP32:         lw      $25, %call16(__udivdi3)($gp)
 
   ; GP64-NOT-R6:  ddivu   $zero, $4, $5
   ; GP64-NOT-R6:  teq     $5, $zero, 7
   ; GP64-NOT-R6:  mflo    $2
 
   ; 64R6:         ddivu   $2, $4, $5
   ; 64R6:         teq     $5, $zero, 7
 
+  ; MM32:         lw      $25, %call16(__udivdi3)($2)
+
+  ; MM64:         ddivu   $2, $4, $5
+  ; MM64:         teq     $5, $zero, 7
+
   %r = udiv i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @udiv_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: udiv_i128:
 
   ; GP32:         lw      $25, %call16(__udivti3)($gp)
 
   ; GP64-NOT-R6:  ld      $25, %call16(__udivti3)($gp)
   ; 64-R6:        ld      $25, %call16(__udivti3)($gp)
 
+  ; MM32:         lw      $25, %call16(__udivti3)($2)
+
+  ; MM64:         ld      $25, %call16(__udivti3)($2)
+
   %r = udiv i128 %a, %b
   ret i128 %r
 }

llvm/trunk/test/CodeGen/Mips/llvm-ir/urem.ll

 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
 ; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
 ; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
 ; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:  -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=MM -check-prefix=MMR3 -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=MM -check-prefix=MMR6 -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=MM -check-prefix=MMR6 -check-prefix=MM64
 
 define signext i1 @urem_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: urem_i1:
 
   ; NOT-R6:       andi    $[[T0:[0-9]+]], $5, 1
   ; NOT-R6:       andi    $[[T1:[0-9]+]], $4, 1
   ; NOT-R6:       divu    $zero, $[[T1]], $[[T0]]
   ; NOT-R6:       teq     $[[T0]], $zero, 7
   ; NOT-R6:       mfhi    $[[T2:[0-9]+]]
   ; NOT-R6:       sll     $[[T3:[0-9]+]], $[[T2]], 31
   ; NOT-R6:       sra     $2, $[[T3]], 31
 
   ; R6:           andi    $[[T0:[0-9]+]], $5, 1
   ; R6:           andi    $[[T1:[0-9]+]], $4, 1
   ; R6:           modu    $[[T2:[0-9]+]], $[[T1]], $[[T0]]
   ; R6:           teq     $[[T0]], $zero, 7
   ; R6:           sll     $[[T3:[0-9]+]], $[[T2]], 31
   ; R6:           sra     $2, $[[T3]], 31
 
+  ; MMR3:         andi16  $[[T0:[0-9]+]], $5, 1
+  ; MMR3:         andi16  $[[T1:[0-9]+]], $4, 1
+  ; MMR3:         divu    $zero, $[[T1]], $[[T0]]
+  ; MMR3:         teq     $[[T0]], $zero, 7
+  ; MMR3:         mfhi    $[[T2:[0-9]+]]
+  ; MMR3:         sll     $[[T3:[0-9]+]], $[[T2]], 31
+  ; MMR3:         sra     $2, $[[T3]], 31
+
+  ; MMR6:         andi16  $[[T0:[0-9]+]], $5, 1
+  ; MMR6:         andi16  $[[T1:[0-9]+]], $4, 1
+  ; MMR6:         modu    $[[T2:[0-9]+]], $[[T1]], $[[T0]]
+  ; MMR6:         teq     $[[T0]], $zero, 7
+  ; MMR6:         sll     $[[T3:[0-9]+]], $[[T2]], 31
+  ; MMR6:         sra     $2, $[[T3]], 31
+
   %r = urem i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @urem_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: urem_i8:
 
; ALL-LABEL: urem_i8:
   ; R2-R5:        seb     $2, $[[T2]]
 
   ; R6:           andi    $[[T0:[0-9]+]], $5, 255
   ; R6:           andi    $[[T1:[0-9]+]], $4, 255
   ; R6:           modu    $[[T2:[0-9]+]], $[[T1]], $[[T0]]
   ; R6:           teq     $[[T0]], $zero, 7
   ; R6:           seb     $2, $[[T2]]
 
+  ; MMR3:         andi16  $[[T0:[0-9]+]], $5, 255
+  ; MMR3:         andi16  $[[T1:[0-9]+]], $4, 255
+  ; MMR3:         divu    $zero, $[[T1]], $[[T0]]
+  ; MMR3:         teq     $[[T0]], $zero, 7
+  ; MMR3:         mfhi    $[[T2:[0-9]+]]
+  ; MMR3:         seb     $2, $[[T2]]
+
+  ; MMR6:         andi16  $[[T0:[0-9]+]], $5, 255
+  ; MMR6:         andi16  $[[T1:[0-9]+]], $4, 255
+  ; MMR6:         modu    $[[T2:[0-9]+]], $[[T1]], $[[T0]]
+  ; MMR6:         teq     $[[T0]], $zero, 7
+  ; MMR6:         seb     $2, $[[T2]]
+
   %r = urem i8 %a, %b
   ret i8 %r
 }
 
 define signext i16 @urem_i16(i16 signext %a, i16 signext %b) {
 entry:
 ; ALL-LABEL: urem_i16:
 
; ALL-LABEL: urem_i16:
   ; R2-R5:        seh     $2, $[[T2]]
 
   ; R6:           andi    $[[T0:[0-9]+]], $5, 65535
   ; R6:           andi    $[[T1:[0-9]+]], $4, 65535
   ; R6:           modu    $[[T2:[0-9]+]], $[[T1]], $[[T0]]
   ; R6:           teq     $[[T0]], $zero, 7
   ; R6:           seh     $2, $[[T2]]
 
+  ; MMR3:         andi16  $[[T0:[0-9]+]], $5, 65535
+  ; MMR3:         andi16  $[[T1:[0-9]+]], $4, 65535
+  ; MMR3:         divu    $zero, $[[T1]], $[[T0]]
+  ; MMR3:         teq     $[[T0]], $zero, 7
+  ; MMR3:         mfhi    $[[T2:[0-9]+]]
+  ; MMR3:         seh     $2, $[[T2]]
+
+  ; MMR6:         andi16  $[[T0:[0-9]+]], $5, 65535
+  ; MMR6:         andi16  $[[T1:[0-9]+]], $4, 65535
+  ; MMR6:         modu    $[[T2:[0-9]+]], $[[T1]], $[[T0]]
+  ; MMR6:         teq     $[[T0]], $zero, 7
+  ; MMR6:         seh     $2, $[[T2]]
+
   %r = urem i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @urem_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: urem_i32:
 
   ; NOT-R6:       divu    $zero, $4, $5
   ; NOT-R6:       teq     $5, $zero, 7
   ; NOT-R6:       mfhi    $2
 
   ; R6:           modu    $2, $4, $5
   ; R6:           teq     $5, $zero, 7
 
+  ; MMR3:         divu    $zero, $4, $5
+  ; MMR3:         teq     $5, $zero, 7
+  ; MMR3:         mfhi    $2
+
+  ; MMR6:         modu    $2, $4, $5
+  ; MMR6:         teq     $5, $zero, 7
+
   %r = urem i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @urem_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: urem_i64:
 
   ; GP32:         lw      $25, %call16(__umoddi3)($gp)
 
   ; GP64-NOT-R6:  ddivu   $zero, $4, $5
   ; GP64-NOT-R6:  teq     $5, $zero, 7
   ; GP64-NOT-R6:  mfhi    $2
 
   ; 64R6:         dmodu   $2, $4, $5
   ; 64R6:         teq     $5, $zero, 7
 
+  ; MM32:         lw      $25, %call16(__umoddi3)($2)
+
+  ; MM64:         dmodu   $2, $4, $5
+  ; MM64:         teq     $5, $zero, 7
+
   %r = urem i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @urem_i128(i128 signext %a, i128 signext %b) {
 entry:
   ; ALL-LABEL: urem_i128:
 
-    ; GP32:         lw      $25, %call16(__umodti3)($gp)
 
-    ; GP64-NOT-R6:  ld      $25, %call16(__umodti3)($gp)
-    ; 64-R6:        ld      $25, %call16(__umodti3)($gp)
 
+  ; MM32:         lw      $25, %call16(__umodti3)($2)
+
+  ; MM64:         ld      $25, %call16(__umodti3)($2)
+
     %r = urem i128 %a, %b
     ret i128 %r
 }

llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt

 0x44 0xb3 # CHECK: jrcaddiusp 20
 0xf0 0x64 0x00 0x05 # CHECK: daui $3, $4, 5
 0x42 0x23 0x00 0x04 # CHECK: dahi $3, 4
 0x42 0x03 0x00 0x04 # CHECK: dati $3, 4
 0x59 0x26 0x30 0xec # CHECK: dext $9, $6, 3, 7
 0x59 0x26 0x30 0xe4 # CHECK: dextm $9, $6, 3, 39
 0x59 0x26 0x30 0xd4 # CHECK: dextu $9, $6, 35, 7
 0x58 0x43 0x25 0x1c # CHECK: dalign $4, $2, $3, 5
-0x58 0x64 0x29 0x18 # CHECK: ddiv $3, $4, $5
-0x58 0x64 0x29 0x58 # CHECK: dmod $3, $4, $5
-0x58 0x64 0x29 0x98 # CHECK: ddivu $3, $4, $5
-0x58 0x64 0x29 0xd8 # CHECK: dmodu $3, $4, $5
+0x58 0xa4 0x19 0x18 # CHECK: ddiv $3, $4, $5
+0x58 0xa4 0x19 0x58 # CHECK: dmod $3, $4, $5
+0x58 0xa4 0x19 0x98 # CHECK: ddivu $3, $4, $5
+0x58 0xa4 0x19 0xd8 # CHECK: dmodu $3, $4, $5
 0x54 0xa4 0x18 0x30 # CHECK: add.s $f3, $f4, $f5
 0x54 0xc4 0x11 0x30 # CHECK: add.d $f2, $f4, $f6
 0x54 0xa4 0x18 0x70 # CHECK: sub.s $f3, $f4, $f5
 0x54 0xc4 0x11 0x70 # CHECK: sub.d $f2, $f4, $f6
 0x54 0xa4 0x18 0xb0 # CHECK: mul.s $f3, $f4, $f5
 0x54 0xc4 0x11 0xb0 # CHECK: mul.d $f2, $f4, $f6
 0x54 0xa4 0x18 0xf0 # CHECK: div.s $f3, $f4, $f5
 0x54 0xc4 0x11 0xf0 # CHECK: div.d $f2, $f4, $f6

llvm/trunk/test/MC/Mips/micromips64r6/valid.s

a:
         dextu $9, $6, 35, 7      # CHECK: dextu $9, $6, 35, 7  # encoding: [0x59,0x26,0x30,0xd4]
         dalign $4, $2, $3, 5     # CHECK: dalign $4, $2, $3, 5  # encoding: [0x58,0x43,0x25,0x1c]
         lw $3, 32($gp)           # CHECK: lw $3, 32($gp)        # encoding: [0x65,0x88]
         lw $3, 24($sp)           # CHECK: lw $3, 24($sp)        # encoding: [0x48,0x66]
         lw16 $4, 8($17)          # CHECK: lw16 $4, 8($17)       # encoding: [0x6a,0x12]
         lhu16 $3, 4($16)         # CHECK: lhu16 $3, 4($16)      # encoding: [0x29,0x82]
         lbu16 $3, 4($17)         # CHECK: lbu16 $3, 4($17)      # encoding: [0x09,0x94]
         lbu16 $3, -1($17)        # CHECK: lbu16 $3, -1($17)     # encoding: [0x09,0x9f]
-        ddiv $3, $4, $5          # CHECK: ddiv $3, $4, $5     # encoding: [0x58,0x64,0x29,0x18]
-        dmod $3, $4, $5          # CHECK: dmod $3, $4, $5     # encoding: [0x58,0x64,0x29,0x58]
-        ddivu $3, $4, $5         # CHECK: ddivu $3, $4, $5    # encoding: [0x58,0x64,0x29,0x98]
-        dmodu $3, $4, $5         # CHECK: dmodu $3, $4, $5    # encoding: [0x58,0x64,0x29,0xd8]
+        ddiv $3, $4, $5          # CHECK: ddiv $3, $4, $5     # encoding: [0x58,0xa4,0x19,0x18]
+        dmod $3, $4, $5          # CHECK: dmod $3, $4, $5     # encoding: [0x58,0xa4,0x19,0x58]
+        ddivu $3, $4, $5         # CHECK: ddivu $3, $4, $5    # encoding: [0x58,0xa4,0x19,0x98]
+        dmodu $3, $4, $5         # CHECK: dmodu $3, $4, $5    # encoding: [0x58,0xa4,0x19,0xd8]
         add.s $f3, $f4, $f5      # CHECK: add.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x30]
         add.d $f2, $f4, $f6      # CHECK: add.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x30]
         sub.s $f3, $f4, $f5      # CHECK: sub.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x70]
         sub.d $f2, $f4, $f6      # CHECK: sub.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x70]
         mul.s $f3, $f4, $f5      # CHECK: mul.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0xb0]
         mul.d $f2, $f4, $f6      # CHECK: mul.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0xb0]
         div.s $f3, $f4, $f5      # CHECK: div.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0xf0]
         div.d $f2, $f4, $f6      # CHECK: div.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0xf0]