[mips][micromips] Implement DCLO, DCLZ, DROTR, DROTR32 and DROTRV instructions

[hvarga]

Summary

Patch implements DCLO, DCLZ, DROTR, DROTR32 and DROTRV instructions for microMIPS64r6.

[sdardis]

Can you rebase and repost this patch?

You should also extend test/CodeGen/Mips/countleading.ll and test/CodeGen/Mips/mips64shift.ll for checking microMIPS64R6 for these instructions.

lib/Target/Mips/MicroMips64r6InstrFormats.td

222

Rename this to POOL32S_2R_SA5_FM_MMR6. Putting a '_' between the 2R and SA5 makes it a bit clearer that this class describes a instruction with a 2 register and shift amount of 5 form.

lib/Target/Mips/Mips64InstrInfo.td

282–287

These need to be marked NoInMicroMips too.

test/MC/Mips/micromips64r6/valid.s

289

Please restore the blank line at the end.

[hvarga]

Changed FM classes so that they inherit from MipsR6Inst and MMR6Arch.
Changed DESC classes for DCLO, DCLZ, DSBH_DSHD so that they don't inherit from MipsR6Inst and MMR6Arch.
Added BaseOpcode to desc classes that were missing it.
Added two SHIFT_ROTATE classes to serve as DESC_BASE to all shift and rotate instructions in MM64R6.
Added CodeGen support and tests for DROTR, DROTRV, DCLZ, DCLO in MM64R6.

This update has been contributed by @mamidzic.

[sdardis]

Some nits and one minor change+addition.

For convenience, mips64 assemblers treat instructions like drotr as taking an immediate value in the range of 0..63 and then picking the d<op>32 form if required.

You will need to modify MipsMCCodeEmitter::encodeInstruction to do this.

lib/Target/Mips/MicroMips64r6InstrInfo.td

250–251

Like DSLL_, DSRA_, DROTR_MM64R6_DESC should take a uimm6 & immZExt6.

You will then have to modify MipsMCCodeEmitter::encodeInstruction & LowerLargeShift as well to pick the correct D<op> or D<op>32.

lib/Target/Mips/Mips64InstrInfo.td

166–182

Join these two blocks together.

293–295

These two blocks can also be joined together.

lib/Target/Mips/Mips64r6InstrInfo.td

103–111

Join these two block together.

test/CodeGen/Mips/mips64shift.ll

100–101

Once the above change is made, this can be simplified back to drotr $... 54.

[sdardis]

One further thing: drotr and dclo, dclz do not appear in the instruction mapping tables.

[dsanders]

lib/Target/Mips/MicroMips64r6InstrInfo.td

250–251

An alternative way to do this is to make the DROTR32_*_DESC class use immZExtPlus32 so that SelectionDAG picks the correct instruction up front. Then the assembler part can be added using an appropriate InstAlias using the uimm5_plus32 operand. The main benefit of this approach is that we can leave the implementation to tablegen instead of writing custom C++.

I have a slight preference for the tablegen approach but if you go that route then you should also change the MIPS64 version for consistency. If you don't want to change the MIPS64 version right now then I'm ok with using the uimm6 and MipsMCCodeEmitter approach Simon describes for now.

[hvarga]

Added MM64R6 cases to LowerLargeShift and encodeInstruction for DSLL, DSRA and DROTR instructions.
Instruction mapping tables:

Added StdMMR6Rel to DSLL, DSRA, DCLO, and DCLZ Mips64 instructions.
Added R6MMR6Rel to DCLO and DCLZ Mips64R6 instructions.

Joined NotInMicroMips predicate blocks where possible.

This update has been contributed by @mamidzic.

[sdardis]

LGTM.

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

case Mips::DSRL:
     Inst.setOpcode(Mips::DSRL32);
     return;
   case Mips::DSRA:
     Inst.setOpcode(Mips::DSRA32);
     return;
   case Mips::DROTR:
     Inst.setOpcode(Mips::DROTR32);
     return;
+  case Mips::DSLL_MM64R6:
+    Inst.setOpcode(Mips::DSLL32_MM64R6);
+    return;
+  case Mips::DSRA_MM64R6:
+    Inst.setOpcode(Mips::DSRA32_MM64R6);
+    return;
+  case Mips::DROTR_MM64R6:
+    Inst.setOpcode(Mips::DROTR32_MM64R6);
+    return;
   }
 }
 
 // Pick a DINS instruction variant based on the pos and size operands
 static void LowerDins(MCInst& InstIn) {
   assert(InstIn.getNumOperands() == 5 &&
          "Invalid no. of machine operands for DINS!");
 
encodeInstruction(const MCInst &MI, raw_ostream &OS,
   // the check to a function call. Until then, this is more efficient.
   MCInst TmpInst = MI;
   switch (MI.getOpcode()) {
   // If shift amount is >= 32 it the inst needs to be lowered further
   case Mips::DSLL:
   case Mips::DSRL:
   case Mips::DSRA:
   case Mips::DROTR:
+  case Mips::DSLL_MM64R6:
+  case Mips::DSRA_MM64R6:
+  case Mips::DROTR_MM64R6:
     LowerLargeShift(TmpInst);
     break;
     // Double extract instruction is chosen by pos and size operands
   case Mips::DINS:
     LowerDins(TmpInst);
     break;
   // Compact branches, enforce encoding restrictions.
   case Mips::BEQC:

lib/Target/Mips/MicroMips64r6InstrFormats.td

class PCREL18_FM_MMR6<bits<3> funct> : MipsR6Inst {
   bits<32> Inst;
 
   let Inst{31-26} = 0b011110;
   let Inst{25-21} = rt;
   let Inst{20-18} = funct;
   let Inst{17-0} = imm;
 }
 
-class POOL32S_2R_FM_MMR6<bits<10> funct> {
+class POOL32S_2R_FM_MMR6<string instr_asm, bits<10> funct>
+    : MMR6Arch<instr_asm>, MipsR6Inst {
   bits<5> rt;
   bits<5> rs;
 
   bits<32> Inst;
 
   let Inst{31-26} = 0b010110;
   let Inst{25-21} = rt;
   let Inst{20-16} = rs;
   let Inst{15-6} = funct;
   let Inst{5-0} = 0b111100;
 }
 
-class POOL32S_2RSA5B0_FM_MMR6<bits<9> funct> {
+class POOL32S_2RSA5B0_FM_MMR6<string instr_asm, bits<9> funct>
+    : MMR6Arch<instr_asm>, MipsR6Inst {
   bits<5> rt;
   bits<5> rs;
   bits<5> sa;
 
   bits<32> Inst;
 
   let Inst{31-26} = 0b010110;
   let Inst{25-21} = rt;
   let Inst{20-16} = rs;
   let Inst{15-11} = sa;
   let Inst{10-9} = 0b00;
   let Inst{8-0} = funct;
 }
 
-class POOL32S_3R_FM_MMR6<bits<9> funct> {
+class POOL32S_3R_FM_MMR6<string instr_asm, bits<9> funct>
+    : MMR6Arch<instr_asm>, MipsR6Inst {
   bits<5> rt;
   bits<5> rs;
   bits<5> rd;
 
   bits<32> Inst;
 
   let Inst{31-26} = 0b010110;
   let Inst{25-21} = rt;
   let Inst{20-16} = rs;
   let Inst{15-11} = rd;
   let Inst{10-9} = 0b00;
   let Inst{8-0} = funct;
 }

lib/Target/Mips/MicroMips64r6InstrInfo.td

 class DADDU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"daddu", 0b101010000>;
 class LDPC_MMR646_ENC : PCREL18_FM_MMR6<0b110>;
 class DSUB_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dsub", 0b110010000>;
 class DSUBU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dsubu", 0b111010000>;
 class DMUL_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmul", 0b000011000>;
 class DMUH_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmuh", 0b001011000>;
 class DMULU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmulu", 0b010011000>;
 class DMUHU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmuhu", 0b011011000>;
-class DSBH_MM64R6_ENC : POOL32S_2R_FM_MMR6<0b0111101100>;
-class DSHD_MM64R6_ENC : POOL32S_2R_FM_MMR6<0b1111101100>;
-class DSLL_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<0b000000000>;
-class DSLL32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<0b000001000>;
-class DSLLV_MM64R6_ENC : POOL32S_3R_FM_MMR6<0b000010000>;
-class DSRAV_MM64R6_ENC : POOL32S_3R_FM_MMR6<0b010010000>;
-class DSRA_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<0b010000000>;
-class DSRA32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<0b010000100>;
+class DSBH_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dsbh", 0b0111101100>;
+class DSHD_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dshd", 0b1111101100>;
+class DSLL_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsll", 0b000000000>;
+class DSLL32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsll32", 0b000001000>;
+class DSLLV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"dsllv", 0b000010000>;
+class DSRAV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"dsrav", 0b010010000>;
+class DSRA_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsra", 0b010000000>;
+class DSRA32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsra32", 0b010000100>;
+class DCLO_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dclo", 0b0100101100>;
+class DCLZ_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dclz", 0b0101101100>;
+class DROTR_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"drotr", 0b011000000>;
+class DROTR32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"drotr32", 0b011001000>;
+class DROTRV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"drotrv", 0b011010000>;
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Descriptions
 //
 //===----------------------------------------------------------------------===//
 
 class DAUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>

 
 class DALIGN_MMR6_DESC : DALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
 
 class DDIV_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddiv", GPR64Opnd, sdiv>;
 class DMOD_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"dmod", GPR64Opnd, srem>;
 class DDIVU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddivu", GPR64Opnd, udiv>;
 class DMODU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"dmodu", GPR64Opnd, urem>;
 
+class DCLO_MM64R6_DESC {
+  dag OutOperandList = (outs GPR64Opnd:$rt);
+  dag InOperandList = (ins GPR64Opnd:$rs);
+  string AsmString = !strconcat("dclo", "\t$rt, $rs");
+  list<dag> Pattern = [(set GPR64Opnd:$rt, (ctlz (not GPR64Opnd:$rs)))];
+  InstrItinClass Itinerary = II_CLO;
+  Format Form = FrmR;
+  string BaseOpcode = "dclo";
+}
+
+class DCLZ_MM64R6_DESC {
+  dag OutOperandList = (outs GPR64Opnd:$rt);
+  dag InOperandList = (ins GPR64Opnd:$rs);
+  string AsmString = !strconcat("dclz", "\t$rt, $rs");
+  list<dag> Pattern = [(set GPR64Opnd:$rt, (ctlz GPR64Opnd:$rs))];
+  InstrItinClass Itinerary = II_CLZ;
+  Format Form = FrmR;
+  string BaseOpcode = "dclz";
+}
+
 class DINSU_MM64R6_DESC : InsBase<"dinsu", GPR64Opnd, uimm5_plus32,
                                   uimm5_inssize_plus1, MipsIns>;
 class DINSM_MM64R6_DESC : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64>;
 class DINS_MM64R6_DESC : InsBase<"dins", GPR64Opnd, uimm5, uimm5_inssize_plus1,
                                  MipsIns>;
 class DMTC0_MM64R6_DESC : MTC0_MMR6_DESC_BASE<"dmtc0", COP0Opnd, GPR64Opnd>;
 class DMTC1_MM64R6_DESC : MTC1_MMR6_DESC_BASE<"dmtc1", FGR64Opnd, GPR64Opnd,
                                               II_DMTC1, bitconvert>;

 
 class DMUL_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmul", GPR64Opnd, II_DMUL, mul>;
 class DMUH_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmuh", GPR64Opnd, II_DMUH,
                                               mulhs>;
 class DMULU_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMULU>;
 class DMUHU_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmuhu", GPR64Opnd, II_DMUHU,
                                                mulhu>;
 
-class DSBH_DSHD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
-    : MMR6Arch<instr_asm>, MipsR6Inst {
+class DSBH_DSHD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
   dag OutOperandList = (outs GPROpnd:$rt);
   dag InOperandList = (ins GPROpnd:$rs);
   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
   bit hasSideEffects = 0;
   list<dag> Pattern = [];
   InstrItinClass Itinerary = NoItinerary;
   Format Form = FrmR;
+  string BaseOpcode = instr_asm;
 }
 
 class DSBH_MM64R6_DESC : DSBH_DSHD_DESC_BASE<"dsbh", GPR64Opnd>;
 class DSHD_MM64R6_DESC : DSBH_DSHD_DESC_BASE<"dshd", GPR64Opnd>;
 
-class DSLL_DSLL32_DESC_BASE<string instr_asm, Operand ImmOpnd,
+class SHIFT_ROTATE_IMM_MM64R6<string instr_asm, Operand ImmOpnd,
                               InstrItinClass itin,
                               SDPatternOperator OpNode = null_frag,
-                            SDPatternOperator PO = null_frag>
-    : MMR6Arch<instr_asm>, MipsR6Inst {
+                              SDPatternOperator PO = null_frag> {
   dag OutOperandList = (outs GPR64Opnd:$rt);
   dag InOperandList = (ins GPR64Opnd:$rs, ImmOpnd:$sa);
   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
   InstrItinClass Itinerary = itin;
   list<dag> Pattern = [(set GPR64Opnd:$rt, (OpNode GPR64Opnd:$rs, PO:$sa))];
   string TwoOperandAliasConstraint = "$rs = $rt";
+  string BaseOpcode = instr_asm;
 }
 
-class DSLL_MM64R6_DESC : DSLL_DSLL32_DESC_BASE<"dsll", uimm6, II_DSLL, shl,
-                                               immZExt6>;
-class DSLL32_MM64R6_DESC : DSLL_DSLL32_DESC_BASE<"dsll32", uimm5, II_DSLL32>;
-
-class DSLLV_DSRAV_MM64R6_DESC_BASE<string instr_asm, RegisterOperand RO,
-                                   InstrItinClass itin,
-                                   SDPatternOperator OpNode = null_frag>
-    : MMR6Arch<instr_asm>, MipsR6Inst {
-  dag OutOperandList = (outs RO:$rd);
-  dag InOperandList = (ins RO:$rt, GPR32Opnd:$rs);
+class SHIFT_ROTATE_REG_MM64R6<string instr_asm, InstrItinClass itin,
+                              SDPatternOperator OpNode = null_frag> {
+  dag OutOperandList = (outs GPR64Opnd:$rd);
+  dag InOperandList = (ins GPR64Opnd:$rt, GPR32Opnd:$rs);
   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs");
-  list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))];
-  InstrItinClass Itinerary = itin;
-  Format Form = FrmR;
-}
-
-class DSLLV_MM64R6_DESC : DSLLV_DSRAV_MM64R6_DESC_BASE<"dsllv", GPR64Opnd,
-                                                       II_DSLLV, shl>;
-class DSRAV_MM64R6_DESC : DSLLV_DSRAV_MM64R6_DESC_BASE<"dsrav", GPR64Opnd,
-                                                       II_DSRAV, sra>;
-
-class DSRA_DSRA32_MM64R6_DESC_BASE<string instr_asm, Operand ImmOpnd,
-                              RegisterOperand RO, InstrItinClass itin,
-                              SDPatternOperator OpNode = null_frag,
-                              SDPatternOperator PF = null_frag>
-    : MMR6Arch<instr_asm>, MipsR6Inst {
-  dag OutOperandList = (outs RO:$rt);
-  dag InOperandList = (ins RO:$rs, ImmOpnd:$sa);
-  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
-  list<dag> Pattern = [(set RO:$rt, (OpNode RO:$rs, PF:$sa))];
+  list<dag> Pattern = [(set GPR64Opnd:$rd,
+                       (OpNode GPR64Opnd:$rt, GPR32Opnd:$rs))];
   InstrItinClass Itinerary = itin;
   Format Form = FrmR;
   string BaseOpcode = instr_asm;
 }
 
-class DSRA_MM64R6_DESC : DSRA_DSRA32_MM64R6_DESC_BASE<"dsra", uimm6, GPR64Opnd,
-                                                      II_DSRA, sra, immZExt6>;
-class DSRA32_MM64R6_DESC : DSRA_DSRA32_MM64R6_DESC_BASE<"dsra32", uimm5,
-                                                        GPR64Opnd, II_DSRA32>;
+class DSLL_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsll", uimm6, II_DSLL, shl,
+                                                 immZExt6>;
+class DSLL32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsll32", uimm5, II_DSLL32>;
+class DSLLV_MM64R6_DESC : SHIFT_ROTATE_REG_MM64R6<"dsllv", II_DSLLV, shl>;
+class DSRAV_MM64R6_DESC : SHIFT_ROTATE_REG_MM64R6<"dsrav", II_DSRAV, sra>;
+class DSRA_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsra", uimm6, II_DSRA, sra,
+                                                 immZExt6>;
+class DSRA32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsra32", uimm5, II_DSRA32>;
+class DROTR_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"drotr", uimm6, II_DROTR,
+                                                  rotr, immZExt6>;
+class DROTR32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"drotr32", uimm5,
+                                                    II_DROTR32>;
+class DROTRV_MM64R6_DESC : SHIFT_ROTATE_REG_MM64R6<"drotrv", II_DROTRV, rotr>;
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
 let DecoderNamespace = "MicroMipsR6" in {
let DecoderNamespace = "MicroMipsR6" in {
   def DMUL_MM64R6 : R6MMR6Rel, DMUL_MM64R6_DESC, DMUL_MM64R6_ENC,
                     ISA_MICROMIPS64R6;
   def DMUH_MM64R6 : R6MMR6Rel, DMUH_MM64R6_DESC, DMUH_MM64R6_ENC,
                     ISA_MICROMIPS64R6;
   def DMULU_MM64R6 : R6MMR6Rel, DMULU_MM64R6_DESC, DMULU_MM64R6_ENC,
                      ISA_MICROMIPS64R6;
   def DMUHU_MM64R6 : R6MMR6Rel, DMUHU_MM64R6_DESC, DMUHU_MM64R6_ENC,
                      ISA_MICROMIPS64R6;
-  def DSBH_MM64R6 : R6MMR6Rel, DSBH_MM64R6_DESC, DSBH_MM64R6_ENC,
+  def DSBH_MM64R6 : R6MMR6Rel, DSBH_MM64R6_ENC, DSBH_MM64R6_DESC,
                     ISA_MICROMIPS64R6;
-  def DSHD_MM64R6 : R6MMR6Rel, DSHD_MM64R6_DESC, DSHD_MM64R6_ENC,
+  def DSHD_MM64R6 : R6MMR6Rel, DSHD_MM64R6_ENC, DSHD_MM64R6_DESC,
                     ISA_MICROMIPS64R6;
-  def DSLL_MM64R6 : R6MMR6Rel, DSLL_MM64R6_DESC, DSLL_MM64R6_ENC,
+  def DSLL_MM64R6 : StdMMR6Rel, DSLL_MM64R6_ENC, DSLL_MM64R6_DESC,
                     ISA_MICROMIPS64R6;
-  def DSLL32_MM64R6 : R6MMR6Rel, DSLL32_MM64R6_DESC, DSLL32_MM64R6_ENC,
+  def DSLL32_MM64R6 : StdMMR6Rel, DSLL32_MM64R6_ENC, DSLL32_MM64R6_DESC,
                     ISA_MICROMIPS64R6;
-  def DSLLV_MM64R6 : R6MMR6Rel, DSLLV_MM64R6_DESC, DSLLV_MM64R6_ENC,
+  def DSLLV_MM64R6 : StdMMR6Rel, DSLLV_MM64R6_ENC, DSLLV_MM64R6_DESC,
                      ISA_MICROMIPS64R6;
-  def DSRAV_MM64R6 : R6MMR6Rel, DSRAV_MM64R6_DESC, DSRAV_MM64R6_ENC,
+  def DSRAV_MM64R6 : StdMMR6Rel, DSRAV_MM64R6_ENC, DSRAV_MM64R6_DESC,
                     ISA_MICROMIPS64R6;
-  def DSRA_MM64R6 : R6MMR6Rel, DSRA_MM64R6_DESC, DSRA_MM64R6_ENC,
+  def DSRA_MM64R6 : StdMMR6Rel, DSRA_MM64R6_ENC, DSRA_MM64R6_DESC,
                     ISA_MICROMIPS64R6;
-  def DSRA32_MM64R6 : R6MMR6Rel, DSRA32_MM64R6_DESC, DSRA32_MM64R6_ENC,
+  def DSRA32_MM64R6 : StdMMR6Rel, DSRA32_MM64R6_ENC, DSRA32_MM64R6_DESC,
+                    ISA_MICROMIPS64R6;
+  def DCLO_MM64R6 : StdMMR6Rel, R6MMR6Rel, DCLO_MM64R6_ENC, DCLO_MM64R6_DESC,
+                    ISA_MICROMIPS64R6;
+  def DCLZ_MM64R6 : StdMMR6Rel, R6MMR6Rel, DCLZ_MM64R6_ENC, DCLZ_MM64R6_DESC,
+                    ISA_MICROMIPS64R6;
+  def DROTR_MM64R6 : StdMMR6Rel, DROTR_MM64R6_ENC, DROTR_MM64R6_DESC,
+                     ISA_MICROMIPS64R6;
+  def DROTR32_MM64R6 : StdMMR6Rel, DROTR32_MM64R6_ENC, DROTR32_MM64R6_DESC,
+                       ISA_MICROMIPS64R6;
+  def DROTRV_MM64R6 : StdMMR6Rel, DROTRV_MM64R6_ENC, DROTRV_MM64R6_DESC,
                       ISA_MICROMIPS64R6;
 }
 
 //===----------------------------------------------------------------------===//
 //
 // Arbitrary patterns that map to one or more instructions
 //
 //===----------------------------------------------------------------------===//
 

 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)),
               (DADDIU_MM64R6 GPR64:$hi, tglobaltlsaddr:$lo)>, ISA_MICROMIPS64R6;
 
 def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),
               (DADDU_MM64R6 GPR64:$lhs, GPR64:$rhs)>, ISA_MICROMIPS64R6;
 def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm),
               (DADDIU_MM64R6 GPR64:$lhs, imm:$imm)>, ISA_MICROMIPS64R6;
 
+
+def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))),
+              (DROTRV_MM64R6 GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>,
+              ISA_MICROMIPS64R6;
+
+
 def : WrapperPat<tglobaladdr, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
 def : WrapperPat<tconstpool, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
 def : WrapperPat<texternalsym, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
 def : WrapperPat<tblockaddress, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
 def : WrapperPat<tjumptable, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
 def : WrapperPat<tglobaltlsaddr, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
 
 // Carry pattern

lib/Target/Mips/Mips64InstrInfo.td

 def AND64  : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>;
 def OR64   : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>;
 def XOR64  : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>;
 def NOR64  : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;
 }
 
 /// Shift Instructions
 let AdditionalPredicates = [NotInMicroMips] in {
-  def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, immZExt6>,
-               SRA_FM<0x38, 0>, ISA_MIPS3;
+  def DSLL : StdMMR6Rel, shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL,
+                                          shl, immZExt6>,
 }
 def DSRL   : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>,
              SRA_FM<0x3a, 0>, ISA_MIPS3;
 let AdditionalPredicates = [NotInMicroMips] in {
-  def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, immZExt6>,
+  def DSRA : StdMMR6Rel, shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA,
+                                          sra, immZExt6>,
              SRA_FM<0x3b, 0>, ISA_MIPS3;
-}
-let AdditionalPredicates = [NotInMicroMips] in {
-  def DSLLV  : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
+  def DSLLV  : StdMMR6Rel, shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
                SRLV_FM<0x14, 0>, ISA_MIPS3;
 }
 def DSRLV  : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
              SRLV_FM<0x16, 0>, ISA_MIPS3;
 let AdditionalPredicates = [NotInMicroMips] in {
-  def DSRAV  : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
+  def DSRAV  : StdMMR6Rel, shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
                SRLV_FM<0x17, 0>, ISA_MIPS3;
 }
 let AdditionalPredicates = [NotInMicroMips] in {
-  def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
+  def DSLL32 : StdMMR6Rel, shift_rotate_imm<"dsll32", uimm5, GPR64Opnd,
+                                            II_DSLL32>,
                SRA_FM<0x3c, 0>, ISA_MIPS3;
 }
 def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
              SRA_FM<0x3e, 0>, ISA_MIPS3;
 let AdditionalPredicates = [NotInMicroMips] in {
-  def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
+  def DSRA32 : StdMMR6Rel, shift_rotate_imm<"dsra32", uimm5, GPR64Opnd,
+               II_DSRA32>,
                SRA_FM<0x3f, 0>, ISA_MIPS3;
-}
 
 // Rotate Instructions
-def DROTR  : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
-                              immZExt6>,
+  def DROTR  : StdMMR6Rel, shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR,
+                                            rotr, immZExt6>,
                SRA_FM<0x3a, 1>, ISA_MIPS64R2;
-def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
+  def DROTRV : StdMMR6Rel, shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV,
+                                            rotr>,
                SRLV_FM<0x16, 1>, ISA_MIPS64R2;
-def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
+  def DROTR32 : StdMMR6Rel, shift_rotate_imm<"drotr32", uimm5, GPR64Opnd,
+                                             II_DROTR32>,
                 SRA_FM<0x3e, 1>, ISA_MIPS64R2;
+}
 
 /// Load and Store Instructions
 ///  aligned
 let isCodeGenOnly = 1 in {
 def LB64  : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>;
 def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>;
 def LH64  : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>;
 def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>;
 def LW64  : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>;

 
 /// Sign Ext In Register Instructions.
 def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>,
             ISA_MIPS32R2;
 def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>,
             ISA_MIPS32R2;
 }
 
 /// Count Leading
-def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, ISA_MIPS64_NOT_64R6;
-def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>, ISA_MIPS64_NOT_64R6;
+let AdditionalPredicates = [NotInMicroMips] in {
+  def DCLZ : StdMMR6Rel, CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>,
+             ISA_MIPS64_NOT_64R6;
+  def DCLO : StdMMR6Rel, CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>,
+             ISA_MIPS64_NOT_64R6;
 
 /// Double Word Swap Bytes/HalfWords
-let AdditionalPredicates = [NotInMicroMips] in {
   def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2;
   def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>, ISA_MIPS64R2;
 }
 
 def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
 
 let isCodeGenOnly = 1 in
 def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
 
 let AdditionalPredicates = [NotInMicroMips] in {
   // The 'pos + size' constraints are enforced by the code that lowers into
   // MipsISD::Ext.
   def DEXT : ExtBase<"dext", GPR64Opnd, uimm5_report_uimm6, uimm5_plus1,
                      immZExt5, immZExt5Plus1, MipsExt>, EXT_FM<3>;

 
 // variable shift instructions patterns
 def : MipsPat<(shl GPR64:$rt, (i32 (trunc GPR64:$rs))),
               (DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
 def : MipsPat<(srl GPR64:$rt, (i32 (trunc GPR64:$rs))),
               (DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
 def : MipsPat<(sra GPR64:$rt, (i32 (trunc GPR64:$rs))),
               (DSRAV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
+let AdditionalPredicates = [NotInMicroMips] in {
   def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))),
                 (DROTRV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
+}
 
 // 32-to-64-bit extension
 def : MipsPat<(i64 (anyext GPR32:$src)),
               (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
 def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
 
 // Sign extend in register

lib/Target/Mips/Mips64r6InstrInfo.td

 //===----------------------------------------------------------------------===//
 
 let AdditionalPredicates = [NotInMicroMips] in {
   def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
   def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
   def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
   def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
 }
 def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
-def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
-def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
 let AdditionalPredicates = [NotInMicroMips] in {
+  def DCLO_R6 : R6MMR6Rel, DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
+  def DCLZ_R6 : R6MMR6Rel, DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
   def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
   def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
   def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
   def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
 }
 def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
 let AdditionalPredicates = [NotInMicroMips] in {
   def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
   def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
   def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
   def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
 }
 def LDPC: R6MMR6Rel, LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;

test/CodeGen/Mips/countleading.ll

 ; RUN: llc -march=mipsel -mcpu=mips32   < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R1-R2 -check-prefix=MIPS32-GT-R1 %s
 ; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R1-R2 -check-prefix=MIPS32-GT-R1 %s
 ; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R6    -check-prefix=MIPS32-GT-R1 %s
 ; RUN: llc -march=mips64el -mcpu=mips4    < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 %s
 ; RUN: llc -march=mips64el -mcpu=mips64   < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
 ; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
-; R!N: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
+; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
+; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=micromips < %s | FileCheck -check-prefix=ALL -check-prefix=MICROMIPS64 %s
 
 ; Prefixes:
 ;   ALL      - All
 ;   MIPS32-GT-R1 - MIPS64r1 and above (does not include MIPS64's)
 ;   MIPS64-GT-R1 - MIPS64r1 and above
 
 define i32 @ctlz_i32(i32 signext %X) nounwind readnone {
 entry:
 ; ALL-LABEL: ctlz_i32:
 
 ; MIPS4-NOT:     clz
 
 ; MIPS32-GT-R1:  clz $2, $4
 
 ; MIPS64-GT-R1:  clz $2, $4
 
+; MICROMIPS64:   clz $2, $4
+
   %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X, i1 true)
   ret i32 %tmp1
 }
 
 declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
 
 define i32 @ctlo_i32(i32 signext %X) nounwind readnone {
 entry:
 ; ALL-LABEL: ctlo_i32:
 
 ; MIPS4-NOT:     clo
 
 ; MIPS32-GT-R1:  clo $2, $4
 
 ; MIPS64-GT-R1:  clo $2, $4
 
+; MICROMIPS64:   clo $2, $4
+
   %neg = xor i32 %X, -1
   %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg, i1 true)
   ret i32 %tmp1
 }
 
 define i64 @ctlz_i64(i64 %X) nounwind readnone {
 entry:
 ; ALL-LABEL: ctlz_i64:
 
 ; MIPS4-NOT:     dclz
 
 ; MIPS32-GT-R1-DAG: clz $[[R0:[0-9]+]], $4
 ; MIPS32-GT-R1-DAG: clz $[[R1:[0-9]+]], $5
 ; MIPS32-GT-R1-DAG: addiu $[[R2:2+]], $[[R0]], 32
 ; MIPS32-R1-R2-DAG: movn $[[R2]], $[[R1]], $5
 ; MIPS32-R6-DAG:    seleqz $[[R5:[0-9]+]], $[[R2]], $5
 ; MIPS32-R6-DAG:    selnez $[[R6:[0-9]+]], $[[R1]], $5
 ; MIPS32-R6-DAG:    or $2, $[[R6]], $[[R5]]
 ; MIPS32-GT-R1-DAG: addiu $3, $zero, 0
 
 ; MIPS64-GT-R1:  dclz $2, $4
+; MICROMIPS64:   dclz $2, $4
 
   %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
   ret i64 %tmp1
 }
 
 declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
 
 define i64 @ctlo_i64(i64 %X) nounwind readnone {

 ; MIPS32-GT-R1-DAG: xor $[[R4:[0-9]+]], $5, $[[R3]]
 ; MIPS32-R1-R2-DAG: movn $[[R2]], $[[R1]], $[[R4]]
 ; MIPS32-R6-DAG:    selnez $[[R5:[0-9]+]], $[[R1]], $[[R4]]
 ; MIPS32-R6-DAG:    seleqz $[[R6:[0-9]+]], $[[R2]], $[[R4]]
 ; MIPS32-R6-DAG:    or $2, $[[R5]], $[[R6]]
 ; MIPS32-GT-R1-DAG: addiu $3, $zero, 0
 
 ; MIPS64-GT-R1:  dclo $2, $4
+; MICROMIPS64:   dclo $2, $4
 
   %neg = xor i64 %X, -1
   %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
   ret i64 %tmp1
 }

test/CodeGen/Mips/mips64shift.ll

-; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s
+; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS %s
+; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=micromips < %s | FileCheck -check-prefix=ALL -check-prefix=MICROMIPS %s
 
 define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
 entry:
-; CHECK: dsllv
+; ALL: dsllv
   %shl = shl i64 %a0, %a1
   ret i64 %shl
 }
 
 define i64 @f1(i64 %a0, i64 %a1) nounwind readnone {
 entry:
-; CHECK: dsrav
+; ALL: dsrav
   %shr = ashr i64 %a0, %a1
   ret i64 %shr
 }
 
 define i64 @f2(i64 %a0, i64 %a1) nounwind readnone {
 entry:
-; CHECK: dsrlv
+; ALL: dsrlv
   %shr = lshr i64 %a0, %a1
   ret i64 %shr
 }
 
 define i64 @f3(i64 %a0) nounwind readnone {
 entry:
-; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 10
+; ALL: dsll ${{[0-9]+}}, ${{[0-9]+}}, 10
   %shl = shl i64 %a0, 10
   ret i64 %shl
 }
 
 define i64 @f4(i64 %a0) nounwind readnone {
 entry:
-; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 10
+; ALL: dsra ${{[0-9]+}}, ${{[0-9]+}}, 10
   %shr = ashr i64 %a0, 10
   ret i64 %shr
 }
 
 define i64 @f5(i64 %a0) nounwind readnone {
 entry:
-; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10
+; ALL: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10
   %shr = lshr i64 %a0, 10
   ret i64 %shr
 }
 
 define i64 @f6(i64 %a0) nounwind readnone {
 entry:
-; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 40
+; ALL: dsll ${{[0-9]+}}, ${{[0-9]+}}, 40
   %shl = shl i64 %a0, 40
   ret i64 %shl
 }
 
 define i64 @f7(i64 %a0) nounwind readnone {
 entry:
-; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 40
+; ALL: dsra ${{[0-9]+}}, ${{[0-9]+}}, 40
   %shr = ashr i64 %a0, 40
   ret i64 %shr
 }
 
 define i64 @f8(i64 %a0) nounwind readnone {
 entry:
-; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 40
+; ALL: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 40
   %shr = lshr i64 %a0, 40
   ret i64 %shr
 }
 
 define i64 @f9(i64 %a0, i64 %a1) nounwind readnone {
 entry:
 ; CHECK-NOT:  sll
-; CHECK:      drotrv
+; ALL:      drotrv
   %shr = lshr i64 %a0, %a1
   %sub = sub i64 64, %a1
   %shl = shl i64 %a0, %sub
   %or = or i64 %shl, %shr
   ret i64 %or
 }
 
 define i64 @f10(i64 %a0, i64 %a1) nounwind readnone {
 entry:
 ; CHECK-NOT:  sll
-; CHECK:      drotrv
+; ALL:      drotrv
   %shl = shl i64 %a0, %a1
   %sub = sub i64 64, %a1
   %shr = lshr i64 %a0, %sub
   %or = or i64 %shr, %shl
   ret i64 %or
 }
 
 define i64 @f11(i64 %a0) nounwind readnone {
 entry:
-; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10
+; ALL: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10
   %shr = lshr i64 %a0, 10
   %shl = shl i64 %a0, 54
   %or = or i64 %shr, %shl
   ret i64 %or
 }
 
 define i64 @f12(i64 %a0) nounwind readnone {
 entry:
-; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 54
+; ALL:       drotr ${{[0-9]+}}, ${{[0-9]+}}, 54
   %shl = shl i64 %a0, 10
   %shr = lshr i64 %a0, 54
   %or = or i64 %shl, %shr
   ret i64 %or
 }
 
 

test/MC/Disassembler/Mips/micromips64r6/valid.txt

 0x58 0x64 0x28 0x08 # CHECK: dsll32 $3, $4, 5
 0x58 0xa6 0x20 0x10 # CHECK: dsllv $4, $5, $6
 0x58 0x85 0x28 0x80 # CHECK: dsra $4, $5, 5
 0x58 0xa6 0x20 0x90 # CHECK: dsrav $4, $5, $6
 0x41 0x1f 0x00 0x02 # CHECK: bc1eqzc $f31, 4
 0x41 0x3f 0x00 0x02 # CHECK: bc1nezc $f31, 4
 0x41 0x5f 0x00 0x04 # CHECK: bc2eqzc $31, 8
 0x41 0x7f 0x00 0x04 # CHECK: bc2nezc $31, 8
+0x58 0x22 0x4b 0x3c # CHECK: dclo $1, $2
+0x58 0x22 0x5b 0x3c # CHECK: dclz $1, $2
+0x58 0xaa 0x40 0xc0 # CHECK: drotr $5, $10, 8
+0x58 0x22 0x20 0xc8 # CHECK: drotr32 $1, $2, 4
+0x58 0xc4 0x18 0xd0 # CHECK: drotrv $3, $6, $4

test/MC/Mips/micromips64r6/invalid.s

# RUN: FileCheck %s < %t1
   bc2eqzc $31, -65537          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
   bc2eqzc $31, 65535           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
   bc2eqzc $31, 65536           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
   bc2nezc $32, 4               # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
   bc2nezc $31, -65535          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
   bc2nezc $31, -65537          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
   bc2nezc $31, 65535           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
   bc2nezc $31, 65536           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
+  drotr $5, $10, 64            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
+  drotr $5, $10, -1            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
+  drotr32 $1, $2, 32           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
+  drotr32 $1, $2, -1           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate

test/MC/Mips/micromips64r6/valid.s

a:
         dsllv $4, $5, $6         # CHECK: dsllv $4, $5, $6        # encoding: [0x58,0xa6,0x20,0x10]
         dsra $4, $5, 5           # CHECK: dsra $4, $5, 5          # encoding: [0x58,0x85,0x28,0x80]
         dsra32 $4, $5, 5         # CHECK: dsra32 $4, $5, 5        # encoding: [0x58,0x85,0x28,0x84]
         dsrav $4, $5, $6         # CHECK: dsrav $4, $5, $6        # encoding: [0x58,0xa6,0x20,0x90]
         bc1eqzc $f31, 4          # CHECK: bc1eqzc $f31, 4         # encoding: [0x41,0x1f,0x00,0x02]
         bc1nezc $f31, 4          # CHECK: bc1nezc $f31, 4         # encoding: [0x41,0x3f,0x00,0x02]
         bc2eqzc $31, 8           # CHECK: bc2eqzc $31, 8          # encoding: [0x41,0x5f,0x00,0x04]
         bc2nezc $31, 8           # CHECK: bc2nezc $31, 8          # encoding: [0x41,0x7f,0x00,0x04]
+        dclo $1, $2              # CHECK: dclo $1, $2             # encoding: [0x58,0x22,0x4b,0x3c]
+        dclz $1, $2              # CHECK: dclz $1, $2             # encoding: [0x58,0x22,0x5b,0x3c]
+        drotr $5, $10, 8         # CHECK: drotr $5, $10, 8        # encoding: [0x58,0xaa,0x40,0xc0]
+        drotr32 $1, $2, 4        # CHECK: drotr32 $1, $2, 4       # encoding: [0x58,0x22,0x20,0xc8]
+        drotrv $3, $6, $4        # CHECK: drotrv $3, $6, $4       # encoding: [0x58,0xc4,0x18,0xd0]
 
 1: