[mips][micromips] Implement DCLO, DCLZ, DROTR, DROTR32 and DROTRV instructions

[hvarga]

Summary

Patch implements DCLO, DCLZ, DROTR, DROTR32 and DROTRV instructions for microMIPS64r6.

[sdardis]

Can you rebase and repost this patch?

You should also extend test/CodeGen/Mips/countleading.ll and test/CodeGen/Mips/mips64shift.ll for checking microMIPS64R6 for these instructions.

lib/Target/Mips/MicroMips64r6InstrFormats.td

118

Rename this to POOL32S_2R_SA5_FM_MMR6. Putting a '_' between the 2R and SA5 makes it a bit clearer that this class describes a instruction with a 2 register and shift amount of 5 form.

lib/Target/Mips/Mips64InstrInfo.td

260–261

These need to be marked NoInMicroMips too.

test/MC/Mips/micromips64r6/valid.s

157

Please restore the blank line at the end.

[hvarga]

Changed FM classes so that they inherit from MipsR6Inst and MMR6Arch.
Changed DESC classes for DCLO, DCLZ, DSBH_DSHD so that they don't inherit from MipsR6Inst and MMR6Arch.
Added BaseOpcode to desc classes that were missing it.
Added two SHIFT_ROTATE classes to serve as DESC_BASE to all shift and rotate instructions in MM64R6.
Added CodeGen support and tests for DROTR, DROTRV, DCLZ, DCLO in MM64R6.

This update has been contributed by @mamidzic.

[sdardis]

Some nits and one minor change+addition.

For convenience, mips64 assemblers treat instructions like drotr as taking an immediate value in the range of 0..63 and then picking the d<op>32 form if required.

You will need to modify MipsMCCodeEmitter::encodeInstruction to do this.

lib/Target/Mips/MicroMips64r6InstrInfo.td

101–102

Like DSLL_, DSRA_, DROTR_MM64R6_DESC should take a uimm6 & immZExt6.

You will then have to modify MipsMCCodeEmitter::encodeInstruction & LowerLargeShift as well to pick the correct D<op> or D<op>32.

lib/Target/Mips/Mips64InstrInfo.td

149–163

Join these two blocks together.

267–269

These two blocks can also be joined together.

lib/Target/Mips/Mips64r6InstrInfo.td

103–113 ↗

(On Diff #59517)

Join these two block together.

test/CodeGen/Mips/mips64shift.ll

100–101 ↗

(On Diff #59517)

Once the above change is made, this can be simplified back to drotr $... 54.

[sdardis]

One further thing: drotr and dclo, dclz do not appear in the instruction mapping tables.

[dsanders]

lib/Target/Mips/MicroMips64r6InstrInfo.td

101–102

An alternative way to do this is to make the DROTR32_*_DESC class use immZExtPlus32 so that SelectionDAG picks the correct instruction up front. Then the assembler part can be added using an appropriate InstAlias using the uimm5_plus32 operand. The main benefit of this approach is that we can leave the implementation to tablegen instead of writing custom C++.

I have a slight preference for the tablegen approach but if you go that route then you should also change the MIPS64 version for consistency. If you don't want to change the MIPS64 version right now then I'm ok with using the uimm6 and MipsMCCodeEmitter approach Simon describes for now.

[hvarga]

Added MM64R6 cases to LowerLargeShift and encodeInstruction for DSLL, DSRA and DROTR instructions.
Instruction mapping tables:

Added StdMMR6Rel to DSLL, DSRA, DCLO, and DCLZ Mips64 instructions.
Added R6MMR6Rel to DCLO and DCLZ Mips64R6 instructions.

Joined NotInMicroMips predicate blocks where possible.

This update has been contributed by @mamidzic.

[sdardis]

LGTM.

lib/Target/Mips/MicroMips64r6InstrFormats.td

class POOL32A_DIVMOD_FM_MMR6<string instr_asm, bits<9> funct>
 
   let Inst{31-26} = 0b010110;
   let Inst{25-21} = rd;
   let Inst{20-16} = rs;
   let Inst{15-11} = rt;
   let Inst{10-9}  = 0b00;
   let Inst{8-0}  = funct;
 }
+
+class POOL32S_2R_FM_MMR6<string instr_asm, bits<10> funct>
+    : MMR6Arch<instr_asm> {
+  bits<5> rd;
+  bits<5> rs;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b010110;
+  let Inst{25-21} = rd;
+  let Inst{20-16} = rs;
+  let Inst{15-6}  = funct;
+  let Inst{5-0}   = 0b111100;
+}
+
+class POOL32S_3R_FM_MMR6<string instr_asm, bits<9> funct>
+    : MMR6Arch<instr_asm> {
+  bits<5> rt;
+  bits<5> rs;
+  bits<5> rd;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b010110;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rs;
+  let Inst{15-11} = rd;
+  let Inst{10-9}  = 0b00;
+  let Inst{8-0}   = funct;
+}
+
+class POOL32S_2RSA5_FM_MMR6<string instr_asm, bits<9> funct> {
+  bits<5> rt;
+  bits<5> rs;
+  bits<5> sa;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b010110;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rs;
+  let Inst{15-11} = sa;
+  let Inst{10-9}  = 0b00;
+  let Inst{8-0}   = funct;
+}

lib/Target/Mips/MicroMips64r6InstrInfo.td

 class DEXT_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b101100>;
 class DEXTM_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b100100>;
 class DEXTU_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b010100>;
 class DALIGN_MMR6_ENC : POOL32S_DALIGN_FM_MMR6;
 class DDIV_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddiv", 0b100011000>;
 class DMOD_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmod", 0b101011000>;
 class DDIVU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddivu", 0b110011000>;
 class DMODU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmodu", 0b111011000>;
+class DCLO_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dclo", 0b0100101100>;
+class DCLZ_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dclz", 0b0101101100>;
+class DROTR_MM64R6_ENC : POOL32S_2RSA5_FM_MMR6<"drotr", 0b011000000>;
+class DROTR32_MM64R6_ENC : POOL32S_2RSA5_FM_MMR6<"drotr32", 0b011001000>;
+class DROTRV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"drotrv", 0b011010000>;
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Descriptions
 //
 //===----------------------------------------------------------------------===//
 
 class DAUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>

 }
 
 class DALIGN_MMR6_DESC : DALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
 
 class DDIV_MM64R6_DESC : ArithLogicR<"ddiv", GPR32Opnd>;
 class DMOD_MM64R6_DESC : ArithLogicR<"dmod", GPR32Opnd>;
 class DDIVU_MM64R6_DESC : ArithLogicR<"ddivu", GPR32Opnd>;
 class DMODU_MM64R6_DESC : ArithLogicR<"dmodu", GPR32Opnd>;
+class DCLO_MM64R6_DESC : CountLeading1<"dclo", GPR64Opnd>;
+class DCLZ_MM64R6_DESC : CountLeading0<"dclz", GPR64Opnd>;
+
+class SHIFT_ROTATE_IMM_MM64R6<string instr_asm, Operand ImmOpnd,
+                              RegisterOperand RO, InstrItinClass itin,
+                              SDPatternOperator OpNode = null_frag,
+                              SDPatternOperator PF = null_frag>
+    : MMR6Arch<instr_asm>, MipsR6Inst {
+  dag OutOperandList = (outs RO:$rt);
+  dag InOperandList = (ins RO:$rs, ImmOpnd:$sa);
+  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
+  list<dag> Pattern = [(set RO:$rt, (OpNode RO:$rs, PF:$sa))];
+  InstrItinClass Itinerary = itin;
+  Format Form = FrmR;
+  string BaseOpcode = instr_asm;
+}
+
+class DROTR_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"drotr", uimm5, GPR64Opnd,
+                                                  II_DROTR, rotr, immZExt5>;
+class DROTR32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"drotr32", uimm5, GPR64Opnd,
+                                                    II_DROTR32>;
+class DROTRV_MM64R6_DESC : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV,
+                                            rotr>;
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
 let DecoderNamespace = "MicroMipsR6" in {
let DecoderNamespace = "MicroMipsR6" in {
   def DDIV_MM64R6 : R6MMR6Rel, DDIV_MM64R6_DESC, DDIV_MM64R6_ENC,
                     ISA_MICROMIPS64R6;
   def DMOD_MM64R6 : R6MMR6Rel, DMOD_MM64R6_DESC, DMOD_MM64R6_ENC,
                     ISA_MICROMIPS64R6;
   def DDIVU_MM64R6 : R6MMR6Rel, DDIVU_MM64R6_DESC, DDIVU_MM64R6_ENC,
                      ISA_MICROMIPS64R6;
   def DMODU_MM64R6 : R6MMR6Rel, DMODU_MM64R6_DESC, DMODU_MM64R6_ENC,
                      ISA_MICROMIPS64R6;
+  def DCLO_MM64R6 : StdMMR6Rel, DCLO_MM64R6_DESC, DCLO_MM64R6_ENC,
+                    ISA_MICROMIPS64R6;
+  def DCLZ_MM64R6 : StdMMR6Rel, DCLZ_MM64R6_DESC, DCLZ_MM64R6_ENC,
+                    ISA_MICROMIPS64R6;
+  def DROTR_MM64R6 : StdMMR6Rel, DROTR_MM64R6_DESC, DROTR_MM64R6_ENC,
+                     ISA_MICROMIPS64R6;
+  def DROTR32_MM64R6 : StdMMR6Rel, DROTR32_MM64R6_DESC, DROTR32_MM64R6_ENC,
+                       ISA_MICROMIPS64R6;
+  def DROTRV_MM64R6 : StdMMR6Rel, DROTRV_MM64R6_DESC, DROTRV_MM64R6_ENC,
+                      ISA_MICROMIPS64R6;
 }

lib/Target/Mips/Mips64InstrInfo.td

def DSLLV  : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
              SRLV_FM<0x14, 0>, ISA_MIPS3;
 def DSRLV  : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
              SRLV_FM<0x16, 0>, ISA_MIPS3;
 def DSRAV  : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
              SRLV_FM<0x17, 0>, ISA_MIPS3;
 def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
              SRA_FM<0x3c, 0>, ISA_MIPS3;
 def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
              SRA_FM<0x3e, 0>, ISA_MIPS3;
 def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
              SRA_FM<0x3f, 0>, ISA_MIPS3;
 
 // Rotate Instructions
+let AdditionalPredicates = [NotInMicroMips] in {
   def DROTR  : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
                                 immZExt6>,
                SRA_FM<0x3a, 1>, ISA_MIPS64R2;
   def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
                SRLV_FM<0x16, 1>, ISA_MIPS64R2;
   def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
                 SRA_FM<0x3e, 1>, ISA_MIPS64R2;
+}
 
 /// Load and Store Instructions
 ///  aligned
 let isCodeGenOnly = 1 in {
 def LB64  : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>;
 def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>;
 def LH64  : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>;
 def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>;
 def LW64  : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>;

 /// Sign Ext In Register Instructions.
 def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>,
             ISA_MIPS32R2;
 def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>,
             ISA_MIPS32R2;
 }
 
 /// Count Leading
 def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, ISA_MIPS64_NOT_64R6;
 def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>, ISA_MIPS64_NOT_64R6;
 
 /// Double Word Swap Bytes/HalfWords
 def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2;
 def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>, ISA_MIPS64R2;
 
 def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
 
 let isCodeGenOnly = 1 in
 def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
 
 let AdditionalPredicates = [NotInMicroMips] in {
   // TODO: Add 'pos + size' constraint check to dext* instructions
   //       DEXT: 0 < pos + size <= 63
   //       DEXTM, DEXTU: 32 < pos + size <= 64
   def DEXT : ExtBase<"dext", GPR64Opnd, uimm5, uimm5_plus1, MipsExt>,
              EXT_FM<3>;

test/MC/Disassembler/Mips/micromips64r6/valid.txt

 0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8
 0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3
 0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
 0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
 0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
 0x00 0x00 0xe3 0x7c # CHECK: deret
 0x00 0x00 0x47 0x7c # CHECK: di
 0x00 0x0f 0x47 0x7c # CHECK: di $15
+0x58 0x22 0x4b 0x3c # CHECK: dclo $1, $2
+0x58 0x22 0x5b 0x3c # CHECK: dclz $1, $2
+0x58 0xaa 0x40 0xc0 # CHECK: drotr $5, $10, 8
+0x58 0x22 0x20 0xc8 # CHECK: drotr32 $1, $2, 4
+0x58 0xc4 0x18 0xd0 # CHECK: drotrv $3, $6, $4

test/MC/Mips/micromips64r6/invalid.s

# RUN: FileCheck %s < %t1
   swm16 $5, $6, $ra, 8($sp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
   swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
   swm16 $16-$25, $ra, 8($sp)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
   swm16 $16, 8($sp)           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16, $17, 8($sp)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16-$20, 8($sp)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16, $17, $ra, 8($fp)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  drotr $5, $10, 64            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
+  drotr $5, $10, -1            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
+  drotr32 $1, $2, 32           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
+  drotr32 $1, $2, -1           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate

test/MC/Mips/micromips64r6/valid.s

a:
         selnez.s $f1, $f2, $f3   # CHECK: selnez.s $f1, $f2, $f3  # encoding: [0x54,0x62,0x08,0x78]
         selnez.d $f2, $f4, $f8   # CHECK: selnez.d $f2, $f4, $f8  # encoding: [0x55,0x04,0x12,0x78]
         class.s $f2, $f3         # CHECK: class.s $f2, $f3        # encoding: [0x54,0x62,0x00,0x60]
         class.d $f2, $f4         # CHECK: class.d $f2, $f4        # encoding: [0x54,0x82,0x02,0x60]
         deret                    # CHECK: deret                   # encoding: [0x00,0x00,0xe3,0x7c]
         di                       # CHECK: di                      # encoding: [0x00,0x00,0x47,0x7c]
         di $0                    # CHECK: di                      # encoding: [0x00,0x00,0x47,0x7c]
         di $15                   # CHECK: di $15                  # encoding: [0x00,0x0f,0x47,0x7c]
-
+        dclo $1, $2              # CHECK: dclo $1, $2             # encoding: [0x58,0x22,0x4b,0x3c]
+        dclz $1, $2              # CHECK: dclz $1, $2             # encoding: [0x58,0x22,0x5b,0x3c]
+        drotr $5, $10, 8         # CHECK: drotr $5, $10, 8        # encoding: [0x58,0xaa,0x40,0xc0]
+        drotr32 $1, $2, 4        # CHECK: drotr32 $1, $2, 4       # encoding: [0x58,0x22,0x20,0xc8]
+        drotrv $3, $6, $4        # CHECK: drotrv $3, $6, $4       # encoding: [0x58,0xc4,0x18,0xd0]
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