[mips] MUL macro variations
Adds support for MUL macro variations.
Patch by: Srdjan Obucina
sdardis on Feb 2 2016, 8:28 AM.Authored by
In original test example there is one more instruction
dmul $4, $5, $6
However, there is a DMUL instruction in TD files, available only for Cavium Octeon, with predicate [HasCnMips], so I am getting "error: instruction requires a CPU feature not currently enabled" when I try to process this instruction.
I need advice on how to handle this situation. One solution is to define new DMUL pseudo instruction for everything but CnMips. Existing DMUL appears as a processor specific instruction, and not a general one, so I am wondering about naming conventions, should I leave existing DMUL as is, or rename it to reflect its nature.
Yes, adding a MipsAsmPseudoInst for the non-cnMIPS macro is the right way to go about it.
For the naming convention, instructions use the mnemonic as far as possible. A few instructions have conflicting definitions for the same mnemonic so these have a disambiguating suffix like '_R6', '_MM', or '_64'. For assembly macros, we've been moving towards using the mnemonic with a 'Macro' suffix (e.g. DMULMacro).
Those predicates look ok to me.
As future work, I think we might want to consider splitting InsnPredicates into a list of positive predicates and a list of negative predicates. Then we could use something like: