[mips] MUL macro variations

[sdardis]

Summary

[mips] MUL macro variations

Adds support for MUL macro variations.

Patch by: Srdjan Obucina

[obucina]

In original test example there is one more instruction

dmul $4, $5, $6

However, there is a DMUL instruction in TD files, available only for Cavium Octeon, with predicate [HasCnMips], so I am getting "error: instruction requires a CPU feature not currently enabled" when I try to process this instruction.

I need advice on how to handle this situation. One solution is to define new DMUL pseudo instruction for everything but CnMips. Existing DMUL appears as a processor specific instruction, and not a general one, so I am wondering about naming conventions, should I leave existing DMUL as is, or rename it to reflect its nature.

[dsanders]

In D16807#341755, @obucina wrote:

In original test example there is one more instruction

dmul $4, $5, $6

However, there is a DMUL instruction in TD files, available only for Cavium Octeon, with predicate [HasCnMips], so I am getting "error: instruction requires a CPU feature not currently enabled" when I try to process this instruction.

I need advice on how to handle this situation. One solution is to define new DMUL pseudo instruction for everything but CnMips. Existing DMUL appears as a processor specific instruction, and not a general one, so I am wondering about naming conventions, should I leave existing DMUL as is, or rename it to reflect its nature.

Yes, adding a MipsAsmPseudoInst for the non-cnMIPS macro is the right way to go about it.

For the naming convention, instructions use the mnemonic as far as possible. A few instructions have conflicting definitions for the same mnemonic so these have a disambiguating suffix like '_R6', '_MM', or '_64'. For assembly macros, we've been moving towards using the mnemonic with a 'Macro' suffix (e.g. DMULMacro).

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

3587–3590

Use the ternary operator

3607–3610

Likewise

3612–3615

Likewise

3617–3620

What happens when useTraps() is true? Shouldn't this use a trap instruction instead of a break

3637–3640

Use ternary operator

3643–3646

What happens when useTraps() is true? Shouldn't this use a trap instruction instead of a break

lib/Target/Mips/MipsInstrInfo.td

1814–1831

Naming convention as discussed above.

Also, AdditionalPredicates isn't the right predicate list for ISA predicates. Use the ISA_MIPS1_NOT_32R6_64R6 adjective instead.

1943

AdditionalPredicates isn't the right predicate list for ISA predicates. Use the ISA_MIPS1_NOT_32R6_64R6 adjective instead.

[obucina]

Changes according to the comments

[obucina]

Old file accidentally left in the patch - removed.

DMUL for non CnMips still missing.

[obucina]

Added DMUL macro for non CnMips. Please, take a look at the predicates of DMULMacro, and confirm are they OK.

[obucina]

Ping

[dsanders]

Added DMUL macro for non CnMips. Please, take a look at the predicates of DMULMacro, and confirm are they OK.

Those predicates look ok to me.

As future work, I think we might want to consider splitting InsnPredicates into a list of positive predicates and a list of negative predicates. Then we could use something like:
def ... : ..., ISA_MIPS64, ASE_NOT_CNMIPS.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

3587–3590

Sorry, this isn't quite what I meant. I should have been clearer.

Rather than a ternary operator with assignments inside it, I was looking for something like:

emitRR(Inst.getOpcode() == Mips::MULImm ? Mips::MULT : Mips::DMULT, SReg, ATReg, IDLoc, Instructions);

3607–3610

As above, this isn't quite what I meant.

3612–3615

As above, this isn't quite what I meant.

3622

I've just noticed that this isn't going to work for micromips because the offset is likely to be different for that case. If it's a constant offset then we can work around it for now (and leave a FIXME) but if it's variable then we'll need to find some way to do this.

For reference, my overall plan for solving this kind of problem is to finish rewriting the emit*() functions such that they directly write to the target streamer. This allows us to drop labels wherever we need them using the target streamer methods.

3637–3640

As above, this isn't quite what I meant.

3653

Similar to expandMulO(), this constant is different on micromips and might not be a constant.

3663

Indentation

lib/Target/Mips/MipsInstrInfo.td

1814–1831

MULImm and DMULImm should end in 'Macro' too

[obucina]

According to feedback - using ternary operators.

[obucina]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

3622

It is unclear to me what do you suggest regarding micromips potential problem with branch offset. Please be more precise.

3653

It is unclear to me what do you suggest regarding micromips potential problem with branch offset. Please be more precise.

[dsanders]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

3622

The offset needs to be different for microMIPS so you need to test for microMIPS and select between the MIPS and microMIPS value.
The way to fix this depends on whether the offset for the microMIPS case is a constant or is variable.

If the offset for the microMIPS case is a constant then we can use magic numbers for the moment (but please document them with comments). If the offset for the microMIPS case is variable for any reason then we'll have to find some way to account for the variability somehow (which could require the work explained at the bottom of this comment).

Ideally, we'd avoid any magic numbers using symbols and symbol references but it's not possible to do that right now (see below)

For reference, my overall plan for solving this kind of problem is to finish rewriting the emit*() functions such that they directly write to the
target streamer. This allows us to drop labels wherever we need them using the target streamer methods.

The reason we can't use symbols to avoid magic numbers at the moment is because this migration work is not yet complete. The problem is that we collect the expansion in a list of instructions and we can't put symbol definitions in this list. To eliminate the magic numbers we need to finish this work and use the target streamers as a stream. This will allow us to drop temporary symbols wherever we need them.

[seanbruno]

This review seems to have aged out and needs the last comments addressed and a refresh to latest trunk.

[sdardis]

Taking over this patch.

[sdardis]

Updated to trunk, addressed outstanding comment on directly specified branch operands vs. usage of label operands and labels.

[sdardis]

Removed some unnecessary symbol manipulation.

[seanbruno]

hrm ... I guess I can't "approve" this patch or something.

[sdardis]

It requires @dsanders to accept the revision as he's requested changes previously.

[dsanders]

In D16807#667692, @sdardis wrote:

It requires @dsanders to accept the revision as he's requested changes previously.

That must be a new requirement of phabricator. Marked as approved to let it change the overall state.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

#include "MipsGenAsmMatcher.inc"
   bool expandDRotation(MCInst &Inst, SMLoc IDLoc,
                        SmallVectorImpl<MCInst> &Instructions);
   bool expandDRotationImm(MCInst &Inst, SMLoc IDLoc,
                           SmallVectorImpl<MCInst> &Instructions);
 
   bool expandAbs(MCInst &Inst, SMLoc IDLoc,
                  SmallVectorImpl<MCInst> &Instructions);
 
+  bool expandMulImm(MCInst &Inst, SMLoc IDLoc,
+                    SmallVectorImpl<MCInst> &Instructions);
+  bool expandMulO(MCInst &Inst, SMLoc IDLoc,
+                  SmallVectorImpl<MCInst> &Instructions);
+  bool expandMulOU(MCInst &Inst, SMLoc IDLoc,
+                   SmallVectorImpl<MCInst> &Instructions);
+
   void createNop(bool hasShortDelaySlot, SMLoc IDLoc,
                  SmallVectorImpl<MCInst> &Instructions);
 
   void createAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg,
                   bool Is64Bit, SmallVectorImpl<MCInst> &Instructions);
 
   void createCpRestoreMemOp(bool IsLoad, int StackOffset, SMLoc IDLoc,
                             SmallVectorImpl<MCInst> &Instructions);
return expandDRotation(Inst, IDLoc, Instructions) ? MER_Fail
                                                       : MER_Success;
   case Mips::DROLImm:
   case Mips::DRORImm:
     return expandDRotationImm(Inst, IDLoc, Instructions) ? MER_Fail
                                                          : MER_Success;
   case Mips::ABSMacro:
     return expandAbs(Inst, IDLoc, Instructions) ? MER_Fail
                                                 : MER_Success;
+  case Mips::MULImm:
+  case Mips::DMULImm:
+    return expandMulImm(Inst, IDLoc, Instructions) ? MER_Fail
+                                                   : MER_Success;
+  case Mips::MULOMacro:
+  case Mips::DMULOMacro:
+    return expandMulO(Inst, IDLoc, Instructions) ? MER_Fail
+                                                 : MER_Success;
+  case Mips::MULOUMacro:
+  case Mips::DMULOUMacro:
+    return expandMulOU(Inst, IDLoc, Instructions) ? MER_Fail
+                                                  : MER_Success;
   }
 }
 
 bool MipsAsmParser::expandJalWithRegs(MCInst &Inst, SMLoc IDLoc,
                                       SmallVectorImpl<MCInst> &Instructions) {
   // Create a JALR instruction which is going to replace the pseudo-JAL.
   MCInst JalrInst;
   JalrInst.setLoc(IDLoc);
if (FirstRegOp != SecondRegOp)
     emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, Instructions);
   else
     createNop(false, IDLoc, Instructions);
   emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, Instructions);
 
   return false;
 }
 
+bool MipsAsmParser::expandMulImm(MCInst &Inst, SMLoc IDLoc,
+                                 SmallVectorImpl<MCInst> &Instructions) {
+  unsigned ATReg = Mips::NoRegister;
+  unsigned DReg = Inst.getOperand(0).getReg();
+  unsigned SReg = Inst.getOperand(1).getReg();
+  int32_t ImmValue = Inst.getOperand(2).getImm();
+
+  ATReg = getATReg(Inst.getLoc());
+  if (!ATReg)
+    return true;
+
+  loadImmediate(ImmValue, ATReg, Mips::NoRegister, true, false, Inst.getLoc(), Instructions);
+
+  unsigned Opcode = Mips::NOP;
+  (Inst.getOpcode() == Mips::MULImm) ? Opcode = Mips::MULT : Opcode = Mips::DMULT;
+  emitRR(Opcode, SReg, ATReg, IDLoc, Instructions);
+
+  emitR(Mips::MFLO, DReg, IDLoc, Instructions);
+
+  return false;
+}
+
+bool MipsAsmParser::expandMulO(MCInst &Inst, SMLoc IDLoc,
+                               SmallVectorImpl<MCInst> &Instructions) {
+  unsigned ATReg = Mips::NoRegister;
+  unsigned DReg = Inst.getOperand(0).getReg();
+  unsigned SReg = Inst.getOperand(1).getReg();
+  unsigned TReg = Inst.getOperand(2).getReg();
+
+  ATReg = getATReg(Inst.getLoc());
+  if (!ATReg)
+    return true;
+
+  unsigned Opcode = Mips::NOP;
+
+  (Inst.getOpcode() == Mips::MULOMacro) ? Opcode = Mips::MULT : Opcode = Mips::DMULT;
+  emitRR(Opcode, SReg, TReg, IDLoc, Instructions);
+
+  emitR(Mips::MFLO, DReg, IDLoc, Instructions);
+
+  (Inst.getOpcode() == Mips::MULOMacro) ? Opcode = Mips::SRA : Opcode = Mips::DSRA32;
+  emitRRI(Opcode, DReg, DReg, 0x1F, IDLoc, Instructions);
+
+  emitR(Mips::MFHI, ATReg, IDLoc, Instructions);
+  if (useTraps()) {
+    emitRRI(Mips::TNE, DReg, ATReg, 6, IDLoc, Instructions);
+  } else {
+    emitRRI(Mips::BEQ, DReg, ATReg, 8, IDLoc, Instructions);
+    if (AssemblerOptions.back()->isReorder())
+      createNop(false, IDLoc, Instructions);
+    emitII(Mips::BREAK,6, 0, IDLoc, Instructions);
+  }
+  emitR(Mips::MFLO, DReg, IDLoc, Instructions);
+
+  return false;
+}
+
+bool MipsAsmParser::expandMulOU(MCInst &Inst, SMLoc IDLoc,
+                                SmallVectorImpl<MCInst> &Instructions) {
+  unsigned ATReg = Mips::NoRegister;
+  unsigned DReg = Inst.getOperand(0).getReg();
+  unsigned SReg = Inst.getOperand(1).getReg();
+  unsigned TReg = Inst.getOperand(2).getReg();
+
+  ATReg = getATReg(Inst.getLoc());
+  if (!ATReg)
+    return true;
+
+  unsigned Opcode = Mips::NOP;
+
+  (Inst.getOpcode() == Mips::MULOUMacro) ? Opcode = Mips::MULTu : Opcode = Mips::DMULTu; 
+  emitRR(Opcode, SReg, TReg, IDLoc, Instructions);
+
+  emitR(Mips::MFHI, ATReg, IDLoc, Instructions);
+  emitR(Mips::MFLO, DReg, IDLoc, Instructions);
+  if (useTraps()) {
+    emitRRI(Mips::TNE, ATReg, Mips::ZERO, 6, IDLoc, Instructions);
+  } else {
+    emitRRI(Mips::BEQ, ATReg, Mips::ZERO, 8, IDLoc, Instructions);
+    if (AssemblerOptions.back()->isReorder())
+      createNop(false, IDLoc, Instructions);
+    emitII(Mips::BREAK, 6, 0, IDLoc, Instructions);
+  }
+
+  return false;
+}
+
 void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc,
                               SmallVectorImpl<MCInst> &Instructions) {
   if (hasShortDelaySlot)
     emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, Instructions);
   else
     emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, Instructions);
 }
 
 void MipsAsmParser::createAddu(unsigned DstReg, unsigned SrcReg,
                                unsigned TrgReg, bool Is64Bit,

lib/Target/Mips/MipsInstrInfo.td

 def : MipsInstAlias<"dror $rd, $rs",
                     (DROR GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>, ISA_MIPS64;
 def : MipsInstAlias<"dror $rd, $imm",
                     (DRORImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>, ISA_MIPS64;
 
 def ABSMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
                                  "abs\t$rd, $rs">;
 
+def MULImm : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs, simm16:$imm),
+                               "mul\t$rd, $rs, $imm">;
+def MULOMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs, GPR32Opnd:$rt),
+                                  "mulo\t$rd, $rs, $rt">, ISA_MIPS1_NOT_32R6_64R6;
+def MULOUMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs, GPR32Opnd:$rt),
+                                   "mulou\t$rd, $rs, $rt">, ISA_MIPS1_NOT_32R6_64R6;
+
+def DMULImm : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
+                                "dmul\t$rs, $rt, $imm">, ISA_MIPS1_NOT_32R6_64R6;
+def DMULOMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd),
+                                   "dmulo\t$rs, $rt, $rd">, ISA_MIPS1_NOT_32R6_64R6;
+def DMULOUMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd),
+                                    "dmulou\t$rs, $rt, $rd">, ISA_MIPS1_NOT_32R6_64R6;
+
 //===----------------------------------------------------------------------===//
 // Instruction aliases
 //===----------------------------------------------------------------------===//
 def : MipsInstAlias<"move $dst, $src",
                     (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
       GPR_32 {
   let AdditionalPredicates = [NotInMicroMips];
 }
 def : MipsInstAlias<"move $dst, $src",
                     (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
       GPR_32 {
   let AdditionalPredicates = [NotInMicroMips];
def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
                                              InvertedImOperand:$imm), 0>;
 def : MipsInstAlias<"sra $rd, $rt, $rs",
                     (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
 def : MipsInstAlias<"srl $rd, $rt, $rs",
                     (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
 def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
 def : MipsInstAlias<"sync",
                     (SYNC 0), 1>, ISA_MIPS2;
+
+def : MipsInstAlias<"mulo $rs, $rt",
+                    (MULOMacro GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>, 
+                    ISA_MIPS1_NOT_32R6_64R6;
+def : MipsInstAlias<"mulou $rs, $rt",
+                    (MULOUMacro GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>,
+                    ISA_MIPS1_NOT_32R6_64R6;
+
 //===----------------------------------------------------------------------===//
 // Assembler Pseudo Instructions
 //===----------------------------------------------------------------------===//
 
 class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> :
   MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
                      !strconcat(instr_asm, "\t$rt, $imm32")> ;
 def LoadImm32 : LoadImmediate32<"li", simm32, GPR32Opnd>;

test/MC/Mips/mul-macro-variations.s

+# RUN: llvm-mc  %s -triple mips-unknown-linux -show-encoding -mcpu=mips64 | FileCheck %s
+# RUN: llvm-mc  %s -triple mips-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s
+# RUN: llvm-mc  %s -triple mips-unknown-linux -show-encoding -mcpu=mips64r3 | FileCheck %s
+# RUN: llvm-mc  %s -triple mips-unknown-linux -show-encoding -mcpu=mips64r5 | FileCheck %s
+
+# RUN: llvm-mc  %s -triple mips-unknown-linux -show-encoding -mattr=use-tcc-in-div -mcpu=mips64 | FileCheck %s --check-prefix=CHECK-TRAP
+# RUN: llvm-mc  %s -triple mips-unknown-linux -show-encoding -mattr=use-tcc-in-div -mcpu=mips64r2 | FileCheck %s --check-prefix=CHECK-TRAP
+# RUN: llvm-mc  %s -triple mips-unknown-linux -show-encoding -mattr=use-tcc-in-div -mcpu=mips64r3 | FileCheck %s --check-prefix=CHECK-TRAP
+# RUN: llvm-mc  %s -triple mips-unknown-linux -show-encoding -mattr=use-tcc-in-div -mcpu=mips64r5 | FileCheck %s --check-prefix=CHECK-TRAP
+
+.text
+text_label:
+
+  mul $4, $5
+# CHECK:        mul     $4, $4, $5              # encoding: [0x70,0x85,0x20,0x02]
+# CHECK-TRAP:   mul     $4, $4, $5              # encoding: [0x70,0x85,0x20,0x02]
+  mul   $4, $5, $6
+# CHECK:        mul     $4, $5, $6              # encoding: [0x70,0xa6,0x20,0x02]
+# CHECK-TRAP:   mul     $4, $5, $6              # encoding: [0x70,0xa6,0x20,0x02]
+  mul $4, $5, 0
+# CHECK:        addiu   $1, $zero, 0            # encoding: [0x24,0x01,0x00,0x00]
+# CHECK:        mult    $5, $1                  # encoding: [0x00,0xa1,0x00,0x18]
+# CHECK:        mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+# CHECK-TRAP:   addiu   $1, $zero, 0            # encoding: [0x24,0x01,0x00,0x00]
+# CHECK-TRAP:   mult    $5, $1                  # encoding: [0x00,0xa1,0x00,0x18]
+# CHECK-TRAP:   mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+  mul   $4, $5, 1
+# CHECK:        addiu   $1, $zero, 1            # encoding: [0x24,0x01,0x00,0x01]
+# CHECK:        mult    $5, $1                  # encoding: [0x00,0xa1,0x00,0x18]
+# CHECK:        mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+# CHECK-TRAP:   addiu   $1, $zero, 1            # encoding: [0x24,0x01,0x00,0x01]
+# CHECK-TRAP:   mult    $5, $1                  # encoding: [0x00,0xa1,0x00,0x18]
+# CHECK-TRAP:   mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+  mul $4, $5, 0x8000
+# CHECK:        ori     $1, $zero, 32768        # encoding: [0x34,0x01,0x80,0x00]
+# CHECK:        mult    $5, $1                  # encoding: [0x00,0xa1,0x00,0x18]
+# CHECK:        mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+# CHECK-TRAP:   ori     $1, $zero, 32768        # encoding: [0x34,0x01,0x80,0x00]
+# CHECK-TRAP:   mult    $5, $1                  # encoding: [0x00,0xa1,0x00,0x18]
+# CHECK-TRAP:   mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+  mul $4, $5, -0x8000
+# CHECK:        addiu   $1, $zero, -32768       # encoding: [0x24,0x01,0x80,0x00]
+# CHECK:        mult    $5, $1                  # encoding: [0x00,0xa1,0x00,0x18]
+# CHECK:        mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+# CHECK-TRAP:   addiu   $1, $zero, -32768       # encoding: [0x24,0x01,0x80,0x00]
+# CHECK-TRAP:   mult    $5, $1                  # encoding: [0x00,0xa1,0x00,0x18]
+# CHECK-TRAP:   mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+  mul $4, $5, 0x10000
+# CHECK:        lui     $1, 1                   # encoding: [0x3c,0x01,0x00,0x01]
+# CHECK:        mult    $5, $1                  # encoding: [0x00,0xa1,0x00,0x18]
+# CHECK:        mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+# CHECK-TRAP:   lui     $1, 1                   # encoding: [0x3c,0x01,0x00,0x01]
+# CHECK-TRAP:   mult    $5, $1                  # encoding: [0x00,0xa1,0x00,0x18]
+# CHECK-TRAP:   mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+  mul $4, $5, 0x1a5a5
+# CHECK:        lui     $1, 1                   # encoding: [0x3c,0x01,0x00,0x01]
+# CHECK:        ori     $1, $1, 42405           # encoding: [0x34,0x21,0xa5,0xa5]
+# CHECK:        mult    $5, $1                  # encoding: [0x00,0xa1,0x00,0x18]
+# CHECK:        mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+# CHECK-TRAP:   lui     $1, 1                   # encoding: [0x3c,0x01,0x00,0x01]
+# CHECK-TRAP:   ori     $1, $1, 42405           # encoding: [0x34,0x21,0xa5,0xa5]
+# CHECK-TRAP:   mult    $5, $1                  # encoding: [0x00,0xa1,0x00,0x18]
+# CHECK-TRAP:   mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+  mulo  $4, $5
+# CHECK:        mult    $4, $5                  # encoding: [0x00,0x85,0x00,0x18]
+# CHECK:        mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+# CHECK:        sra     $4, $4, 31              # encoding: [0x00,0x04,0x27,0xc3]
+# CHECK:        mfhi    $1                      # encoding: [0x00,0x00,0x08,0x10]
+# CHECK:        beq     $4, $1, 8               # encoding: [0x10,0x81,0x00,0x02]
+# CHECK:        nop                             # encoding: [0x00,0x00,0x00,0x00]
+# CHECK:        break   6                       # encoding: [0x00,0x06,0x00,0x0d]
+# CHECK:        mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+# CHECK-TRAP:   mult    $4, $5                  # encoding: [0x00,0x85,0x00,0x18]
+# CHECK-TRAP:   mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+# CHECK-TRAP:   sra     $4, $4, 31              # encoding: [0x00,0x04,0x27,0xc3]
+# CHECK-TRAP:   mfhi    $1                      # encoding: [0x00,0x00,0x08,0x10]
+# CHECK-TRAP:   tne     $4, $1, 6               # encoding: [0x00,0x81,0x01,0xb6]
+# CHECK-TRAP:   mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+
+  mulo  $4, $5, $6
+# CHECK:        mult    $5, $6                  # encoding: [0x00,0xa6,0x00,0x18]
+# CHECK:        mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+# CHECK:        sra     $4, $4, 31              # encoding: [0x00,0x04,0x27,0xc3]
+# CHECK:        mfhi    $1                      # encoding: [0x00,0x00,0x08,0x10]
+# CHECK:        beq     $4, $1, 8               # encoding: [0x10,0x81,0x00,0x02]
+# CHECK:        nop                             # encoding: [0x00,0x00,0x00,0x00]
+# CHECK:        break   6                       # encoding: [0x00,0x06,0x00,0x0d]
+# CHECK:        mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+# CHECK-TRAP:   mult    $5, $6                  # encoding: [0x00,0xa6,0x00,0x18]
+# CHECK-TRAP:   mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+# CHECK-TRAP:   sra     $4, $4, 31              # encoding: [0x00,0x04,0x27,0xc3]
+# CHECK-TRAP:   mfhi    $1                      # encoding: [0x00,0x00,0x08,0x10]
+# CHECK-TRAP:   tne     $4, $1, 6               # encoding: [0x00,0x81,0x01,0xb6]
+# CHECK-TRAP:   mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+ mulou  $4,$5
+# CHECK:        multu   $4, $5                  # encoding: [0x00,0x85,0x00,0x19]
+# CHECK:        mfhi    $1                      # encoding: [0x00,0x00,0x08,0x10]
+# CHECK:        mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+# CHECK:        beqz    $1, 8                   # encoding: [0x10,0x20,0x00,0x02]
+# CHECK:        nop                             # encoding: [0x00,0x00,0x00,0x00]
+# CHECK:        break   6                       # encoding: [0x00,0x06,0x00,0x0d]
+# CHECK-TRAP:   multu   $4, $5                  # encoding: [0x00,0x85,0x00,0x19]
+# CHECK-TRAP:   mfhi    $1                      # encoding: [0x00,0x00,0x08,0x10]
+# CHECK-TRAP:   mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+# CHECK-TRAP:   tne     $1, $zero, 6            # encoding: [0x00,0x20,0x01,0xb6]
+ mulou $4, $5, $6
+# CHECK:        multu   $5, $6                  # encoding: [0x00,0xa6,0x00,0x19]
+# CHECK:        mfhi    $1                      # encoding: [0x00,0x00,0x08,0x10]
+# CHECK:        mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+# CHECK:        beqz    $1, 8                   # encoding: [0x10,0x20,0x00,0x02]
+# CHECK:        nop                             # encoding: [0x00,0x00,0x00,0x00]
+# CHECK:        break   6                       # encoding: [0x00,0x06,0x00,0x0d]
+# CHECK-TRAP:   multu   $5, $6                  # encoding: [0x00,0xa6,0x00,0x19]
+# CHECK-TRAP:   mfhi    $1                      # encoding: [0x00,0x00,0x08,0x10]
+# CHECK-TRAP:   mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+# CHECK-TRAP:   tne     $1, $zero, 6            # encoding: [0x00,0x20,0x01,0xb6]
+
+ dmul $4, $5, 1
+# CHECK:        addiu   $1, $zero, 1            # encoding: [0x24,0x01,0x00,0x01]
+# CHECK:        dmult   $5, $1                  # encoding: [0x00,0xa1,0x00,0x1c]
+# CHECK:        mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+# CHECK-TRAP:   addiu   $1, $zero, 1            # encoding: [0x24,0x01,0x00,0x01]
+# CHECK-TRAP:   dmult   $5, $1                  # encoding: [0x00,0xa1,0x00,0x1c]
+# CHECK-TRAP:   mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+ dmulo $4, $5, $6
+# CHECK:        dmult   $5, $6                  # encoding: [0x00,0xa6,0x00,0x1c]
+# CHECK:        mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+# CHECK:        dsra32  $4, $4, 31              # encoding: [0x00,0x04,0x27,0xff]
+# CHECK:        mfhi    $1                      # encoding: [0x00,0x00,0x08,0x10]
+# CHECK:        beq     $4, $1, 8               # encoding: [0x10,0x81,0x00,0x02]
+# CHECK:        nop                             # encoding: [0x00,0x00,0x00,0x00]
+# CHECK:        break   6                       # encoding: [0x00,0x06,0x00,0x0d]
+# CHECK:        mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+# CHECK-TRAP:   dmult   $5, $6                  # encoding: [0x00,0xa6,0x00,0x1c]
+# CHECK-TRAP:   mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+# CHECK-TRAP:   dsra32  $4, $4, 31              # encoding: [0x00,0x04,0x27,0xff]
+# CHECK-TRAP:   mfhi    $1                      # encoding: [0x00,0x00,0x08,0x10]
+# CHECK-TRAP:   tne     $4, $1, 6               # encoding: [0x00,0x81,0x01,0xb6]
+# CHECK-TRAP:   mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+ dmulou $4,$5,$6
+# CHECK:        dmultu  $5, $6                  # encoding: [0x00,0xa6,0x00,0x1d]
+# CHECK:        mfhi    $1                      # encoding: [0x00,0x00,0x08,0x10]
+# CHECK:        mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+# CHECK:        beqz    $1, 8                   # encoding: [0x10,0x20,0x00,0x02]
+# CHECK:        nop                             # encoding: [0x00,0x00,0x00,0x00]
+# CHECK:        break   6                       # encoding: [0x00,0x06,0x00,0x0d]
+# CHECK-TRAP:   dmultu  $5, $6                  # encoding: [0x00,0xa6,0x00,0x1d]
+# CHECK-TRAP:   mfhi    $1                      # encoding: [0x00,0x00,0x08,0x10]
+# CHECK-TRAP:   mflo    $4                      # encoding: [0x00,0x00,0x20,0x12]
+# CHECK-TRAP:   tne     $1, $zero, 6            # encoding: [0x00,0x20,0x01,0xb6]