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Differential D159204

[InstCombine] Baseline tests for folding (A/-B)==(A/B) to (A/B)==0
Needs ReviewPublic

Authored by marcauberer on Aug 30 2023, 7:10 AM.

Details

Reviewers
nikic
spatel
goldstein.w.n
lebedev.ri
sebastian-ne
greened
Summary

Baseline tests for: https://reviews.llvm.org/D159203

Diff Detail

Event Timeline

marcauberer created this revision.Aug 30 2023, 7:10 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 30 2023, 7:10 AM
Herald added a subscriber: StephenFan. · View Herald Transcript
marcauberer requested review of this revision.Aug 30 2023, 7:10 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 30 2023, 7:10 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
marcauberer updated this revision to Diff 554707.Aug 30 2023, 7:13 AM

Update link to code rev

marcauberer edited the summary of this revision. (Show Details)Aug 30 2023, 7:14 AM
marcauberer mentioned this in D159203: [InstCombine] Fold (A/-B)==(A/B) to (A/B)==0.
marcauberer updated this revision to Diff 554716.Aug 30 2023, 7:33 AM

Rebased

goldstein.w.n added a subscriber: goldstein.w.n.Aug 30 2023, 12:09 PM

Can you make this and the impl a series. You do that with the Edit Related Revisions button and set this one as the child of the impl patch.

marcauberer added a parent revision: D159203: [InstCombine] Fold (A/-B)==(A/B) to (A/B)==0.Aug 30 2023, 12:11 PM
marcauberer removed a parent revision: D159203: [InstCombine] Fold (A/-B)==(A/B) to (A/B)==0.Sep 1 2023, 1:07 PM
marcauberer added a child revision: D159203: [InstCombine] Fold (A/-B)==(A/B) to (A/B)==0.
marcauberer updated this revision to Diff 555494.Sep 1 2023, 1:25 PM

Rebase

marcauberer added reviewers: goldstein.w.n, lebedev.ri, sebastian-ne, greened.Sep 7 2023, 12:27 PM
marcauberer updated this revision to Diff 556304.Sep 8 2023, 2:50 PM

Use icmp eq instead of ne for precondition

Harbormaster completed remote builds in B256893: Diff 556304.Sep 8 2023, 4:10 PM
marcauberer updated this revision to Diff 556605.Sep 12 2023, 1:07 PM

Rebase

Harbormaster completed remote builds in B257102: Diff 556605.Sep 12 2023, 1:28 PM

Revision Contents

PathSize
llvm/
test/
Transforms/
InstCombine/
176 lines

Diff 554706

llvm/test/Transforms/InstCombine/icmp-sdiv-sdiv.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=instcombine -S | FileCheck %s
declare void @llvm.assume(i1)
declare void @use.i7(i7)
declare void @use.i14(i14)
define i1 @icmp_sdiv_sdiv_normal_i8(i8 %x, i8 %C) {
; CHECK-LABEL: @icmp_sdiv_sdiv_normal_i8(
; CHECK-NEXT: [[PRECOND:%.*]] = icmp ne i8 [[C:%.*]], -128
; CHECK-NEXT: call void @llvm.assume(i1 [[PRECOND]])
; CHECK-NEXT: [[NEGC:%.*]] = sub i8 0, [[C]]
; CHECK-NEXT: [[D1:%.*]] = sdiv i8 [[X:%.*]], [[NEGC]]
; CHECK-NEXT: [[D2:%.*]] = sdiv i8 [[X]], [[C]]
; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[D1]], [[D2]]
; CHECK-NEXT: ret i1 [[C]]
;
%precond = icmp ne i8 %C, -128
call void @llvm.assume(i1 %precond)
%negC = sub i8 0, %C
%d1 = sdiv i8 %x, %negC
%d2 = sdiv i8 %x, %C
%c = icmp eq i8 %d1, %d2
ret i1 %c
}
define i1 @icmp_sdiv_sdiv_normal_i64(i64 %x, i64 %C) {
; CHECK-LABEL: @icmp_sdiv_sdiv_normal_i64(
; CHECK-NEXT: [[PRECOND:%.*]] = icmp ne i64 [[C:%.*]], -9223372036854775808
; CHECK-NEXT: call void @llvm.assume(i1 [[PRECOND]])
; CHECK-NEXT: [[NEGC:%.*]] = sub i64 0, [[C]]
; CHECK-NEXT: [[D1:%.*]] = sdiv i64 [[X:%.*]], [[NEGC]]
; CHECK-NEXT: [[D2:%.*]] = sdiv i64 [[X]], [[C]]
; CHECK-NEXT: [[C:%.*]] = icmp eq i64 [[D1]], [[D2]]
; CHECK-NEXT: ret i1 [[C]]
;
%precond = icmp ne i64 %C, -9223372036854775808
call void @llvm.assume(i1 %precond)
%negC = sub i64 0, %C
%d1 = sdiv i64 %x, %negC
%d2 = sdiv i64 %x, %C
%c = icmp eq i64 %d1, %d2
ret i1 %c
}
define i1 @icmp_sdiv_sdiv_negative_no_precond(i17 %x, i17 %C) {
; CHECK-LABEL: @icmp_sdiv_sdiv_negative_no_precond(
; CHECK-NEXT: [[NEGC:%.*]] = sub i17 0, [[C:%.*]]
; CHECK-NEXT: [[D1:%.*]] = sdiv i17 [[X:%.*]], [[NEGC]]
; CHECK-NEXT: [[D2:%.*]] = sdiv i17 [[X]], [[C]]
; CHECK-NEXT: [[C:%.*]] = icmp eq i17 [[D1]], [[D2]]
; CHECK-NEXT: ret i1 [[C]]
;
%negC = sub i17 0, %C
%d1 = sdiv i17 %x, %negC
%d2 = sdiv i17 %x, %C
%c = icmp eq i17 %d1, %d2
ret i1 %c
}
define i1 @icmp_sdiv_sdiv_negative_precond_failure1(i24 %x, i24 %C) {
; CHECK-LABEL: @icmp_sdiv_sdiv_negative_precond_failure1(
; CHECK-NEXT: [[PRECOND:%.*]] = icmp ne i24 [[C:%.*]], -8388607
; CHECK-NEXT: call void @llvm.assume(i1 [[PRECOND]])
; CHECK-NEXT: [[NEGC:%.*]] = sub i24 0, [[C]]
; CHECK-NEXT: [[D1:%.*]] = sdiv i24 [[X:%.*]], [[NEGC]]
; CHECK-NEXT: [[D2:%.*]] = sdiv i24 [[X]], [[C]]
; CHECK-NEXT: [[C:%.*]] = icmp eq i24 [[D1]], [[D2]]
; CHECK-NEXT: ret i1 [[C]]
;
%precond = icmp ne i24 %C, -8388607 ; off by one
call void @llvm.assume(i1 %precond)
%negC = sub i24 0, %C
%d1 = sdiv i24 %x, %negC
%d2 = sdiv i24 %x, %C
%c = icmp eq i24 %d1, %d2
ret i1 %c
}
define i1 @icmp_sdiv_sdiv_negative_precond_failure2(i24 %x, i24 %C) {
; CHECK-LABEL: @icmp_sdiv_sdiv_negative_precond_failure2(
; CHECK-NEXT: [[PRECOND:%.*]] = icmp eq i24 [[C:%.*]], -8388608
; CHECK-NEXT: call void @llvm.assume(i1 [[PRECOND]])
; CHECK-NEXT: [[D1:%.*]] = sdiv i24 [[X:%.*]], [[C]]
; CHECK-NEXT: [[D2:%.*]] = sdiv i24 [[X]], [[C]]
; CHECK-NEXT: [[C:%.*]] = icmp eq i24 [[D1]], [[D2]]
; CHECK-NEXT: ret i1 [[C]]
;
%precond = icmp eq i24 %C, -8388608
call void @llvm.assume(i1 %precond)
%negC = sub i24 0, %C
%d1 = sdiv i24 %x, %negC
%d2 = sdiv i24 %x, %C
%c = icmp eq i24 %d1, %d2
ret i1 %c
}
define i1 @icmp_sdiv_sdiv_negative_icmp_ne(i6 %x, i6 %C) {
; CHECK-LABEL: @icmp_sdiv_sdiv_negative_icmp_ne(
; CHECK-NEXT: [[PRECOND:%.*]] = icmp ne i6 [[C:%.*]], -31
; CHECK-NEXT: call void @llvm.assume(i1 [[PRECOND]])
; CHECK-NEXT: [[NEGC:%.*]] = sub i6 0, [[C]]
; CHECK-NEXT: [[D1:%.*]] = sdiv i6 [[X:%.*]], [[NEGC]]
; CHECK-NEXT: [[D2:%.*]] = sdiv i6 [[X]], [[C]]
; CHECK-NEXT: [[C:%.*]] = icmp ne i6 [[D1]], [[D2]]
; CHECK-NEXT: ret i1 [[C]]
;
%precond = icmp ne i6 %C, -31
call void @llvm.assume(i1 %precond)
%negC = sub i6 0, %C
%d1 = sdiv i6 %x, %negC
%d2 = sdiv i6 %x, %C
%c = icmp ne i6 %d1, %d2
ret i1 %c
}
define i1 @icmp_sdiv_sdiv_negative_udiv(i9 %x, i9 %C) {
; CHECK-LABEL: @icmp_sdiv_sdiv_negative_udiv(
; CHECK-NEXT: [[PRECOND:%.*]] = icmp ne i9 [[C:%.*]], -256
; CHECK-NEXT: call void @llvm.assume(i1 [[PRECOND]])
; CHECK-NEXT: [[NEGC:%.*]] = sub i9 0, [[C]]
; CHECK-NEXT: [[D1:%.*]] = udiv i9 [[X:%.*]], [[NEGC]]
; CHECK-NEXT: [[D2:%.*]] = sdiv i9 [[X]], [[C]]
; CHECK-NEXT: [[C:%.*]] = icmp eq i9 [[D1]], [[D2]]
; CHECK-NEXT: ret i1 [[C]]
;
%precond = icmp ne i9 %C, -256
call void @llvm.assume(i1 %precond)
%negC = sub i9 0, %C
%d1 = udiv i9 %x, %negC
%d2 = sdiv i9 %x, %C
%c = icmp eq i9 %d1, %d2
ret i1 %c
}
define i1 @icmp_sdiv_sdiv_negative_multiple_uses_neg(i7 %x, i7 %C) {
; CHECK-LABEL: @icmp_sdiv_sdiv_negative_multiple_uses_neg(
; CHECK-NEXT: [[PRECOND:%.*]] = icmp ne i7 [[C:%.*]], -64
; CHECK-NEXT: call void @llvm.assume(i1 [[PRECOND]])
; CHECK-NEXT: [[NEGC:%.*]] = sub i7 0, [[C]]
; CHECK-NEXT: [[D1:%.*]] = sdiv i7 [[X:%.*]], [[NEGC]]
; CHECK-NEXT: [[D2:%.*]] = sdiv i7 [[X]], [[C]]
; CHECK-NEXT: [[C:%.*]] = icmp eq i7 [[D1]], [[D2]]
; CHECK-NEXT: call void @use.i7(i7 [[NEGC]])
; CHECK-NEXT: ret i1 [[C]]
;
%precond = icmp ne i7 %C, -64
call void @llvm.assume(i1 %precond)
%negC = sub i7 0, %C
%d1 = sdiv i7 %x, %negC
%d2 = sdiv i7 %x, %C
%c = icmp eq i7 %d1, %d2
call void @use.i7(i7 %negC)
ret i1 %c
}
define i1 @icmp_sdiv_sdiv_negative_multiple_uses_sdiv(i14 %x, i14 %C) {
; CHECK-LABEL: @icmp_sdiv_sdiv_negative_multiple_uses_sdiv(
; CHECK-NEXT: [[PRECOND:%.*]] = icmp ne i14 [[C:%.*]], -8192
; CHECK-NEXT: call void @llvm.assume(i1 [[PRECOND]])
; CHECK-NEXT: [[NEGC:%.*]] = sub i14 0, [[C]]
; CHECK-NEXT: [[D1:%.*]] = sdiv i14 [[X:%.*]], [[NEGC]]
; CHECK-NEXT: call void @use.i14(i14 [[D1]])
; CHECK-NEXT: [[D2:%.*]] = sdiv i14 [[X]], [[C]]
; CHECK-NEXT: [[C:%.*]] = icmp eq i14 [[D1]], [[D2]]
; CHECK-NEXT: ret i1 [[C]]
;
%precond = icmp ne i14 %C, -8192
call void @llvm.assume(i1 %precond)
%negC = sub i14 0, %C
%d1 = sdiv i14 %x, %negC
call void @use.i14(i14 %d1)
%d2 = sdiv i14 %x, %C
%c = icmp eq i14 %d1, %d2
ret i1 %c
}