[PowerPC] Implement SchedModel for Power7

[qiucf]

Summary

This patch implements the resource based SchedModel for Power7 CPU. Only the autogenerated cases are updated in this revision.

[shchenz]

llvm/lib/Target/PowerPC/PPCScheduleP7.td

33

What rules do we take to add unsupported features here? I believe we are missing lots of CPU features defined in PPC.td.

51

I checked P7_bookIV version 2.1, in sections 4.1.3, it says there is only 1 VMX unit:

One VMX execution unit capable of executing simple FX, complex FX, permute and 4-way SIMD single-precision FP ops

 Twelve execution units
– Two symmetric load/store units (LSU), also capable of executing simple fixed-point ops
– Two symmetric fixed-point units (FXU)
– Four floating-point units (FPU), implemented as two 2-way SIMD operations for double- and
single-precision. Scalar binary floating point instructions can only use two FPUs.
– One VMX execution unit capable of executing simple FX, complex FX, permute and 4-way SIMD
single-precision FP ops
– One decimal floating-point unit (DFU)
– 1 Branch execution unit (BR)
– 1 CR Logical execution unit (CRL)

60

use meaningful names please.

64

Out of order issue of up to 8 operations into the following 8 issue ports
– Two load or store operations
– Two fixed-point operations
– Two issue ports shared by two floating-point, two VSX, two VMX and one DFP ops
– One branch operation
– One condition register operation

218

hmm, in the above version, I see latency info for vsx scalar instructions.

[qiucf]

• Update VSX instructions according to new version UM
• Rename issue ports
• Add IsISA2_07 to unsupported features
• VMX has only one port

[shchenz]

LGTM with a small fix in one LIT.

I assume 1: you fixed all the LIT failures except the auto generated cases(the summary of the patch needs update). 2: you checked that the performance impact of this patch is positive for -mcpu=pwr7.

llvm/lib/Target/PowerPC/PPCScheduleP7.td

33

hmm, OK, let use this setting for now. I think we may need a similar approach in SystemZ arch. That's more clear and robust.

llvm/test/CodeGen/PowerPC/aix-vector-stack-caller.ll

85

Fix the broken case.

[qiucf]

In D158704#4644830, @shchenz wrote:

LGTM with a small fix in one LIT.

I assume 1: you fixed all the LIT failures except the auto generated cases(the summary of the patch needs update). 2: you checked that the performance impact of this patch is positive for -mcpu=pwr7.

Sure.

llvm/lib/Target/PowerPC/PPCScheduleP7.td

 //===-- PPCScheduleP7.td - PPC P7 Scheduling Definitions ---*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
-// This file defines the itinerary class data for the POWER7 processor.
+// This file defines the SchedModel for the POWER7 processor.
 //
 //===----------------------------------------------------------------------===//
 
-// Primary reference:
-// IBM POWER7 multicore server processor
-// B. Sinharoy, et al.
-// IBM J. Res. & Dev. (55) 3. May/June 2011.
-
-// Scheduling for the P7 involves tracking two types of resources:
-//  1. The dispatch bundle slots
-//  2. The functional unit resources
-
-// Dispatch units:
-def P7_DU1    : FuncUnit;
-def P7_DU2    : FuncUnit;
-def P7_DU3    : FuncUnit;
-def P7_DU4    : FuncUnit;
-def P7_DU5    : FuncUnit;
-def P7_DU6    : FuncUnit;
-
-def P7_LS1    : FuncUnit; // Load/Store pipeline 1
-def P7_LS2    : FuncUnit; // Load/Store pipeline 2
-
-def P7_FX1    : FuncUnit; // FX pipeline 1
-def P7_FX2    : FuncUnit; // FX pipeline 2
-
-// VS pipeline 1 (vector integer ops. always here)
-def P7_VS1    : FuncUnit; // VS pipeline 1
-// VS pipeline 2 (128-bit stores and perms. here)
-def P7_VS2    : FuncUnit; // VS pipeline 2
-
-def P7_CRU    : FuncUnit; // CR unit (CR logicals and move-from-SPRs)
-def P7_BRU    : FuncUnit; // BR unit
-
-// Notes:
-// Each LSU pipeline can also execute FX add and logical instructions.
-// Each LSU pipeline can complete a load or store in one cycle.
-//
-// Each store is broken into two parts, AGEN goes to the LSU while a
-// "data steering" op. goes to the FXU or VSU.
-//
-// FX loads have a two cycle load-to-use latency (so one "bubble" cycle).
-// VSU loads have a three cycle load-to-use latency (so two "bubble" cycle).
-//
-// Frequent FX ops. take only one cycle and results can be used again in the
-// next cycle (there is a self-bypass). Getting results from the other FX
-// pipeline takes an additional cycle.
-//
-// The VSU XS is similar to the POWER6, but with a pipeline length of 2 cycles
-// (instead of 3 cycles on the POWER6). VSU XS handles vector FX-style ops.
-// Dispatch of an instruction to VS1 that uses four single prec. inputs
-// (either to a float or XC op). prevents dispatch in that cycle to VS2 of any
-// floating point instruction.
-//
-// The VSU PM is similar to the POWER6, but with a pipeline length of 3 cycles
-// (instead of 4 cycles on the POWER6). vsel is handled by the PM pipeline
-// (unlike on the POWER6).
-//
-// FMA from the VSUs can forward results in 6 cycles. VS1 XS and vector FP
-// share the same write-back, and have a 5-cycle latency difference, so the
-// IFU/IDU will not dispatch an XS instructon 5 cycles after a vector FP
-// op. has been dispatched to VS1.
-//
-// Three cycles after an L1 cache hit, a dependent VSU instruction can issue.
-//
-// Instruction dispatch groups have (at most) four non-branch instructions, and
-// two branches. Unlike on the POWER4/5, a branch does not automatically
-// end the dispatch group, but a second branch must be the last in the group.
-
-def P7Itineraries : ProcessorItineraries<
-  [P7_DU1, P7_DU2, P7_DU3, P7_DU4, P7_DU5, P7_DU6,
-   P7_LS1, P7_LS2, P7_FX1, P7_FX2, P7_VS1, P7_VS2, P7_CRU, P7_BRU], [], [
-  InstrItinData<IIC_IntSimple   , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2,
-                                                  P7_LS1, P7_LS2]>],
-                                  [1, 1, 1]>,
-  InstrItinData<IIC_IntGeneral  , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                  [1, 1, 1]>,
-  InstrItinData<IIC_IntISEL,      [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2], 0>,
-                                   InstrStage<1, [P7_BRU]>],
-                                  [1, 1, 1, 1]>,
-  InstrItinData<IIC_IntCompare  , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                  [1, 1, 1]>,
-  // FIXME: Add record-form itinerary data.
-  InstrItinData<IIC_IntDivW     , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_DU2], 0>,
-                                   InstrStage<36, [P7_FX1, P7_FX2]>],
-                                  [36, 1, 1]>,
-  InstrItinData<IIC_IntDivD     , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_DU2], 0>,
-                                   InstrStage<68, [P7_FX1, P7_FX2]>],
-                                  [68, 1, 1]>,
-  InstrItinData<IIC_IntMulHW    , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                  [4, 1, 1]>,
-  InstrItinData<IIC_IntMulHWU   , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                  [4, 1, 1]>,
-  InstrItinData<IIC_IntMulHD    , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                  [4, 1, 1]>,
-  InstrItinData<IIC_IntMulLI    , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                  [4, 1, 1]>,
-  InstrItinData<IIC_IntRotate   , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                   [1, 1, 1]>,
-  InstrItinData<IIC_IntRotateD  , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                   [1, 1, 1]>,
-  InstrItinData<IIC_IntRotateDI , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                   [1, 1, 1]>,
-  InstrItinData<IIC_IntShift    , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                  [1, 1, 1]>,
-  InstrItinData<IIC_IntTrapW    , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                  [1, 1]>,
-  InstrItinData<IIC_IntTrapD    , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                  [1, 1]>,
-  InstrItinData<IIC_BrB         , [InstrStage<1, [P7_DU5, P7_DU6], 0>,
-                                   InstrStage<1, [P7_BRU]>],
-                                  [3, 1, 1]>,
-  InstrItinData<IIC_BrCR        , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_CRU]>],
-                                  [3, 1, 1]>,
-  InstrItinData<IIC_BrMCR       , [InstrStage<1, [P7_DU5, P7_DU6], 0>,
-                                   InstrStage<1, [P7_BRU]>],
-                                  [3, 1, 1]>,
-  InstrItinData<IIC_BrMCRX      , [InstrStage<1, [P7_DU5, P7_DU6], 0>,
-                                   InstrStage<1, [P7_BRU]>],
-                                  [3, 1, 1]>,
-  InstrItinData<IIC_LdStLoad    , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_LS1, P7_LS2]>],
-                                  [2, 1, 1]>,
-  InstrItinData<IIC_LdStLoadUpd , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_DU2], 0>,
-                                   InstrStage<1, [P7_LS1, P7_LS2], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                  [2, 2, 1, 1]>,
-  InstrItinData<IIC_LdStLoadUpdX, [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_DU2], 0>,
-                                   InstrStage<1, [P7_DU3], 0>,
-                                   InstrStage<1, [P7_DU4], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>,
-                                   InstrStage<1, [P7_LS1, P7_LS2], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                  [3, 3, 1, 1]>,
-  InstrItinData<IIC_LdStLD      , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_LS1, P7_LS2]>],
-                                  [2, 1, 1]>,
-  InstrItinData<IIC_LdStLDU     , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_DU2], 0>,
-                                   InstrStage<1, [P7_LS1, P7_LS2], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                  [2, 2, 1, 1]>,
-  InstrItinData<IIC_LdStLDUX    , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_DU2], 0>,
-                                   InstrStage<1, [P7_DU3], 0>,
-                                   InstrStage<1, [P7_DU4], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>,
-                                   InstrStage<1, [P7_LS1, P7_LS2], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                  [3, 3, 1, 1]>,
-  InstrItinData<IIC_LdStLFD     , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_LS1, P7_LS2]>],
-                                  [3, 1, 1]>,
-  InstrItinData<IIC_LdStLVecX   , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_LS1, P7_LS2]>],
-                                  [3, 1, 1]>,
-  InstrItinData<IIC_LdStLFDU    , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_DU2], 0>,
-                                   InstrStage<1, [P7_LS1, P7_LS2], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                  [3, 3, 1, 1]>,
-  InstrItinData<IIC_LdStLFDUX   , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_DU2], 0>,
-                                   InstrStage<1, [P7_LS1, P7_LS2], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                  [3, 3, 1, 1]>,
-  InstrItinData<IIC_LdStLHA     , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_DU2], 0>,
-                                   InstrStage<1, [P7_LS1, P7_LS2]>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                  [3, 1, 1]>,
-  InstrItinData<IIC_LdStLHAU    , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_DU2], 0>,
-                                   InstrStage<1, [P7_LS1, P7_LS2], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                  [4, 4, 1, 1]>,
-  InstrItinData<IIC_LdStLHAUX   , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_DU2], 0>,
-                                   InstrStage<1, [P7_DU3], 0>,
-                                   InstrStage<1, [P7_DU4], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>,
-                                   InstrStage<1, [P7_LS1, P7_LS2], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                  [4, 4, 1, 1]>,
-  InstrItinData<IIC_LdStLWA     , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_DU2], 0>,
-                                   InstrStage<1, [P7_LS1, P7_LS2]>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                  [3, 1, 1]>,
-  InstrItinData<IIC_LdStLWARX,    [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_DU2], 0>,
-                                   InstrStage<1, [P7_DU3], 0>,
-                                   InstrStage<1, [P7_DU4], 0>,
-                                   InstrStage<1, [P7_LS1, P7_LS2]>],
-                                  [3, 1, 1]>,
-  InstrItinData<IIC_LdStLDARX,    [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_DU2], 0>,
-                                   InstrStage<1, [P7_DU3], 0>,
-                                   InstrStage<1, [P7_DU4], 0>,
-                                   InstrStage<1, [P7_LS1, P7_LS2]>],
-                                  [3, 1, 1]>,
-  InstrItinData<IIC_LdStLMW     , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_LS1, P7_LS2]>],
-                                  [2, 1, 1]>,
-  InstrItinData<IIC_LdStStore   , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_LS1, P7_LS2], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                  [1, 1, 1]>,
-  InstrItinData<IIC_LdStSTD     , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_LS1, P7_LS2], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                  [1, 1, 1]>,
-  InstrItinData<IIC_LdStSTU     , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_DU2], 0>,
-                                   InstrStage<1, [P7_LS1, P7_LS2], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                  [2, 1, 1, 1]>,
-  InstrItinData<IIC_LdStSTUX    , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_DU2], 0>,
-                                   InstrStage<1, [P7_DU3], 0>,
-                                   InstrStage<1, [P7_DU4], 0>,
-                                   InstrStage<1, [P7_LS1, P7_LS2], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                  [2, 1, 1, 1]>,
-  InstrItinData<IIC_LdStSTFD    , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_LS1, P7_LS2], 0>,
-                                   InstrStage<1, [P7_VS1, P7_VS2]>],
-                                  [1, 1, 1]>,
-  InstrItinData<IIC_LdStSTFDU   , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_DU2], 0>,
-                                   InstrStage<1, [P7_LS1, P7_LS2], 0>,
-                                   InstrStage<1, [P7_FX1, P7_FX2], 0>,
-                                   InstrStage<1, [P7_VS1, P7_VS2]>],
-                                  [2, 1, 1, 1]>,
-  InstrItinData<IIC_LdStSTVEBX  , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_LS1, P7_LS2], 0>,
-                                   InstrStage<1, [P7_VS2]>],
-                                  [1, 1, 1]>,
-  InstrItinData<IIC_LdStSTDCX   , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_DU2], 0>,
-                                   InstrStage<1, [P7_DU3], 0>,
-                                   InstrStage<1, [P7_DU4], 0>,
-                                   InstrStage<1, [P7_LS1, P7_LS2]>],
-                                  [1, 1, 1]>,
-  InstrItinData<IIC_LdStSTWCX   , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_DU2], 0>,
-                                   InstrStage<1, [P7_DU3], 0>,
-                                   InstrStage<1, [P7_DU4], 0>,
-                                   InstrStage<1, [P7_LS1, P7_LS2]>],
-                                  [1, 1, 1]>,
-  InstrItinData<IIC_BrMCRX      , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_DU2], 0>,
-                                   InstrStage<1, [P7_DU3], 0>,
-                                   InstrStage<1, [P7_DU4], 0>,
-                                   InstrStage<1, [P7_CRU]>,
-                                   InstrStage<1, [P7_FX1, P7_FX2]>],
-                                  [3, 1]>, // mtcr
-  InstrItinData<IIC_SprMFCR     , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_CRU]>],
-                                  [6, 1]>,
-  InstrItinData<IIC_SprMFCRF    , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_CRU]>],
-                                  [3, 1]>,
-  InstrItinData<IIC_SprMTSPR    , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_FX1]>],
-                                  [4, 1]>, // mtctr
-  InstrItinData<IIC_FPGeneral   , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_VS1, P7_VS2]>],
-                                  [5, 1, 1]>,
-  InstrItinData<IIC_FPAddSub    , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_VS1, P7_VS2]>],
-                                  [5, 1, 1]>,
-  InstrItinData<IIC_FPCompare   , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_VS1, P7_VS2]>],
-                                  [8, 1, 1]>,
-  InstrItinData<IIC_FPDivD      , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_VS1, P7_VS2]>],
-                                  [33, 1, 1]>,
-  InstrItinData<IIC_FPDivS      , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_VS1, P7_VS2]>],
-                                  [27, 1, 1]>,
-  InstrItinData<IIC_FPSqrtD     , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_VS1, P7_VS2]>],
-                                  [44, 1, 1]>,
-  InstrItinData<IIC_FPSqrtS     , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_VS1, P7_VS2]>],
-                                  [32, 1, 1]>,
-  InstrItinData<IIC_FPFused     , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_VS1, P7_VS2]>],
-                                  [5, 1, 1, 1]>,
-  InstrItinData<IIC_FPRes       , [InstrStage<1, [P7_DU1, P7_DU2,
-                                                  P7_DU3, P7_DU4], 0>,
-                                   InstrStage<1, [P7_VS1, P7_VS2]>],
-                                  [5, 1, 1]>,
-  InstrItinData<IIC_VecGeneral  , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_VS1]>],
-                                  [2, 1, 1]>,
-  InstrItinData<IIC_VecVSL      , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_VS1]>],
-                                  [2, 1, 1]>,
-  InstrItinData<IIC_VecVSR      , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_VS1]>],
-                                  [2, 1, 1]>,
-  InstrItinData<IIC_VecFP       , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_VS1, P7_VS2]>],
-                                  [6, 1, 1]>,
-  InstrItinData<IIC_VecFPCompare, [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_VS1, P7_VS2]>],
-                                  [6, 1, 1]>,
-  InstrItinData<IIC_VecFPRound  , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_VS1, P7_VS2]>],
-                                  [6, 1, 1]>,
-  InstrItinData<IIC_VecComplex  , [InstrStage<1, [P7_DU1], 0>,
-                                   InstrStage<1, [P7_VS1]>],
-                                  [7, 1, 1]>,
-  InstrItinData<IIC_VecPerm     , [InstrStage<1, [P7_DU1, P7_DU2], 0>,
-                                   InstrStage<1, [P7_VS2]>],
-                                  [3, 1, 1]>
-]>;
-
-// ===---------------------------------------------------------------------===//
-// P7 machine model for scheduling and other instruction cost heuristics.
-
 def P7Model : SchedMachineModel {
   let IssueWidth = 6;  // 4 (non-branch) instructions are dispatched per cycle.
                        // Note that the dispatch bundle size is 6 (including
                        // branches), but the total internal issue bandwidth per
                        // cycle (from all queues) is 8.
 
   let LoadLatency = 3; // Optimistic load latency assuming bypass.
                        // This is overriden by OperandCycles if the
                        // Itineraries are queried instead.
   let MispredictPenalty = 16;
 
+  let MicroOpBufferSize = 44;
+
   // Try to make sure we have at least 10 dispatch groups in a loop.
   let LoopMicroOpBufferSize = 40;
 
   let CompleteModel = 0;
 
-  let Itineraries = P7Itineraries;
+  let UnsupportedFeatures = [HasSPE, PrefixInstrs, MMA,
+                             PairedVectorMemops, IsISA3_0,
+                             PCRelativeMemops, IsISA3_1, IsISAFuture];
 }
 
+let SchedModel = P7Model in {
+  def P7_LSU_FXU: ProcResource<4>;
+  def P7_LSU: ProcResource<2> {
+    let Super = P7_LSU_FXU;
+  }
+  def P7_FXU: ProcResource<2> {
+    let Super = P7_LSU_FXU;
+  }
+  // Implemented as two 2-way SIMD operations for double- and single-precision.
+  def P7_FPU: ProcResource<4>;
+  // Scalar binary floating point instructions can only use two FPUs.
+  def P7_ScalarFPU: ProcResource<2> {
+    let Super = P7_FPU;
+  }
+  // Executing simple FX, complex FX, permute and 4-way SIMD single-precision FP ops
+  def P7_VMX: ProcResource<2>;
+  def P7_VPM: ProcResource<2> {
+    let Super = P7_VMX;
+    let BufferSize = 1;
+  }
+  def P7_DFU: ProcResource<1>;
+  def P7_BRU: ProcResource<1>;
+  def P7_CRU: ProcResource<1>;
+
+  def P7_PORT_1 : ProcResource<2>;
+  def P7_PORT_2 : ProcResource<2>;
+  def P7_PORT_3 : ProcResource<2>;
+  def P7_PORT_4 : ProcResource<1>;
+  def P7_PORT_5 : ProcResource<1>;
+
+  def P7_DISP_LS : SchedWriteRes<[P7_PORT_1]>;
+  def P7_DISP_FX : SchedWriteRes<[P7_PORT_2]>;
+  def P7_DISP_FP : SchedWriteRes<[P7_PORT_3]>;
+  def P7_DISP_BR : SchedWriteRes<[P7_PORT_4]>;
+  def P7_DISP_CR : SchedWriteRes<[P7_PORT_5]>;
+
+  def P7_NONE_0C : SchedWriteRes<[]> { let Latency = 0; }
+  def P7_BRU_1C : SchedWriteRes<[P7_BRU]>;
+  def P7_BRU_3C : SchedWriteRes<[P7_BRU]> { let Latency = 3; }
+  def P7_BRU_4C : SchedWriteRes<[P7_BRU]> { let Latency = 4; }
+  def P7_CRU_3C : SchedWriteRes<[P7_CRU]> { let Latency = 3; }
+  def P7_CRU_6C : SchedWriteRes<[P7_CRU]> { let Latency = 6; }
+  def P7_LSU_1C : SchedWriteRes<[P7_LSU]> { let Latency = 1; }
+  def P7_LSU_2C : SchedWriteRes<[P7_LSU]> { let Latency = 2; }
+  def P7_LSU_3C : SchedWriteRes<[P7_LSU]> { let Latency = 3; }
+  def P7_LSU_4C : SchedWriteRes<[P7_LSU]> { let Latency = 4; }
+  def P7_FXU_1C : SchedWriteRes<[P7_FXU]> { let Latency = 1; }
+  def P7_FXU_2C : SchedWriteRes<[P7_FXU]> { let Latency = 2; }
+  def P7_FXU_3C : SchedWriteRes<[P7_FXU]> { let Latency = 3; }
+  def P7_FXU_4C : SchedWriteRes<[P7_FXU]> { let Latency = 4; }
+  def P7_FXU_5C : SchedWriteRes<[P7_FXU]> { let Latency = 5; }
+  def P7_FXU_38C : SchedWriteRes<[P7_FXU]> { let Latency = 38; }
+  def P7_FXU_69C : SchedWriteRes<[P7_FXU]> { let Latency = 69; }
+  def P7_LSU_FXU_2C : SchedWriteRes<[P7_LSU_FXU]> { let Latency = 2; }
+  def P7_FPU_6C : SchedWriteRes<[P7_FPU]> { let Latency = 6; }
+  def P7_ScalarFPU_6C : SchedWriteRes<[P7_ScalarFPU]> { let Latency = 6; }
+  def P7_ScalarFPU_8C : SchedWriteRes<[P7_ScalarFPU]> { let Latency = 8; }
+  def P7_ScalarFPU_27C : SchedWriteRes<[P7_ScalarFPU]> { let Latency = 27; }
+  def P7_ScalarFPU_32C : SchedWriteRes<[P7_ScalarFPU]> { let Latency = 32; }
+  def P7_ScalarFPU_33C : SchedWriteRes<[P7_ScalarFPU]> { let Latency = 33; }
+  def P7_ScalarFPU_44C : SchedWriteRes<[P7_ScalarFPU]> { let Latency = 44; }
+  def P7_VMX_6C : SchedWriteRes<[P7_VMX]> { let Latency = 6; }
+  def P7_VPM_6C : SchedWriteRes<[P7_VPM]> { let Latency = 6; }
+
+  def : InstRW<[P7_NONE_0C], (instrs
+    NOP, NOP_GT_PWR6, NOP_GT_PWR7
+  )>;
+
+  def : InstRW<[P7_BRU_1C, P7_DISP_BR], (instregex "^B(L)?(A)?(8)?(_NOP|_NOTOC)?(_TLS|_RM)?(_)?$")>;
+
+  def : InstRW<[P7_BRU_3C, P7_DISP_BR], (instrs
+    BDZLRLp, BDZLRm, BDZLRp, BDZLm, BDZLp, BDZm, BDZp,
+    BDNZ, BDNZ8, BDNZA, BDNZAm, BDNZAp, BDNZL, BDNZLA, BDNZLAm, BDNZLAp, BDNZLR,
+    BDNZLR8, BDNZLRL, BDNZLRLm, BDNZLRLp, BDNZLRm, BDNZLRp, BDNZLm, BDNZLp, BDNZm, BDNZp, BDZ,
+    BDZ8, BDZA, BDZAm, BDZAp, BDZL, BDZLA, BDZLAm, BDZLAp, BDZLR, BDZLR8, BDZLRL, BDZLRLm,
+    MFCTR, MFCTR8, MFLR, MFLR8,
+    BLR, BLR8, BLRL, BCL, BCLR, BCLRL, BCLRLn, BCLRn, BCLalways, BCLn, BCTR, BCTR8, BCTRL, BCTRL8, BCTRL8_LDinto_toc,
+    BCTRL8_LDinto_toc_RM, BCTRL8_RM, BCTRL_LWZinto_toc, BCTRL_LWZinto_toc_RM, BCTRL_RM, BCn, BC, BCC, BCCA,
+    BCCCTR, BCCCTR8, BCCCTRL, BCCCTRL8, BCCL, BCCLA, BCCLR, BCCLRL, BCCTR, BCCTR8, BCCTR8n, BCCTRL, BCCTRL8,
+    BCCTRL8n, BCCTRLn, BCCTRn, gBC, gBCA, gBCAat, gBCCTR, gBCCTRL, gBCL, gBCLA, gBCLAat, gBCLR, gBCLRL, gBCLat, gBCat
+  )>;
+
+  def : InstRW<[P7_BRU_4C], (instrs MTLR, MTLR8, MTCTR, MTCTR8, MTCTR8loop, MTCTRloop)>;
+
+  def : InstRW<[P7_CRU_3C], (instrs MCRF)>;
+
+  def : InstRW<[P7_CRU_6C, P7_DISP_CR], (instrs
+    CMPD, CMPDI, CMPLD, CMPLDI, CMPLW, CMPLWI, CMPW, CMPWI, COPY,
+    CR6SET, CR6UNSET, CRSET, CRUNSET,
+    CRAND, CRANDC, CREQV, CRNAND, CRNOR, CRNOT, CROR, CRORC
+  )>;
+
+  def : InstRW<[P7_LSU_2C, P7_DISP_LS], (instrs LHBRX, LHBRX8, LWBRX, LWBRX8)>;
+
+  def : InstRW<[P7_LSU_3C], (instrs MFSR, MFSRIN)>;
+
+  def : InstRW<[P7_LSU_4C, P7_FXU_4C, P7_DISP_LS], (instrs
+    LBARX, LBZCIX, LDBRX, LDCIX, LFD, LFDU, LFDUX, LFDX, LFIWAX, LFIWZX,
+    LFS, LFSU, LFSUX, LFSX, LHARX, LHZCIX, LSWI, LVEBX, LVEHX, LVEWX, LVSL,
+    LVSR, LVX, LVXL, LWZCIX, LXSDX, LXVD2X, LXVDSX, LXVW4X,
+    STFD, STFDU, STFDUX, STFDX, STFIWX, STFS, STFSU, STFSUX, STFSX,
+    STHCIX, STSWI, STVEBX, STVEHX, STVEWX, STVX, STVXL, STWCIX, STXSDX, STXVD2X, STXVW4X,
+    LHA, LHA8, LHAX, LHAX8, LWA, LWAX, LWAX_32, LWA_32, LHAU, LHAU8, LHAUX, LHAUX8, LWAUX
+  )>;
+
+  def : InstRW<[P7_LSU_2C, P7_FXU_2C, P7_DISP_LS], (instrs
+    LWZU, LWZU8, LHZU, LHZU8, LBZU, LBZU8, LDU,
+    LWZUX, LWZUX8, LHZUX, LHZUX8, LBZUX, LBZUX8, LDUX
+  )>;
+
+  def : InstRW<[P7_LSU_1C, P7_FXU_1C, P7_DISP_LS], (instrs
+    STB, STB8, STH, STH8, STW, STW8, STD,
+    STBX, STBX8, STHX, STHX8, STWX, STWX8, STDX,
+    STHBRX, STWBRX, STMW, STWCX, STDCX, STDU, STHU, STHU8, STBU, STBU8, STWU, STWU8,
+    STDUX, STWUX, STWUX8, STHUX, STHUX8, STBUX, STBUX8
+  )>;
+
+  def : InstRW<[P7_LSU_1C, P7_DISP_LS], (instrs LMW, LWARX, LWARXL, LDARX, LDARXL)>;
+
+  def : InstRW<[P7_LSU_FXU_2C, P7_DISP_FX], (instrs
+    (instregex "^(ADD|L)I(S)?(8)?$"),
+    (instregex "^(ADD|SUBF)(4|8)(TLS)?(_)?(_rec)?$"),
+    (instregex "^(X)?ORI(S)?(8)?$"),
+    (instregex "^(X)OR(8)?(_rec)?$"),
+    ADDIC, ADDIC8, SUBFIC, SUBFIC8, SUBFZE, SUBFZE8,
+    ADDE, ADDE8, ADDME, ADDME8, SUBFME, SUBFME8,
+    NEG, NEG8, NEG8_rec, NEG_rec, NEG8O, NEGO,
+    ANDI_rec, ANDIS_rec, AND, AND8, AND_rec, AND8_rec,
+    NAND, NAND8, NAND_rec, NAND8_rec, NOR, NOR8, NOR_rec, NOR8_rec,
+    EQV, EQV8, EQV_rec, EQV8_rec, ANDC, ANDC8, ANDC_rec, ANDC8_rec,
+    ORC, ORC8, ORC_rec, ORC8_rec
+  )>;
+
+  def : InstRW<[P7_FXU_2C, P7_DISP_FX], (instrs
+    EXTSB8_32_64, EXTSB8_rec, EXTSH8_32_64, EXTSH8_rec, EXTSW_32, EXTSW_32_64, EXTSW_32_64_rec,
+    POPCNTB, POPCNTB8, POPCNTD, POPCNTW,
+    ADDPCIS, ANDI8_rec, ANDIS8_rec,
+    SUBFUS, SUBFUS_rec,
+    ADD4O, ADD8O, ADDC, ADDC8, SUBFO, SUBF8O, SUBFC, SUBFC8,
+    ADDIC_rec, ADDE8_rec, ADDE_rec, SUBFE8_rec, SUBFE_rec,
+    ADDME8_rec, ADDME_rec, SUBFME8_rec, SUBFME_rec, ADDZE8_rec, ADDZE_rec,
+    SUBFZE_rec, SUBFZE8_rec, ADD8O_rec, SUBFO_rec, SUBF8O_rec, ADD4O_rec,
+    ADDEO, ADDE8O, SUBFEO, SUBFE8O, ADDMEO, SUBFMEO, SUBFME8O, ADDME8O,
+    ADDZEO, ADDZE8O, SUBFZEO, SUBFZE8O, NEG8O_rec, NEGO_rec,
+    ADDE8O_rec, ADDEO_rec, ADDMEO_rec, ADDME8O_rec, SUBFMEO_rec, SUBFME8O_rec,
+    ADDZEO_rec, ADDZE8O_rec, SUBFZEO_rec, SUBFZE8O_rec,
+    ADDC8_rec, ADDC_rec, ADDCO, ADDCO_rec, ADDC8O, ADDC8O_rec,
+    SUBFC8_rec, SUBFC_rec, SUBFCO, SUBFC8O,  SUBFCO_rec, SUBFC8O_rec,
+    EXTSB, EXTSB8, EXTSB_rec, EXTSH, EXTSH8, EXTSH_rec, EXTSW, EXTSW_rec,
+    RLDICL, RLDICL_rec, RLDICR, RLDICR_rec, RLDIC, RLDIC_rec,
+    RLWINM, RLWINM8, RLWINM_rec, RLDCL, RLDCL_rec, RLDCR, RLDCR_rec,
+    RLWNM, RLWNM8, RLWNM_rec, RLDIMI, RLDIMI_rec,
+    RLDICL_32, RLDICL_32_64, RLDICL_32_rec, RLDICR_32, RLWINM8_rec, RLWNM8_rec,
+    SLD, SLD_rec, SLW, SLW8, SLW_rec, SLW8_rec, SRD, SRD_rec, SRW, SRW8, SRW_rec, SRW8_rec,
+    SRADI, SRADI_rec, SRAWI, SRAWI_rec, SRAD, SRAD_rec, SRAW, SRAW_rec, SRADI_32,
+    SUBFE, SUBFE8, SUBFE8O_rec, SUBFEO_rec
+  )>;
+
+  def : InstRW<[P7_VPM_6C, P7_DISP_FP], (instrs
+    VPERM,
+    XXMRGHW, XXMRGLW, XXPERMDI, XXPERMDIs, XXSLDWI, XXSLDWIs,
+    VSPLTB, VSPLTBs, VSPLTH, VSPLTHs, VSPLTISB, VSPLTISH, VSPLTISW, VSPLTW, XXSPLTW, XXSPLTWs,
+    VSEL, XXSEL,
+    VPKSHSS, VPKSHUS, VPKSWSS, VPKSWUS, VPKUHUM, VPKUHUS, VPKUWUM, VPKUWUS, VPKPX,
+    VUPKHPX, VUPKHSB, VUPKHSH, VUPKLPX, VUPKLSB, VUPKLSH
+  )>;
+
+  def : InstRW<[P7_VMX_6C, P7_DISP_FP], (instrs
+    (instregex "^VADD(U|S)(B|H|W)(S|M)$"),
+    (instregex "^V(MAX|MIN)(S|U)(B|H|W)$"),
+    (instregex "^V(MRG)(L|H)(B|H|W)$"),
+    XXLORf, XXLXORdpz, XXLXORspz, XXLXORz,
+    XVRSQRTESP, XVRESP, XVSQRTSP, XVTDIVSP, XVTSQRTSP,
+    XVCMPEQSP, XVCMPEQSP_rec, XVCMPGESP, XVCMPGESP_rec, XVCMPGTSP, XVCMPGTSP_rec,
+    XVCVSXDSP, XVCVSXWSP, XVCVUXDSP, XVCVUXWSP, XVDIVSP, XVCPSGNSP, XVCVDPSP,
+    VADDCUW, VADDFP,
+    VAND, VANDC, VAVGSB, VAVGSH, VAVGSW, VAVGUB, VAVGUH, VAVGUW, VCFSX, VCFUX,
+    VCMPBFP, VCMPBFP_rec, VCMPEQFP, VCMPEQFP_rec, VCMPEQUB, VCMPEQUB_rec, VCMPEQUH, VCMPEQUH_rec,
+    VCMPEQUW, VCMPEQUW_rec, VCMPGEFP, VCMPGEFP_rec, VCMPGTFP, VCMPGTFP_rec, VCMPGTSB, VCMPGTSB_rec,
+    VCMPGTSH, VCMPGTSH_rec, VCMPGTSW, VCMPGTSW_rec, VCMPGTUB, VCMPGTUB_rec, VCMPGTUH, VCMPGTUH_rec,
+    VCMPGTUW, VCMPGTUW_rec,
+    VCTSXS, VCTUXS, VEXPTEFP, VLOGEFP, VNOR, VOR,
+    VMADDFP, VMHADDSHS, VMHRADDSHS, VMLADDUHM, VNMSUBFP,
+    VMAXFP, VMINFP,
+    VMSUMMBM, VMSUMSHM, VMSUMSHS, VMSUMUBM, VMSUMUDM, VMSUMUHM, VMSUMUHS,
+    VMULESB, VMULESH, VMULEUB, VMULEUH, VMULOSB, VMULOSH, VMULOUB, VMULOUH,
+    VREFP, VRFIM, VRFIN, VRFIP, VRFIZ, VRLB, VRLH, VRLW, VRSQRTEFP,
+    VSR, VSRAB, VSRAH, VSRAW,
+    VSRB, VSRH, VSRO, VSRW, VSUBCUW, VSL, VSLB, VSLDOI, VSLH, VSLO, VSLW,
+    VSUBFP, VSUBSBS, VSUBSHS, VSUBSWS, VSUBUBM, VSUBUBS, VSUBUHM, VSUBUHS, VSUBUWM, VSUBUWS,
+    VSUM2SWS, VSUM4SBS, VSUM4SHS, VSUM4UBS, VSUMSWS, VXOR,
+    XXLAND, XXLANDC, XXLNOR, XXLOR, XXLXOR
+  )>;
+
+  def : InstRW<[P7_FPU_6C, P7_DISP_FP], (instrs
+    XVCMPEQDP, XVCMPEQDP_rec, XVCMPGEDP, XVCMPGEDP_rec, XVCMPGTDP, XVCMPGTDP_rec,
+    XVCPSGNDP, XVCVDPSXDS, XVCVDPSXWS, XVCVDPUXDS, XVCVDPUXWS, XVCVSPSXDS, XVCVSPSXWS,
+    XVCVSPUXDS, XVCVSPUXWS, XVCVSXDDP, XVCVSXWDP, XVCVUXDDP, XVCVUXWDP, XVDIVDP,
+    XVRDPI, XVRDPIC, XVRDPIM, XVRDPIP, XVRDPIZ, XVREDP, XVRSPI, XVRSPIC, XVRSPIM, XVRSPIP, XVRSPIZ,
+    XVRSQRTEDP, XVSQRTDP, XVTDIVDP, XVTSQRTDP
+  )>;
+
+  def : InstRW<[P7_FXU_3C, P7_DISP_FX], (instrs
+    CNTLZDM, CNTLZW8_rec, CNTTZD, CNTTZDM, CNTTZD_rec, CNTTZW, CNTTZW8, CNTTZW8_rec, CNTTZW_rec,
+    CNTLZD, CNTLZD_rec, CNTLZW, CNTLZW8, CNTLZW_rec
+  )>;
+
+  def : InstRW<[P7_FXU_5C, P7_DISP_FX], (instrs
+    MULLI, MULLI8, MULLW, MULHW, MULHWU, MULLD, MULHD, MULHDU, MULLWO, MULLDO,
+    MULLW_rec, MULLD_rec, MULHD_rec, MULHW_rec, MULHDU_rec, MULHWU_rec, MULLWO_rec, MULLDO_rec
+  )>;
+
+  def : InstRW<[P7_FXU_38C, P7_DISP_FX], (instrs
+    DIVDE, DIVDEO, DIVDEO_rec, DIVDEU, DIVDEUO, DIVDEUO_rec, DIVDEU_rec, DIVDE_rec,
+    DIVWE, DIVWEO, DIVWEO_rec, DIVWEU, DIVWEUO, DIVWEUO_rec, DIVWEU_rec, DIVWE_rec,
+    DIVW, DIVWU, DIVWU_rec, DIVWO, DIVWO_rec, DIVWUO, DIVWUO_rec, DIVW_rec
+  )>;
+
+  def : InstRW<[P7_FXU_69C, P7_DISP_FX], (instrs
+    DIVD, DIVDU, DIVDO, DIVDO_rec, DIVDUO, DIVDUO_rec, DIVDU_rec, DIVD_rec
+  )>;
+
+  def : InstRW<[P7_ScalarFPU_6C, P7_DISP_FP], (instrs
+    FRE, FRES_rec, FRE_rec, FRSP_rec, FTDIV, FTSQRT,
+    FMR, FNEGD, FNEGS, FABSD, FABSS, FNABSD, FNABSS, FADD, FADDS, FSUB, FSUBS, FMUL, FMULS,
+    FMADD, FMADDS, FMSUB, FMSUBS, FNMADD, FNMADDS, FNMSUB, FNMSUBS,
+    FMADDS_rec, FMADD_rec, FMSUBS_rec, FMSUB_rec, FNMADDS_rec, FNMADD_rec, FNMSUBS_rec, FNMSUB_rec,
+    XSNEGDP, XSABSDP, XSNABSDP, XSNABSDPs, XSADDDP, XSADDSP, XSSUBDP, XSSUBSP, XSMULDP, XSMULSP,
+    XSMADDADP, XSMADDASP, XSMADDMDP, XSMADDMSP, XSMSUBADP, XSMSUBASP, XSMSUBMDP, XSMSUBMSP,
+    XSNMADDADP, XSNMADDASP, XSNMADDMDP, XSNMADDMSP, XSNMSUBADP, XSNMSUBASP, XSNMSUBMDP, XSNMSUBMSP,
+    FRSP, FRES, FRSQRTE, FRSQRTES, FRSQRTES_rec, FRSQRTE_rec,
+    FCTID, FCTIDU, FCTIDUZ, FCTIDZ, FCTIW, FCTIWU, FCTIWUZ, FCTIWZ, FCFID, FCFIDS, FCFIDU, FCFIDUS,
+    FSELD, FSELS, FSELD_rec, FSELS_rec, FABSD_rec, FABSS_rec, FNABSD_rec, FNABSS_rec,
+    FMR_rec, FMULS_rec, FMUL_rec, FNEGD_rec, FNEGS_rec, FADDS_rec, FADD_rec, FSUBS_rec, FSUB_rec,
+    FCFIDS_rec, FCFIDUS_rec, FCFIDU_rec, FCFID_rec, FCTIDUZ_rec, FCTIDU_rec, FCTIDZ_rec, FCTID_rec,
+    FCTIWUZ_rec, FCTIWU_rec, FCTIWZ_rec, FCTIW_rec,
+    FCPSGND, FCPSGND_rec, FCPSGNS, FCPSGNS_rec,
+    FRIMD, FRIMD_rec, FRIMS, FRIMS_rec, FRIND, FRIND_rec, FRINS, FRINS_rec,
+    FRIPD, FRIPD_rec, FRIPS, FRIPS_rec, FRIZD, FRIZD_rec, FRIZS, FRIZS_rec,
+    XSCPSGNDP, XSCVDPSP, XSCVDPSXDS, XSCVDPSXDSs, XSCVDPSXWS, XSCVDPSXWSs, XSCVDPUXDS, XSCVDPUXDSs,
+    XSCVDPUXWS, XSCVDPUXWSs, XSCVSPDP, XSCVSXDDP, XSCVUXDDP, XSMAXDP, XSMINDP, XSRDPI, XSRDPIC,
+    XSRDPIM, XSRDPIP, XSRDPIZ, XSREDP, XSRSQRTEDP,
+    XSTDIVDP,
+    XSTSQRTDP
+  )>;
+
+  def : InstRW<[P7_FPU_6C, P7_DISP_FP], (instrs
+    (instregex "^XV(N)?(M)?(ADD|SUB)(A|M)?(D|S)P$"),
+    XVMAXDP, XVMAXSP, XVMINDP, XVMINSP, XVMULDP, XVMULSP, XVNABSDP, XVNABSSP, XVNEGDP, XVNEGSP,
+    XVABSDP, XVABSSP, XVADDDP, XVADDSP
+  )>;
+
+  def : InstRW<[P7_ScalarFPU_8C, P7_DISP_FP], (instrs FCMPOD, FCMPOS, FCMPUD, FCMPUS, XSCMPODP, XSCMPUDP)>;
+  def : InstRW<[P7_ScalarFPU_27C, P7_DISP_FP], (instrs FDIVS, XSDIVSP, FDIVS_rec)>;
+  def : InstRW<[P7_ScalarFPU_32C, P7_DISP_FP], (instrs FSQRTS, XSSQRTSP, FSQRTS_rec)>;
+  def : InstRW<[P7_ScalarFPU_33C, P7_DISP_FP], (instrs FDIV, XSDIVDP, FDIV_rec)>;
+  def : InstRW<[P7_ScalarFPU_44C, P7_DISP_FP], (instrs FSQRT, XSSQRTDP, FSQRT_rec)>;
+}

llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll

 ; CHECK-NEXT:    mtlr 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: main:
 ; CHECK-P7:       # %bb.0: # %L.entry
 ; CHECK-P7-NEXT:    mflr 0
 ; CHECK-P7-NEXT:    stdu 1, -48(1)
 ; CHECK-P7-NEXT:    li 3, -32477
-; CHECK-P7-NEXT:    lis 5, 0
-; CHECK-P7-NEXT:    addi 4, 1, 46
-; CHECK-P7-NEXT:    li 7, 0
 ; CHECK-P7-NEXT:    std 0, 64(1)
-; CHECK-P7-NEXT:    sth 3, 46(1)
+; CHECK-P7-NEXT:    addi 4, 1, 46
 ; CHECK-P7-NEXT:    li 6, 234
-; CHECK-P7-NEXT:    rlwinm 3, 4, 3, 27, 27
-; CHECK-P7-NEXT:    ori 5, 5, 33059
-; CHECK-P7-NEXT:    ori 7, 7, 65535
+; CHECK-P7-NEXT:    sth 3, 46(1)
+; CHECK-P7-NEXT:    lis 3, 0
 ; CHECK-P7-NEXT:    sync
-; CHECK-P7-NEXT:    slw 6, 6, 3
-; CHECK-P7-NEXT:    slw 8, 5, 3
-; CHECK-P7-NEXT:    slw 5, 7, 3
+; CHECK-P7-NEXT:    ori 5, 3, 33059
+; CHECK-P7-NEXT:    rlwinm 3, 4, 3, 27, 27
 ; CHECK-P7-NEXT:    rldicr 4, 4, 0, 61
+; CHECK-P7-NEXT:    slw 7, 5, 3
+; CHECK-P7-NEXT:    li 5, 0
+; CHECK-P7-NEXT:    slw 6, 6, 3
+; CHECK-P7-NEXT:    ori 5, 5, 65535
+; CHECK-P7-NEXT:    slw 5, 5, 3
 ; CHECK-P7-NEXT:    and 6, 6, 5
-; CHECK-P7-NEXT:    and 7, 8, 5
+; CHECK-P7-NEXT:    and 7, 7, 5
 ; CHECK-P7-NEXT:  .LBB0_1: # %L.entry
 ; CHECK-P7-NEXT:    #
 ; CHECK-P7-NEXT:    lwarx 9, 0, 4
 ; CHECK-P7-NEXT:    and 8, 9, 5
 ; CHECK-P7-NEXT:    cmpw 8, 7
 ; CHECK-P7-NEXT:    bne 0, .LBB0_3
 ; CHECK-P7-NEXT:  # %bb.2: # %L.entry
 ; CHECK-P7-NEXT:    #

llvm/test/CodeGen/PowerPC/aix-lower-jump-table-mir.ll

define i32 @jump_table(i32 %a) {
   ; 32SMALL-MIR-NEXT:   renamable $r3 = ADDI killed renamable $r3, -1
   ; 32SMALL-MIR-NEXT:   renamable $cr0 = CMPLWI renamable $r3, 3
   ; 32SMALL-MIR-NEXT:   BCC 44, killed renamable $cr0, %bb.6
   ; 32SMALL-MIR-NEXT: {{  $}}
   ; 32SMALL-MIR-NEXT: bb.1.entry:
   ; 32SMALL-MIR-NEXT:   successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)
   ; 32SMALL-MIR-NEXT:   liveins: $r3
   ; 32SMALL-MIR-NEXT: {{  $}}
-  ; 32SMALL-MIR-NEXT:   renamable $r4 = LWZtoc %jump-table.0, $r2 :: (load (s32) from got)
   ; 32SMALL-MIR-NEXT:   renamable $r3 = RLWINM killed renamable $r3, 2, 0, 29
+  ; 32SMALL-MIR-NEXT:   renamable $r4 = LWZtoc %jump-table.0, $r2 :: (load (s32) from got)
   ; 32SMALL-MIR-NEXT:   renamable $r3 = LWZX killed renamable $r3, renamable $r4 :: (load (s32) from jump-table)
   ; 32SMALL-MIR-NEXT:   renamable $r3 = ADD4 killed renamable $r3, killed renamable $r4
   ; 32SMALL-MIR-NEXT:   MTCTR killed renamable $r3, implicit-def $ctr
   ; 32SMALL-MIR-NEXT:   BCTR implicit $ctr
   ; 32SMALL-MIR-NEXT: {{  $}}
   ; 32SMALL-MIR-NEXT: bb.2.sw.bb:
   ; 32SMALL-MIR-NEXT:   successors: %bb.6(0x80000000)
   ; 32SMALL-MIR-NEXT: {{  $}}
define i32 @jump_table(i32 %a) {
   ; 32LARGE-MIR-NEXT:   renamable $r3 = ADDI killed renamable $r3, -1
   ; 32LARGE-MIR-NEXT:   renamable $cr0 = CMPLWI renamable $r3, 3
   ; 32LARGE-MIR-NEXT:   BCC 44, killed renamable $cr0, %bb.6
   ; 32LARGE-MIR-NEXT: {{  $}}
   ; 32LARGE-MIR-NEXT: bb.1.entry:
   ; 32LARGE-MIR-NEXT:   successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)
   ; 32LARGE-MIR-NEXT:   liveins: $r3
   ; 32LARGE-MIR-NEXT: {{  $}}
+  ; 32LARGE-MIR-NEXT:   renamable $r3 = RLWINM killed renamable $r3, 2, 0, 29
   ; 32LARGE-MIR-NEXT:   renamable $r4 = ADDIStocHA $r2, %jump-table.0
   ; 32LARGE-MIR-NEXT:   renamable $r4 = LWZtocL %jump-table.0, killed renamable $r4, implicit $r2 :: (load (s32) from got)
-  ; 32LARGE-MIR-NEXT:   renamable $r3 = RLWINM killed renamable $r3, 2, 0, 29
   ; 32LARGE-MIR-NEXT:   renamable $r3 = LWZX killed renamable $r3, renamable $r4 :: (load (s32) from jump-table)
   ; 32LARGE-MIR-NEXT:   renamable $r3 = ADD4 killed renamable $r3, killed renamable $r4
   ; 32LARGE-MIR-NEXT:   MTCTR killed renamable $r3, implicit-def $ctr
   ; 32LARGE-MIR-NEXT:   BCTR implicit $ctr
   ; 32LARGE-MIR-NEXT: {{  $}}
   ; 32LARGE-MIR-NEXT: bb.2.sw.bb:
   ; 32LARGE-MIR-NEXT:   successors: %bb.6(0x80000000)
   ; 32LARGE-MIR-NEXT: {{  $}}
define i32 @jump_table(i32 %a) {
   ; 64SMALL-MIR-NEXT:   renamable $r3 = ADDI renamable $r3, -1, implicit killed $x3, implicit-def $x3
   ; 64SMALL-MIR-NEXT:   renamable $cr0 = CMPLWI renamable $r3, 3
   ; 64SMALL-MIR-NEXT:   BCC 44, killed renamable $cr0, %bb.6
   ; 64SMALL-MIR-NEXT: {{  $}}
   ; 64SMALL-MIR-NEXT: bb.1.entry:
   ; 64SMALL-MIR-NEXT:   successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)
   ; 64SMALL-MIR-NEXT:   liveins: $x3
   ; 64SMALL-MIR-NEXT: {{  $}}
-  ; 64SMALL-MIR-NEXT:   renamable $x4 = LDtocJTI %jump-table.0, $x2 :: (load (s64) from got)
   ; 64SMALL-MIR-NEXT:   renamable $x3 = RLDIC killed renamable $x3, 2, 30
+  ; 64SMALL-MIR-NEXT:   renamable $x4 = LDtocJTI %jump-table.0, $x2 :: (load (s64) from got)
   ; 64SMALL-MIR-NEXT:   renamable $x3 = LWAX killed renamable $x3, renamable $x4 :: (load (s32) from jump-table)
   ; 64SMALL-MIR-NEXT:   renamable $x3 = ADD8 killed renamable $x3, killed renamable $x4
   ; 64SMALL-MIR-NEXT:   MTCTR8 killed renamable $x3, implicit-def $ctr8
   ; 64SMALL-MIR-NEXT:   BCTR8 implicit $ctr8
   ; 64SMALL-MIR-NEXT: {{  $}}
   ; 64SMALL-MIR-NEXT: bb.2.sw.bb:
   ; 64SMALL-MIR-NEXT:   successors: %bb.6(0x80000000)
   ; 64SMALL-MIR-NEXT: {{  $}}
define i32 @jump_table(i32 %a) {
   ; 64LARGE-MIR-NEXT:   renamable $r3 = ADDI renamable $r3, -1, implicit killed $x3, implicit-def $x3
   ; 64LARGE-MIR-NEXT:   renamable $cr0 = CMPLWI renamable $r3, 3
   ; 64LARGE-MIR-NEXT:   BCC 44, killed renamable $cr0, %bb.6
   ; 64LARGE-MIR-NEXT: {{  $}}
   ; 64LARGE-MIR-NEXT: bb.1.entry:
   ; 64LARGE-MIR-NEXT:   successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)
   ; 64LARGE-MIR-NEXT:   liveins: $x3
   ; 64LARGE-MIR-NEXT: {{  $}}
+  ; 64LARGE-MIR-NEXT:   renamable $x3 = RLDIC killed renamable $x3, 2, 30
   ; 64LARGE-MIR-NEXT:   renamable $x4 = ADDIStocHA8 $x2, %jump-table.0
   ; 64LARGE-MIR-NEXT:   renamable $x4 = LDtocL %jump-table.0, killed renamable $x4, implicit $x2 :: (load (s64) from got)
-  ; 64LARGE-MIR-NEXT:   renamable $x3 = RLDIC killed renamable $x3, 2, 30
   ; 64LARGE-MIR-NEXT:   renamable $x3 = LWAX killed renamable $x3, renamable $x4 :: (load (s32) from jump-table)
   ; 64LARGE-MIR-NEXT:   renamable $x3 = ADD8 killed renamable $x3, killed renamable $x4
   ; 64LARGE-MIR-NEXT:   MTCTR8 killed renamable $x3, implicit-def $ctr8
   ; 64LARGE-MIR-NEXT:   BCTR8 implicit $ctr8
   ; 64LARGE-MIR-NEXT: {{  $}}
   ; 64LARGE-MIR-NEXT: bb.2.sw.bb:
   ; 64LARGE-MIR-NEXT:   successors: %bb.6(0x80000000)
   ; 64LARGE-MIR-NEXT: {{  $}}

llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-double.ll

   %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarUninit)
   %1 = load double, ptr %0, align 8
   ret double %1
 }
 
 define double @loadITLUninit2() {
 ; SMALL64-LABEL: loadITLUninit2:
 ; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C4(r2) # @VarInit
+; SMALL64-NEXT:    lfd f0, 0(r3)
 ; SMALL64-NEXT:    ld r3, L..C0(r2) # target-flags(ppc-tprel) @IThreadLocalVarUninit
-; SMALL64-NEXT:    ld r4, L..C4(r2) # @VarInit
-; SMALL64-NEXT:    lfdx f0, r13, r3
-; SMALL64-NEXT:    lfd f1, 0(r4)
-; SMALL64-NEXT:    xsadddp f1, f0, f1
+; SMALL64-NEXT:    lfdx f1, r13, r3
+; SMALL64-NEXT:    xsadddp f1, f1, f0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: loadITLUninit2:
 ; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C4@u(r2)
+; LARGE64-NEXT:    ld r3, L..C4@l(r3)
+; LARGE64-NEXT:    lfd f0, 0(r3)
 ; LARGE64-NEXT:    addis r3, L..C0@u(r2)
-; LARGE64-NEXT:    addis r4, L..C4@u(r2)
 ; LARGE64-NEXT:    ld r3, L..C0@l(r3)
-; LARGE64-NEXT:    ld r4, L..C4@l(r4)
-; LARGE64-NEXT:    lfdx f0, r13, r3
-; LARGE64-NEXT:    lfd f1, 0(r4)
-; LARGE64-NEXT:    xsadddp f1, f0, f1
+; LARGE64-NEXT:    lfdx f1, r13, r3
+; LARGE64-NEXT:    xsadddp f1, f1, f0
 ; LARGE64-NEXT:    blr
 ;
 ; SMALL32-LABEL: loadITLUninit2:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr r0
 ; SMALL32-NEXT:    stwu r1, -32(r1)
-; SMALL32-NEXT:    lwz r4, L..C0(r2) # target-flags(ppc-tprel) @IThreadLocalVarUninit
 ; SMALL32-NEXT:    lwz r5, L..C4(r2) # @VarInit
+; SMALL32-NEXT:    lwz r4, L..C0(r2) # target-flags(ppc-tprel) @IThreadLocalVarUninit
 ; SMALL32-NEXT:    stw r0, 40(r1)
 ; SMALL32-NEXT:    bla .__get_tpointer[PR]
-; SMALL32-NEXT:    lfdx f0, r3, r4
-; SMALL32-NEXT:    lfd f1, 0(r5)
-; SMALL32-NEXT:    xsadddp f1, f0, f1
+; SMALL32-NEXT:    lfd f0, 0(r5)
+; SMALL32-NEXT:    lfdx f1, r3, r4
+; SMALL32-NEXT:    xsadddp f1, f1, f0
 ; SMALL32-NEXT:    addi r1, r1, 32
 ; SMALL32-NEXT:    lwz r0, 8(r1)
 ; SMALL32-NEXT:    mtlr r0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: loadITLUninit2:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr r0

   %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarInit)
   %1 = load double, ptr %0, align 8
   ret double %1
 }
 
 define double @loadITLInit2() {
 ; SMALL64-LABEL: loadITLInit2:
 ; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C4(r2) # @VarInit
+; SMALL64-NEXT:    lfd f0, 0(r3)
 ; SMALL64-NEXT:    ld r3, L..C1(r2) # target-flags(ppc-tprel) @IThreadLocalVarInit
-; SMALL64-NEXT:    ld r4, L..C4(r2) # @VarInit
-; SMALL64-NEXT:    lfdx f0, r13, r3
-; SMALL64-NEXT:    lfd f1, 0(r4)
-; SMALL64-NEXT:    xsadddp f1, f0, f1
+; SMALL64-NEXT:    lfdx f1, r13, r3
+; SMALL64-NEXT:    xsadddp f1, f1, f0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: loadITLInit2:
 ; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C4@u(r2)
+; LARGE64-NEXT:    ld r3, L..C4@l(r3)
+; LARGE64-NEXT:    lfd f0, 0(r3)
 ; LARGE64-NEXT:    addis r3, L..C1@u(r2)
-; LARGE64-NEXT:    addis r4, L..C4@u(r2)
 ; LARGE64-NEXT:    ld r3, L..C1@l(r3)
-; LARGE64-NEXT:    ld r4, L..C4@l(r4)
-; LARGE64-NEXT:    lfdx f0, r13, r3
-; LARGE64-NEXT:    lfd f1, 0(r4)
-; LARGE64-NEXT:    xsadddp f1, f0, f1
+; LARGE64-NEXT:    lfdx f1, r13, r3
+; LARGE64-NEXT:    xsadddp f1, f1, f0
 ; LARGE64-NEXT:    blr
 ;
 ; SMALL32-LABEL: loadITLInit2:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr r0
 ; SMALL32-NEXT:    stwu r1, -32(r1)
-; SMALL32-NEXT:    lwz r4, L..C1(r2) # target-flags(ppc-tprel) @IThreadLocalVarInit
 ; SMALL32-NEXT:    lwz r5, L..C4(r2) # @VarInit
+; SMALL32-NEXT:    lwz r4, L..C1(r2) # target-flags(ppc-tprel) @IThreadLocalVarInit
 ; SMALL32-NEXT:    stw r0, 40(r1)
 ; SMALL32-NEXT:    bla .__get_tpointer[PR]
-; SMALL32-NEXT:    lfdx f0, r3, r4
-; SMALL32-NEXT:    lfd f1, 0(r5)
-; SMALL32-NEXT:    xsadddp f1, f0, f1
+; SMALL32-NEXT:    lfd f0, 0(r5)
+; SMALL32-NEXT:    lfdx f1, r3, r4
+; SMALL32-NEXT:    xsadddp f1, f1, f0
 ; SMALL32-NEXT:    addi r1, r1, 32
 ; SMALL32-NEXT:    lwz r0, 8(r1)
 ; SMALL32-NEXT:    mtlr r0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: loadITLInit2:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr r0

   %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @ThreadLocalVarUninit)
   %1 = load double, ptr %0, align 8
   ret double %1
 }
 
 define double @loadTLUninit2() {
 ; SMALL64-LABEL: loadTLUninit2:
 ; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C4(r2) # @VarInit
+; SMALL64-NEXT:    lfd f0, 0(r3)
 ; SMALL64-NEXT:    ld r3, L..C2(r2) # target-flags(ppc-tprel) @ThreadLocalVarUninit
-; SMALL64-NEXT:    ld r4, L..C4(r2) # @VarInit
-; SMALL64-NEXT:    lfdx f0, r13, r3
-; SMALL64-NEXT:    lfd f1, 0(r4)
-; SMALL64-NEXT:    xsadddp f1, f0, f1
+; SMALL64-NEXT:    lfdx f1, r13, r3
+; SMALL64-NEXT:    xsadddp f1, f1, f0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: loadTLUninit2:
 ; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C4@u(r2)
+; LARGE64-NEXT:    ld r3, L..C4@l(r3)
+; LARGE64-NEXT:    lfd f0, 0(r3)
 ; LARGE64-NEXT:    addis r3, L..C2@u(r2)
-; LARGE64-NEXT:    addis r4, L..C4@u(r2)
 ; LARGE64-NEXT:    ld r3, L..C2@l(r3)
-; LARGE64-NEXT:    ld r4, L..C4@l(r4)
-; LARGE64-NEXT:    lfdx f0, r13, r3
-; LARGE64-NEXT:    lfd f1, 0(r4)
-; LARGE64-NEXT:    xsadddp f1, f0, f1
+; LARGE64-NEXT:    lfdx f1, r13, r3
+; LARGE64-NEXT:    xsadddp f1, f1, f0
 ; LARGE64-NEXT:    blr
 ;
 ; SMALL32-LABEL: loadTLUninit2:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr r0
 ; SMALL32-NEXT:    stwu r1, -32(r1)
-; SMALL32-NEXT:    lwz r4, L..C2(r2) # target-flags(ppc-tprel) @ThreadLocalVarUninit
 ; SMALL32-NEXT:    lwz r5, L..C4(r2) # @VarInit
+; SMALL32-NEXT:    lwz r4, L..C2(r2) # target-flags(ppc-tprel) @ThreadLocalVarUninit
 ; SMALL32-NEXT:    stw r0, 40(r1)
 ; SMALL32-NEXT:    bla .__get_tpointer[PR]
-; SMALL32-NEXT:    lfdx f0, r3, r4
-; SMALL32-NEXT:    lfd f1, 0(r5)
-; SMALL32-NEXT:    xsadddp f1, f0, f1
+; SMALL32-NEXT:    lfd f0, 0(r5)
+; SMALL32-NEXT:    lfdx f1, r3, r4
+; SMALL32-NEXT:    xsadddp f1, f1, f0
 ; SMALL32-NEXT:    addi r1, r1, 32
 ; SMALL32-NEXT:    lwz r0, 8(r1)
 ; SMALL32-NEXT:    mtlr r0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: loadTLUninit2:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr r0

   %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @ThreadLocalVarInit)
   %1 = load double, ptr %0, align 8
   ret double %1
 }
 
 define double @loadTLInit2() {
 ; SMALL64-LABEL: loadTLInit2:
 ; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C4(r2) # @VarInit
+; SMALL64-NEXT:    lfd f0, 0(r3)
 ; SMALL64-NEXT:    ld r3, L..C3(r2) # target-flags(ppc-tprel) @ThreadLocalVarInit
-; SMALL64-NEXT:    ld r4, L..C4(r2) # @VarInit
-; SMALL64-NEXT:    lfdx f0, r13, r3
-; SMALL64-NEXT:    lfd f1, 0(r4)
-; SMALL64-NEXT:    xsadddp f1, f0, f1
+; SMALL64-NEXT:    lfdx f1, r13, r3
+; SMALL64-NEXT:    xsadddp f1, f1, f0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: loadTLInit2:
 ; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C4@u(r2)
+; LARGE64-NEXT:    ld r3, L..C4@l(r3)
+; LARGE64-NEXT:    lfd f0, 0(r3)
 ; LARGE64-NEXT:    addis r3, L..C3@u(r2)
-; LARGE64-NEXT:    addis r4, L..C4@u(r2)
 ; LARGE64-NEXT:    ld r3, L..C3@l(r3)
-; LARGE64-NEXT:    ld r4, L..C4@l(r4)
-; LARGE64-NEXT:    lfdx f0, r13, r3
-; LARGE64-NEXT:    lfd f1, 0(r4)
-; LARGE64-NEXT:    xsadddp f1, f0, f1
+; LARGE64-NEXT:    lfdx f1, r13, r3
+; LARGE64-NEXT:    xsadddp f1, f1, f0
 ; LARGE64-NEXT:    blr
 ;
 ; SMALL32-LABEL: loadTLInit2:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr r0
 ; SMALL32-NEXT:    stwu r1, -32(r1)
-; SMALL32-NEXT:    lwz r4, L..C3(r2) # target-flags(ppc-tprel) @ThreadLocalVarInit
 ; SMALL32-NEXT:    lwz r5, L..C4(r2) # @VarInit
+; SMALL32-NEXT:    lwz r4, L..C3(r2) # target-flags(ppc-tprel) @ThreadLocalVarInit
 ; SMALL32-NEXT:    stw r0, 40(r1)
 ; SMALL32-NEXT:    bla .__get_tpointer[PR]
-; SMALL32-NEXT:    lfdx f0, r3, r4
-; SMALL32-NEXT:    lfd f1, 0(r5)
-; SMALL32-NEXT:    xsadddp f1, f0, f1
+; SMALL32-NEXT:    lfd f0, 0(r5)
+; SMALL32-NEXT:    lfdx f1, r3, r4
+; SMALL32-NEXT:    xsadddp f1, f1, f0
 ; SMALL32-NEXT:    addi r1, r1, 32
 ; SMALL32-NEXT:    lwz r0, 8(r1)
 ; SMALL32-NEXT:    mtlr r0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: loadTLInit2:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr r0

llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-float.ll

   %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @IThreadLocalVarUninit)
   %1 = load float, ptr %0, align 4
   ret float %1
 }
 
 define float @loadITLUninit2() {
 ; SMALL64-LABEL: loadITLUninit2:
 ; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C4(r2) # @VarInit
+; SMALL64-NEXT:    lfs f0, 0(r3)
 ; SMALL64-NEXT:    ld r3, L..C0(r2) # target-flags(ppc-tprel) @IThreadLocalVarUninit
-; SMALL64-NEXT:    ld r4, L..C4(r2) # @VarInit
-; SMALL64-NEXT:    lfsx f0, r13, r3
-; SMALL64-NEXT:    lfs f1, 0(r4)
-; SMALL64-NEXT:    fadds f1, f0, f1
+; SMALL64-NEXT:    lfsx f1, r13, r3
+; SMALL64-NEXT:    fadds f1, f1, f0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: loadITLUninit2:
 ; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C4@u(r2)
+; LARGE64-NEXT:    ld r3, L..C4@l(r3)
+; LARGE64-NEXT:    lfs f0, 0(r3)
 ; LARGE64-NEXT:    addis r3, L..C0@u(r2)
-; LARGE64-NEXT:    addis r4, L..C4@u(r2)
 ; LARGE64-NEXT:    ld r3, L..C0@l(r3)
-; LARGE64-NEXT:    ld r4, L..C4@l(r4)
-; LARGE64-NEXT:    lfsx f0, r13, r3
-; LARGE64-NEXT:    lfs f1, 0(r4)
-; LARGE64-NEXT:    fadds f1, f0, f1
+; LARGE64-NEXT:    lfsx f1, r13, r3
+; LARGE64-NEXT:    fadds f1, f1, f0
 ; LARGE64-NEXT:    blr
 ;
 ; SMALL32-LABEL: loadITLUninit2:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr r0
 ; SMALL32-NEXT:    stwu r1, -32(r1)
-; SMALL32-NEXT:    lwz r4, L..C0(r2) # target-flags(ppc-tprel) @IThreadLocalVarUninit
 ; SMALL32-NEXT:    lwz r5, L..C4(r2) # @VarInit
+; SMALL32-NEXT:    lwz r4, L..C0(r2) # target-flags(ppc-tprel) @IThreadLocalVarUninit
 ; SMALL32-NEXT:    stw r0, 40(r1)
 ; SMALL32-NEXT:    bla .__get_tpointer[PR]
-; SMALL32-NEXT:    lfsx f0, r3, r4
-; SMALL32-NEXT:    lfs f1, 0(r5)
-; SMALL32-NEXT:    fadds f1, f0, f1
+; SMALL32-NEXT:    lfs f0, 0(r5)
+; SMALL32-NEXT:    lfsx f1, r3, r4
+; SMALL32-NEXT:    fadds f1, f1, f0
 ; SMALL32-NEXT:    addi r1, r1, 32
 ; SMALL32-NEXT:    lwz r0, 8(r1)
 ; SMALL32-NEXT:    mtlr r0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: loadITLUninit2:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr r0

   %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @IThreadLocalVarInit)
   %1 = load float, ptr %0, align 4
   ret float %1
 }
 
 define float @loadITLInit2() {
 ; SMALL64-LABEL: loadITLInit2:
 ; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C4(r2) # @VarInit
+; SMALL64-NEXT:    lfs f0, 0(r3)
 ; SMALL64-NEXT:    ld r3, L..C1(r2) # target-flags(ppc-tprel) @IThreadLocalVarInit
-; SMALL64-NEXT:    ld r4, L..C4(r2) # @VarInit
-; SMALL64-NEXT:    lfsx f0, r13, r3
-; SMALL64-NEXT:    lfs f1, 0(r4)
-; SMALL64-NEXT:    fadds f1, f0, f1
+; SMALL64-NEXT:    lfsx f1, r13, r3
+; SMALL64-NEXT:    fadds f1, f1, f0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: loadITLInit2:
 ; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C4@u(r2)
+; LARGE64-NEXT:    ld r3, L..C4@l(r3)
+; LARGE64-NEXT:    lfs f0, 0(r3)
 ; LARGE64-NEXT:    addis r3, L..C1@u(r2)
-; LARGE64-NEXT:    addis r4, L..C4@u(r2)
 ; LARGE64-NEXT:    ld r3, L..C1@l(r3)
-; LARGE64-NEXT:    ld r4, L..C4@l(r4)
-; LARGE64-NEXT:    lfsx f0, r13, r3
-; LARGE64-NEXT:    lfs f1, 0(r4)
-; LARGE64-NEXT:    fadds f1, f0, f1
+; LARGE64-NEXT:    lfsx f1, r13, r3
+; LARGE64-NEXT:    fadds f1, f1, f0
 ; LARGE64-NEXT:    blr
 ;
 ; SMALL32-LABEL: loadITLInit2:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr r0
 ; SMALL32-NEXT:    stwu r1, -32(r1)
-; SMALL32-NEXT:    lwz r4, L..C1(r2) # target-flags(ppc-tprel) @IThreadLocalVarInit
 ; SMALL32-NEXT:    lwz r5, L..C4(r2) # @VarInit
+; SMALL32-NEXT:    lwz r4, L..C1(r2) # target-flags(ppc-tprel) @IThreadLocalVarInit
 ; SMALL32-NEXT:    stw r0, 40(r1)
 ; SMALL32-NEXT:    bla .__get_tpointer[PR]
-; SMALL32-NEXT:    lfsx f0, r3, r4
-; SMALL32-NEXT:    lfs f1, 0(r5)
-; SMALL32-NEXT:    fadds f1, f0, f1
+; SMALL32-NEXT:    lfs f0, 0(r5)
+; SMALL32-NEXT:    lfsx f1, r3, r4
+; SMALL32-NEXT:    fadds f1, f1, f0
 ; SMALL32-NEXT:    addi r1, r1, 32
 ; SMALL32-NEXT:    lwz r0, 8(r1)
 ; SMALL32-NEXT:    mtlr r0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: loadITLInit2:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr r0

   %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @ThreadLocalVarUninit)
   %1 = load float, ptr %0, align 4
   ret float %1
 }
 
 define float @loadTLUninit2() {
 ; SMALL64-LABEL: loadTLUninit2:
 ; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C4(r2) # @VarInit
+; SMALL64-NEXT:    lfs f0, 0(r3)
 ; SMALL64-NEXT:    ld r3, L..C2(r2) # target-flags(ppc-tprel) @ThreadLocalVarUninit
-; SMALL64-NEXT:    ld r4, L..C4(r2) # @VarInit
-; SMALL64-NEXT:    lfsx f0, r13, r3
-; SMALL64-NEXT:    lfs f1, 0(r4)
-; SMALL64-NEXT:    fadds f1, f0, f1
+; SMALL64-NEXT:    lfsx f1, r13, r3
+; SMALL64-NEXT:    fadds f1, f1, f0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: loadTLUninit2:
 ; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C4@u(r2)
+; LARGE64-NEXT:    ld r3, L..C4@l(r3)
+; LARGE64-NEXT:    lfs f0, 0(r3)
 ; LARGE64-NEXT:    addis r3, L..C2@u(r2)
-; LARGE64-NEXT:    addis r4, L..C4@u(r2)
 ; LARGE64-NEXT:    ld r3, L..C2@l(r3)
-; LARGE64-NEXT:    ld r4, L..C4@l(r4)
-; LARGE64-NEXT:    lfsx f0, r13, r3
-; LARGE64-NEXT:    lfs f1, 0(r4)
-; LARGE64-NEXT:    fadds f1, f0, f1
+; LARGE64-NEXT:    lfsx f1, r13, r3
+; LARGE64-NEXT:    fadds f1, f1, f0
 ; LARGE64-NEXT:    blr
 ;
 ; SMALL32-LABEL: loadTLUninit2:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr r0
 ; SMALL32-NEXT:    stwu r1, -32(r1)
-; SMALL32-NEXT:    lwz r4, L..C2(r2) # target-flags(ppc-tprel) @ThreadLocalVarUninit
 ; SMALL32-NEXT:    lwz r5, L..C4(r2) # @VarInit
+; SMALL32-NEXT:    lwz r4, L..C2(r2) # target-flags(ppc-tprel) @ThreadLocalVarUninit
 ; SMALL32-NEXT:    stw r0, 40(r1)
 ; SMALL32-NEXT:    bla .__get_tpointer[PR]
-; SMALL32-NEXT:    lfsx f0, r3, r4
-; SMALL32-NEXT:    lfs f1, 0(r5)
-; SMALL32-NEXT:    fadds f1, f0, f1
+; SMALL32-NEXT:    lfs f0, 0(r5)
+; SMALL32-NEXT:    lfsx f1, r3, r4
+; SMALL32-NEXT:    fadds f1, f1, f0
 ; SMALL32-NEXT:    addi r1, r1, 32
 ; SMALL32-NEXT:    lwz r0, 8(r1)
 ; SMALL32-NEXT:    mtlr r0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: loadTLUninit2:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr r0

   %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @ThreadLocalVarInit)
   %1 = load float, ptr %0, align 4
   ret float %1
 }
 
 define float @loadTLInit2() {
 ; SMALL64-LABEL: loadTLInit2:
 ; SMALL64:       # %bb.0: # %entry
+; SMALL64-NEXT:    ld r3, L..C4(r2) # @VarInit
+; SMALL64-NEXT:    lfs f0, 0(r3)
 ; SMALL64-NEXT:    ld r3, L..C3(r2) # target-flags(ppc-tprel) @ThreadLocalVarInit
-; SMALL64-NEXT:    ld r4, L..C4(r2) # @VarInit
-; SMALL64-NEXT:    lfsx f0, r13, r3
-; SMALL64-NEXT:    lfs f1, 0(r4)
-; SMALL64-NEXT:    fadds f1, f0, f1
+; SMALL64-NEXT:    lfsx f1, r13, r3
+; SMALL64-NEXT:    fadds f1, f1, f0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: loadTLInit2:
 ; LARGE64:       # %bb.0: # %entry
+; LARGE64-NEXT:    addis r3, L..C4@u(r2)
+; LARGE64-NEXT:    ld r3, L..C4@l(r3)
+; LARGE64-NEXT:    lfs f0, 0(r3)
 ; LARGE64-NEXT:    addis r3, L..C3@u(r2)
-; LARGE64-NEXT:    addis r4, L..C4@u(r2)
 ; LARGE64-NEXT:    ld r3, L..C3@l(r3)
-; LARGE64-NEXT:    ld r4, L..C4@l(r4)
-; LARGE64-NEXT:    lfsx f0, r13, r3
-; LARGE64-NEXT:    lfs f1, 0(r4)
-; LARGE64-NEXT:    fadds f1, f0, f1
+; LARGE64-NEXT:    lfsx f1, r13, r3
+; LARGE64-NEXT:    fadds f1, f1, f0
 ; LARGE64-NEXT:    blr
 ;
 ; SMALL32-LABEL: loadTLInit2:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr r0
 ; SMALL32-NEXT:    stwu r1, -32(r1)
-; SMALL32-NEXT:    lwz r4, L..C3(r2) # target-flags(ppc-tprel) @ThreadLocalVarInit
 ; SMALL32-NEXT:    lwz r5, L..C4(r2) # @VarInit
+; SMALL32-NEXT:    lwz r4, L..C3(r2) # target-flags(ppc-tprel) @ThreadLocalVarInit
 ; SMALL32-NEXT:    stw r0, 40(r1)
 ; SMALL32-NEXT:    bla .__get_tpointer[PR]
-; SMALL32-NEXT:    lfsx f0, r3, r4
-; SMALL32-NEXT:    lfs f1, 0(r5)
-; SMALL32-NEXT:    fadds f1, f0, f1
+; SMALL32-NEXT:    lfs f0, 0(r5)
+; SMALL32-NEXT:    lfsx f1, r3, r4
+; SMALL32-NEXT:    fadds f1, f1, f0
 ; SMALL32-NEXT:    addi r1, r1, 32
 ; SMALL32-NEXT:    lwz r0, 8(r1)
 ; SMALL32-NEXT:    mtlr r0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: loadTLInit2:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr r0

llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-int.ll

 ; LARGE64-NEXT:    extsw r3, r3
 ; LARGE64-NEXT:    blr
 ;
 ; SMALL32-LABEL: loadITLUninit2:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr r0
 ; SMALL32-NEXT:    stwu r1, -32(r1)
 ; SMALL32-NEXT:    lwz r4, L..C0(r2) # target-flags(ppc-tprel) @IThreadLocalVarUninit
-; SMALL32-NEXT:    lwz r5, L..C4(r2) # @VarInit
 ; SMALL32-NEXT:    stw r0, 40(r1)
 ; SMALL32-NEXT:    bla .__get_tpointer[PR]
 ; SMALL32-NEXT:    lwzx r3, r3, r4
-; SMALL32-NEXT:    lwz r4, 0(r5)
+; SMALL32-NEXT:    lwz r4, L..C4(r2) # @VarInit
+; SMALL32-NEXT:    lwz r4, 0(r4)
 ; SMALL32-NEXT:    add r3, r4, r3
 ; SMALL32-NEXT:    addi r1, r1, 32
 ; SMALL32-NEXT:    lwz r0, 8(r1)
 ; SMALL32-NEXT:    mtlr r0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: loadITLUninit2:
 ; LARGE32:       # %bb.0: # %entry

 ; LARGE64-NEXT:    extsw r3, r3
 ; LARGE64-NEXT:    blr
 ;
 ; SMALL32-LABEL: loadITLInit2:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr r0
 ; SMALL32-NEXT:    stwu r1, -32(r1)
 ; SMALL32-NEXT:    lwz r4, L..C1(r2) # target-flags(ppc-tprel) @IThreadLocalVarInit
-; SMALL32-NEXT:    lwz r5, L..C4(r2) # @VarInit
 ; SMALL32-NEXT:    stw r0, 40(r1)
 ; SMALL32-NEXT:    bla .__get_tpointer[PR]
 ; SMALL32-NEXT:    lwzx r3, r3, r4
-; SMALL32-NEXT:    lwz r4, 0(r5)
+; SMALL32-NEXT:    lwz r4, L..C4(r2) # @VarInit
+; SMALL32-NEXT:    lwz r4, 0(r4)
 ; SMALL32-NEXT:    add r3, r4, r3
 ; SMALL32-NEXT:    addi r1, r1, 32
 ; SMALL32-NEXT:    lwz r0, 8(r1)
 ; SMALL32-NEXT:    mtlr r0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: loadITLInit2:
 ; LARGE32:       # %bb.0: # %entry

 ; LARGE64-NEXT:    extsw r3, r3
 ; LARGE64-NEXT:    blr
 ;
 ; SMALL32-LABEL: loadTLUninit2:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr r0
 ; SMALL32-NEXT:    stwu r1, -32(r1)
 ; SMALL32-NEXT:    lwz r4, L..C2(r2) # target-flags(ppc-tprel) @ThreadLocalVarUninit
-; SMALL32-NEXT:    lwz r5, L..C4(r2) # @VarInit
 ; SMALL32-NEXT:    stw r0, 40(r1)
 ; SMALL32-NEXT:    bla .__get_tpointer[PR]
 ; SMALL32-NEXT:    lwzx r3, r3, r4
-; SMALL32-NEXT:    lwz r4, 0(r5)
+; SMALL32-NEXT:    lwz r4, L..C4(r2) # @VarInit
+; SMALL32-NEXT:    lwz r4, 0(r4)
 ; SMALL32-NEXT:    add r3, r4, r3
 ; SMALL32-NEXT:    addi r1, r1, 32
 ; SMALL32-NEXT:    lwz r0, 8(r1)
 ; SMALL32-NEXT:    mtlr r0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: loadTLUninit2:
 ; LARGE32:       # %bb.0: # %entry

 ; LARGE64-NEXT:    extsw r3, r3
 ; LARGE64-NEXT:    blr
 ;
 ; SMALL32-LABEL: loadTLInit2:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr r0
 ; SMALL32-NEXT:    stwu r1, -32(r1)
 ; SMALL32-NEXT:    lwz r4, L..C3(r2) # target-flags(ppc-tprel) @ThreadLocalVarInit
-; SMALL32-NEXT:    lwz r5, L..C4(r2) # @VarInit
 ; SMALL32-NEXT:    stw r0, 40(r1)
 ; SMALL32-NEXT:    bla .__get_tpointer[PR]
 ; SMALL32-NEXT:    lwzx r3, r3, r4
-; SMALL32-NEXT:    lwz r4, 0(r5)
+; SMALL32-NEXT:    lwz r4, L..C4(r2) # @VarInit
+; SMALL32-NEXT:    lwz r4, 0(r4)
 ; SMALL32-NEXT:    add r3, r4, r3
 ; SMALL32-NEXT:    addi r1, r1, 32
 ; SMALL32-NEXT:    lwz r0, 8(r1)
 ; SMALL32-NEXT:    mtlr r0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: loadTLInit2:
 ; LARGE32:       # %bb.0: # %entry

llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-longlong.ll

 ; LARGE64-NEXT:    add r3, r4, r3
 ; LARGE64-NEXT:    blr
 ;
 ; SMALL32-LABEL: loadITLUninit2:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr r0
 ; SMALL32-NEXT:    stwu r1, -32(r1)
 ; SMALL32-NEXT:    lwz r4, L..C0(r2) # target-flags(ppc-tprel) @IThreadLocalVarUninit
-; SMALL32-NEXT:    lwz r5, L..C4(r2) # @VarInit
 ; SMALL32-NEXT:    bla .__get_tpointer[PR]
+; SMALL32-NEXT:    lwz r5, L..C4(r2) # @VarInit
 ; SMALL32-NEXT:    stw r0, 40(r1)
 ; SMALL32-NEXT:    add r3, r3, r4
 ; SMALL32-NEXT:    lwz r6, 4(r5)
 ; SMALL32-NEXT:    lwz r5, 0(r5)
 ; SMALL32-NEXT:    lwz r4, 4(r3)
 ; SMALL32-NEXT:    lwz r3, 0(r3)
 ; SMALL32-NEXT:    addc r4, r6, r4
 ; SMALL32-NEXT:    adde r3, r5, r3

 ; LARGE64-NEXT:    add r3, r4, r3
 ; LARGE64-NEXT:    blr
 ;
 ; SMALL32-LABEL: loadITLInit2:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr r0
 ; SMALL32-NEXT:    stwu r1, -32(r1)
 ; SMALL32-NEXT:    lwz r4, L..C1(r2) # target-flags(ppc-tprel) @IThreadLocalVarInit
-; SMALL32-NEXT:    lwz r5, L..C4(r2) # @VarInit
 ; SMALL32-NEXT:    bla .__get_tpointer[PR]
+; SMALL32-NEXT:    lwz r5, L..C4(r2) # @VarInit
 ; SMALL32-NEXT:    stw r0, 40(r1)
 ; SMALL32-NEXT:    add r3, r3, r4
 ; SMALL32-NEXT:    lwz r6, 4(r5)
 ; SMALL32-NEXT:    lwz r5, 0(r5)
 ; SMALL32-NEXT:    lwz r4, 4(r3)
 ; SMALL32-NEXT:    lwz r3, 0(r3)
 ; SMALL32-NEXT:    addc r4, r6, r4
 ; SMALL32-NEXT:    adde r3, r5, r3

 ; LARGE64-NEXT:    add r3, r4, r3
 ; LARGE64-NEXT:    blr
 ;
 ; SMALL32-LABEL: loadTLUninit2:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr r0
 ; SMALL32-NEXT:    stwu r1, -32(r1)
 ; SMALL32-NEXT:    lwz r4, L..C2(r2) # target-flags(ppc-tprel) @ThreadLocalVarUninit
-; SMALL32-NEXT:    lwz r5, L..C4(r2) # @VarInit
 ; SMALL32-NEXT:    bla .__get_tpointer[PR]
+; SMALL32-NEXT:    lwz r5, L..C4(r2) # @VarInit
 ; SMALL32-NEXT:    stw r0, 40(r1)
 ; SMALL32-NEXT:    add r3, r3, r4
 ; SMALL32-NEXT:    lwz r6, 4(r5)
 ; SMALL32-NEXT:    lwz r5, 0(r5)
 ; SMALL32-NEXT:    lwz r4, 4(r3)
 ; SMALL32-NEXT:    lwz r3, 0(r3)
 ; SMALL32-NEXT:    addc r4, r6, r4
 ; SMALL32-NEXT:    adde r3, r5, r3

 ; LARGE64-NEXT:    add r3, r4, r3
 ; LARGE64-NEXT:    blr
 ;
 ; SMALL32-LABEL: loadTLInit2:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr r0
 ; SMALL32-NEXT:    stwu r1, -32(r1)
 ; SMALL32-NEXT:    lwz r4, L..C3(r2) # target-flags(ppc-tprel) @ThreadLocalVarInit
-; SMALL32-NEXT:    lwz r5, L..C4(r2) # @VarInit
 ; SMALL32-NEXT:    bla .__get_tpointer[PR]
+; SMALL32-NEXT:    lwz r5, L..C4(r2) # @VarInit
 ; SMALL32-NEXT:    stw r0, 40(r1)
 ; SMALL32-NEXT:    add r3, r3, r4
 ; SMALL32-NEXT:    lwz r6, 4(r5)
 ; SMALL32-NEXT:    lwz r5, 0(r5)
 ; SMALL32-NEXT:    lwz r4, 4(r3)
 ; SMALL32-NEXT:    lwz r3, 0(r3)
 ; SMALL32-NEXT:    addc r4, r6, r4
 ; SMALL32-NEXT:    adde r3, r5, r3

llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll

 %struct.Test = type { double, double, double, double }
 
 @__const.caller.t = private unnamed_addr constant %struct.Test { double 0.000000e+00, double 1.000000e+00, double 2.000000e+00, double 3.000000e+00 }, align 8
 
 define double @caller() {
 
   ; MIR32-LABEL: name: caller
   ; MIR32: bb.0.entry:
-  ; MIR32-NEXT:   renamable $r3 = LIS 16392
-  ; MIR32-NEXT:   renamable $r4 = LIS 16384
-  ; MIR32-NEXT:   STW killed renamable $r3, 180, $r1 :: (store (s32) into unknown-address + 24)
   ; MIR32-NEXT:   renamable $r3 = LI 0
-  ; MIR32-NEXT:   STW killed renamable $r4, 172, $r1 :: (store (s32) into unknown-address + 16)
-  ; MIR32-NEXT:   renamable $r4 = LIS 16368
+  ; MIR32-NEXT:   renamable $r4 = LIS 16392
+  ; MIR32-NEXT:   STW killed renamable $r4, 180, $r1 :: (store (s32) into unknown-address + 24)
+  ; MIR32-NEXT:   renamable $r4 = LIS 16384
   ; MIR32-NEXT:   STW renamable $r3, 184, $r1 :: (store (s32) into unknown-address + 28)
   ; MIR32-NEXT:   STW renamable $r3, 176, $r1 :: (store (s32) into unknown-address + 20)
+  ; MIR32-NEXT:   STW killed renamable $r4, 172, $r1 :: (store (s32) into unknown-address + 16)
   ; MIR32-NEXT:   STW renamable $r3, 168, $r1 :: (store (s32) into unknown-address + 12)
+  ; MIR32-NEXT:   renamable $r4 = LIS 16368
   ; MIR32-NEXT:   STW killed renamable $r4, 164, $r1 :: (store (s32) into unknown-address + 8)
   ; MIR32-NEXT:   STW renamable $r3, 160, $r1 :: (store (s32) into unknown-address + 4)
   ; MIR32-NEXT:   STW killed renamable $r3, 156, $r1 :: (store (s32))
   ; MIR32-NEXT:   ADJCALLSTACKDOWN 188, 0, implicit-def dead $r1, implicit $r1
   ; MIR32-NEXT:   renamable $vsl0 = XXLXORz
+  ; MIR32-NEXT:   renamable $r3 = LI 136
+  ; MIR32-NEXT:   renamable $r4 = LWZtoc %const.0, $r2 :: (load (s32) from got)
+  ; MIR32-NEXT:   renamable $vsl1 = LXVD2X $zero, killed renamable $r4 :: (load (s128) from constant-pool)
+  ; MIR32-NEXT:   renamable $r4 = LI 120
+  ; MIR32-NEXT:   STXVW4X renamable $vsl0, $r1, killed renamable $r3 :: (store (s128), align 8)
+  ; MIR32-NEXT:   renamable $r3 = LI 104
+  ; MIR32-NEXT:   STXVW4X renamable $vsl0, $r1, killed renamable $r4 :: (store (s128), align 8)
+  ; MIR32-NEXT:   renamable $r4 = LI 88
+  ; MIR32-NEXT:   STXVW4X renamable $vsl0, $r1, killed renamable $r3 :: (store (s128), align 8)
+  ; MIR32-NEXT:   renamable $r3 = LI 72
+  ; MIR32-NEXT:   STXVW4X renamable $vsl0, $r1, killed renamable $r4 :: (store (s128), align 8)
+  ; MIR32-NEXT:   renamable $r4 = LI 48
+  ; MIR32-NEXT:   STXVW4X killed renamable $vsl0, $r1, killed renamable $r3 :: (store (s128), align 8)
+  ; MIR32-NEXT:   renamable $r3 = LI 512
+  ; MIR32-NEXT:   STXVD2X killed renamable $vsl1, $r1, killed renamable $r4 :: (store (s128))
+  ; MIR32-NEXT:   STW killed renamable $r3, 152, $r1 :: (store (s32))
   ; MIR32-NEXT:   $f1 = XXLXORdpz
   ; MIR32-NEXT:   $f2 = XXLXORdpz
   ; MIR32-NEXT:   $v2 = XXLXORz
   ; MIR32-NEXT:   $v3 = XXLXORz
   ; MIR32-NEXT:   $v4 = XXLXORz
   ; MIR32-NEXT:   $v5 = XXLXORz
   ; MIR32-NEXT:   $v6 = XXLXORz
   ; MIR32-NEXT:   $v7 = XXLXORz
   ; MIR32-NEXT:   $v8 = XXLXORz
   ; MIR32-NEXT:   $v9 = XXLXORz
   ; MIR32-NEXT:   $v10 = XXLXORz
+  ; MIR32-NEXT:   $r3 = LI 128
+  ; MIR32-NEXT:   $r4 = LI 256
   ; MIR32-NEXT:   $v11 = XXLXORz
   ; MIR32-NEXT:   $v12 = XXLXORz
   ; MIR32-NEXT:   $v13 = XXLXORz
   ; MIR32-NEXT:   $f3 = XXLXORdpz
   ; MIR32-NEXT:   $f4 = XXLXORdpz
   ; MIR32-NEXT:   $f5 = XXLXORdpz
   ; MIR32-NEXT:   $f6 = XXLXORdpz
   ; MIR32-NEXT:   $f7 = XXLXORdpz
-  ; MIR32-NEXT:   renamable $r3 = LI 136
   ; MIR32-NEXT:   $f8 = XXLXORdpz
-  ; MIR32-NEXT:   renamable $r4 = LI 120
-  ; MIR32-NEXT:   renamable $r5 = LWZtoc %const.0, $r2 :: (load (s32) from got)
-  ; MIR32-NEXT:   STXVW4X renamable $vsl0, $r1, killed renamable $r3 :: (store (s128), align 8)
   ; MIR32-NEXT:   $f9 = XXLXORdpz
-  ; MIR32-NEXT:   renamable $r3 = LI 104
-  ; MIR32-NEXT:   STXVW4X renamable $vsl0, $r1, killed renamable $r4 :: (store (s128), align 8)
   ; MIR32-NEXT:   $f10 = XXLXORdpz
-  ; MIR32-NEXT:   STXVW4X renamable $vsl0, $r1, killed renamable $r3 :: (store (s128), align 8)
-  ; MIR32-NEXT:   renamable $r3 = LI 88
   ; MIR32-NEXT:   $f11 = XXLXORdpz
-  ; MIR32-NEXT:   STXVW4X renamable $vsl0, $r1, killed renamable $r3 :: (store (s128), align 8)
-  ; MIR32-NEXT:   renamable $r3 = LI 72
-  ; MIR32-NEXT:   renamable $v0 = LXVD2X $zero, killed renamable $r5 :: (load (s128) from constant-pool)
   ; MIR32-NEXT:   $f12 = XXLXORdpz
-  ; MIR32-NEXT:   STXVW4X killed renamable $vsl0, $r1, killed renamable $r3 :: (store (s128), align 8)
   ; MIR32-NEXT:   $f13 = XXLXORdpz
-  ; MIR32-NEXT:   renamable $r5 = LI 48
-  ; MIR32-NEXT:   renamable $r6 = LI 512
-  ; MIR32-NEXT:   $r3 = LI 128
-  ; MIR32-NEXT:   $r4 = LI 256
-  ; MIR32-NEXT:   STXVD2X killed renamable $v0, $r1, killed renamable $r5 :: (store (s128))
-  ; MIR32-NEXT:   STW killed renamable $r6, 152, $r1 :: (store (s32))
-  ; MIR32-NEXT:   BL_NOP <mcsymbol .callee[PR]>, csr_aix32_altivec, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $f1, implicit $f2, implicit $v2, implicit $v3, implicit $v4, implicit $v5, implicit killed $v6, implicit killed $v7, implicit killed $v8, implicit killed $v9, implicit killed $v10, implicit killed $v11, implicit killed $v12, implicit killed $v13, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit $f10, implicit $f11, implicit $f12, implicit $f13, implicit $r2, implicit-def $r1, implicit-def $f1
+  ; MIR32-NEXT:   BL_NOP <mcsymbol .callee[PR]>, csr_aix32_altivec, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $f1, implicit killed $f2, implicit killed $v2, implicit killed $v3, implicit killed $v4, implicit killed $v5, implicit killed $v6, implicit killed $v7, implicit killed $v8, implicit killed $v9, implicit killed $v10, implicit killed $v11, implicit killed $v12, implicit killed $v13, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $r2, implicit-def $r1, implicit-def $f1
   ; MIR32-NEXT:   ADJCALLSTACKUP 188, 0, implicit-def dead $r1, implicit $r1
   ; MIR32-NEXT:   BLR implicit $lr, implicit $rm, implicit $f1
+  ;
   ; MIR64-LABEL: name: caller
   ; MIR64: bb.0.entry:
   ; MIR64-NEXT:   renamable $x3 = LI8 2049
   ; MIR64-NEXT:   renamable $x4 = LI8 1
   ; MIR64-NEXT:   renamable $x3 = RLDIC killed renamable $x3, 51, 1
-  ; MIR64-NEXT:   renamable $x4 = RLDIC killed renamable $x4, 62, 1
   ; MIR64-NEXT:   STD killed renamable $x3, 216, $x1 :: (store (s64) into unknown-address + 24, align 4)
   ; MIR64-NEXT:   renamable $x3 = LI8 1023
+  ; MIR64-NEXT:   renamable $x4 = RLDIC killed renamable $x4, 62, 1
   ; MIR64-NEXT:   STD killed renamable $x4, 208, $x1 :: (store (s64) into unknown-address + 16, align 4)
-  ; MIR64-NEXT:   renamable $x5 = LI8 0
+  ; MIR64-NEXT:   renamable $x4 = LI8 0
+  ; MIR64-NEXT:   STD renamable $x4, 192, $x1 :: (store (s64), align 4)
   ; MIR64-NEXT:   renamable $x3 = RLDIC killed renamable $x3, 52, 2
-  ; MIR64-NEXT:   STD renamable $x5, 192, $x1 :: (store (s64), align 4)
   ; MIR64-NEXT:   STD killed renamable $x3, 200, $x1 :: (store (s64) into unknown-address + 8, align 4)
   ; MIR64-NEXT:   ADJCALLSTACKDOWN 224, 0, implicit-def dead $r1, implicit $r1
   ; MIR64-NEXT:   renamable $vsl0 = XXLXORz
+  ; MIR64-NEXT:   renamable $x3 = LDtocCPT %const.0, $x2 :: (load (s64) from got)
+  ; MIR64-NEXT:   renamable $vsl1 = LXVD2X $zero8, killed renamable $x3 :: (load (s128) from constant-pool)
+  ; MIR64-NEXT:   renamable $x3 = LI8 160
+  ; MIR64-NEXT:   STXVW4X renamable $vsl0, $x1, killed renamable $x3 :: (store (s128), align 8)
+  ; MIR64-NEXT:   renamable $x3 = LI8 144
+  ; MIR64-NEXT:   STXVW4X renamable $vsl0, $x1, killed renamable $x3 :: (store (s128), align 8)
+  ; MIR64-NEXT:   renamable $x3 = LI8 128
+  ; MIR64-NEXT:   STXVW4X killed renamable $vsl0, $x1, killed renamable $x3 :: (store (s128), align 8)
+  ; MIR64-NEXT:   renamable $x3 = LI8 80
+  ; MIR64-NEXT:   STXVD2X killed renamable $vsl1, $x1, killed renamable $x3 :: (store (s128))
+  ; MIR64-NEXT:   renamable $x3 = LI8 512
+  ; MIR64-NEXT:   STD killed renamable $x3, 184, $x1 :: (store (s64))
+  ; MIR64-NEXT:   STD killed renamable $x4, 176, $x1 :: (store (s64))
   ; MIR64-NEXT:   $f1 = XXLXORdpz
   ; MIR64-NEXT:   $f2 = XXLXORdpz
   ; MIR64-NEXT:   $v2 = XXLXORz
   ; MIR64-NEXT:   $v3 = XXLXORz
   ; MIR64-NEXT:   $v4 = XXLXORz
   ; MIR64-NEXT:   $v5 = XXLXORz
   ; MIR64-NEXT:   $v6 = XXLXORz
   ; MIR64-NEXT:   $v7 = XXLXORz
   ; MIR64-NEXT:   $v8 = XXLXORz
   ; MIR64-NEXT:   $v9 = XXLXORz
   ; MIR64-NEXT:   $v10 = XXLXORz
+  ; MIR64-NEXT:   $x3 = LI8 128
+  ; MIR64-NEXT:   $x4 = LI8 256
   ; MIR64-NEXT:   $v11 = XXLXORz
   ; MIR64-NEXT:   $v12 = XXLXORz
   ; MIR64-NEXT:   $v13 = XXLXORz
   ; MIR64-NEXT:   $f3 = XXLXORdpz
   ; MIR64-NEXT:   $f4 = XXLXORdpz
   ; MIR64-NEXT:   $f5 = XXLXORdpz
   ; MIR64-NEXT:   $f6 = XXLXORdpz
   ; MIR64-NEXT:   $f7 = XXLXORdpz
-  ; MIR64-NEXT:   renamable $x3 = LDtocCPT %const.0, $x2 :: (load (s64) from got)
   ; MIR64-NEXT:   $f8 = XXLXORdpz
   ; MIR64-NEXT:   $f9 = XXLXORdpz
-  ; MIR64-NEXT:   renamable $x4 = LI8 160
   ; MIR64-NEXT:   $f10 = XXLXORdpz
-  ; MIR64-NEXT:   renamable $x6 = LI8 144
-  ; MIR64-NEXT:   STXVW4X renamable $vsl0, $x1, killed renamable $x4 :: (store (s128), align 8)
-  ; MIR64-NEXT:   renamable $v0 = LXVD2X $zero8, killed renamable $x3 :: (load (s128) from constant-pool)
   ; MIR64-NEXT:   $f11 = XXLXORdpz
-  ; MIR64-NEXT:   renamable $x3 = LI8 128
-  ; MIR64-NEXT:   STXVW4X renamable $vsl0, $x1, killed renamable $x6 :: (store (s128), align 8)
   ; MIR64-NEXT:   $f12 = XXLXORdpz
-  ; MIR64-NEXT:   renamable $x4 = LI8 80
-  ; MIR64-NEXT:   STXVW4X killed renamable $vsl0, $x1, killed renamable $x3 :: (store (s128), align 8)
   ; MIR64-NEXT:   $f13 = XXLXORdpz
-  ; MIR64-NEXT:   STXVD2X killed renamable $v0, $x1, killed renamable $x4 :: (store (s128))
-  ; MIR64-NEXT:   renamable $x6 = LI8 512
-  ; MIR64-NEXT:   $x3 = LI8 128
-  ; MIR64-NEXT:   $x4 = LI8 256
-  ; MIR64-NEXT:   STD killed renamable $x6, 184, $x1 :: (store (s64))
-  ; MIR64-NEXT:   STD killed renamable $x5, 176, $x1 :: (store (s64))
-  ; MIR64-NEXT:   BL8_NOP <mcsymbol .callee[PR]>, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $f1, implicit $f2, implicit $v2, implicit $v3, implicit $v4, implicit $v5, implicit killed $v6, implicit killed $v7, implicit killed $v8, implicit killed $v9, implicit killed $v10, implicit killed $v11, implicit killed $v12, implicit killed $v13, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit $f10, implicit $f11, implicit $f12, implicit $f13, implicit $x2, implicit-def $r1, implicit-def $f1
+  ; MIR64-NEXT:   BL8_NOP <mcsymbol .callee[PR]>, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $f1, implicit killed $f2, implicit killed $v2, implicit killed $v3, implicit killed $v4, implicit killed $v5, implicit killed $v6, implicit killed $v7, implicit killed $v8, implicit killed $v9, implicit killed $v10, implicit killed $v11, implicit killed $v12, implicit killed $v13, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $x2, implicit-def $r1, implicit-def $f1
   ; MIR64-NEXT:   ADJCALLSTACKUP 224, 0, implicit-def dead $r1, implicit $r1
   ; MIR64-NEXT:   BLR8 implicit $lr8, implicit $rm, implicit $f1
   entry:
     %call = tail call double @callee(i32 signext 128, i32 signext 256, double 0.000000e+00, double 0.000000e+00, <2 x double> <double 0.000000e+00, double 0.000000e+00>, <2 x double> <double 0.000000e+00, double 0.000000e+00>, <2 x double> <double 0.000000e+00, double 0.000000e+00>, <2 x double> <double 0.000000e+00, double 0.000000e+00>, <2 x double> <double 0.000000e+00, double 0.000000e+00>, <2 x double> <double 0.000000e+00, double 0.000000e+00>, <2 x double> <double 0.000000e+00, double 0.000000e+00>, <2 x double> <double 0.000000e+00, double 0.000000e+00>, <2 x double> <double 0.000000e+00, double 0.000000e+00>, <2 x double> <double 0.000000e+00, double 0.000000e+00>, <2 x double> <double 0.000000e+00, double 0.000000e+00>, <2 x double> <double 0.000000e+00, double 0.000000e+00>, <2 x double> <double 2.400000e+01, double 2.500000e+01>, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, i32 signext 512, ptr nonnull byval(%struct.Test) align 4 @__const.caller.t)
       ret double %call
 }
 
 declare double @callee(i32 signext, i32 signext, double, double, <2 x double>, <2 x double>, <2 x double>, <2 x double>, <2 x double>, <2 x double>, <2 x double>, <2 x double>, <2 x double>, <2 x double>, <2 x double>, <2 x double>, <2 x double>, double, double, double, double, double, double, double, double, double, double, double, i32 signext, ptr byval(%struct.Test) align 8)

llvm/test/CodeGen/PowerPC/aix-vec-arg-spills.ll

 
 @__const.caller.t = private unnamed_addr constant %struct.Test { double 0.000000e+00, double 1.000000e+00, double 2.000000e+00, double 3.000000e+00 }, align 8
 
 define double @caller() {
 ; 32BIT-LABEL: caller:
 ; 32BIT:       # %bb.0: # %entry
 ; 32BIT-NEXT:    mflr 0
 ; 32BIT-NEXT:    stwu 1, -192(1)
-; 32BIT-NEXT:    lis 3, 16392
+; 32BIT-NEXT:    lis 4, 16392
 ; 32BIT-NEXT:    stw 0, 200(1)
-; 32BIT-NEXT:    lis 4, 16384
 ; 32BIT-NEXT:    xxlxor 0, 0, 0
-; 32BIT-NEXT:    lwz 5, L..C0(2) # %const.0
-; 32BIT-NEXT:    stw 3, 180(1)
 ; 32BIT-NEXT:    li 3, 0
-; 32BIT-NEXT:    xxlxor 1, 1, 1
-; 32BIT-NEXT:    li 6, 512
-; 32BIT-NEXT:    stw 4, 172(1)
-; 32BIT-NEXT:    lis 4, 16368
 ; 32BIT-NEXT:    xxlxor 2, 2, 2
+; 32BIT-NEXT:    stw 4, 180(1)
+; 32BIT-NEXT:    lis 4, 16384
 ; 32BIT-NEXT:    stw 3, 184(1)
 ; 32BIT-NEXT:    stw 3, 176(1)
-; 32BIT-NEXT:    xxlxor 34, 34, 34
+; 32BIT-NEXT:    stw 4, 172(1)
+; 32BIT-NEXT:    lis 4, 16368
 ; 32BIT-NEXT:    stw 3, 168(1)
 ; 32BIT-NEXT:    stw 3, 160(1)
-; 32BIT-NEXT:    xxlxor 35, 35, 35
+; 32BIT-NEXT:    stw 4, 164(1)
+; 32BIT-NEXT:    lwz 4, L..C0(2) # %const.0
+; 32BIT-NEXT:    xxlxor 34, 34, 34
 ; 32BIT-NEXT:    stw 3, 156(1)
 ; 32BIT-NEXT:    li 3, 136
-; 32BIT-NEXT:    lxvd2x 32, 0, 5
-; 32BIT-NEXT:    xxlxor 36, 36, 36
-; 32BIT-NEXT:    stw 4, 164(1)
-; 32BIT-NEXT:    li 4, 120
 ; 32BIT-NEXT:    stxvw4x 0, 1, 3
-; 32BIT-NEXT:    xxlxor 37, 37, 37
 ; 32BIT-NEXT:    li 3, 104
+; 32BIT-NEXT:    lxvd2x 1, 0, 4
+; 32BIT-NEXT:    li 4, 120
+; 32BIT-NEXT:    xxlxor 35, 35, 35
+; 32BIT-NEXT:    xxlxor 36, 36, 36
+; 32BIT-NEXT:    xxlxor 37, 37, 37
 ; 32BIT-NEXT:    stxvw4x 0, 1, 4
-; 32BIT-NEXT:    xxlxor 38, 38, 38
-; 32BIT-NEXT:    li 5, 48
+; 32BIT-NEXT:    li 4, 88
+; 32BIT-NEXT:    stxvw4x 0, 1, 3
+; 32BIT-NEXT:    li 3, 72
+; 32BIT-NEXT:    stxvw4x 0, 1, 4
+; 32BIT-NEXT:    li 4, 48
 ; 32BIT-NEXT:    stxvw4x 0, 1, 3
-; 32BIT-NEXT:    li 3, 88
+; 32BIT-NEXT:    xxlxor 38, 38, 38
+; 32BIT-NEXT:    stxvd2x 1, 1, 4
+; 32BIT-NEXT:    xxlxor 1, 1, 1
 ; 32BIT-NEXT:    xxlxor 39, 39, 39
-; 32BIT-NEXT:    li 4, 256
 ; 32BIT-NEXT:    xxlxor 40, 40, 40
-; 32BIT-NEXT:    stxvw4x 0, 1, 3
-; 32BIT-NEXT:    li 3, 72
 ; 32BIT-NEXT:    xxlxor 41, 41, 41
-; 32BIT-NEXT:    stxvw4x 0, 1, 3
-; 32BIT-NEXT:    li 3, 128
 ; 32BIT-NEXT:    xxlxor 42, 42, 42
-; 32BIT-NEXT:    stxvd2x 32, 1, 5
-; 32BIT-NEXT:    stw 6, 152(1)
 ; 32BIT-NEXT:    xxlxor 43, 43, 43
 ; 32BIT-NEXT:    xxlxor 44, 44, 44
 ; 32BIT-NEXT:    xxlxor 45, 45, 45
 ; 32BIT-NEXT:    xxlxor 3, 3, 3
 ; 32BIT-NEXT:    xxlxor 4, 4, 4
 ; 32BIT-NEXT:    xxlxor 5, 5, 5
 ; 32BIT-NEXT:    xxlxor 6, 6, 6
 ; 32BIT-NEXT:    xxlxor 7, 7, 7
 ; 32BIT-NEXT:    xxlxor 8, 8, 8
 ; 32BIT-NEXT:    xxlxor 9, 9, 9
 ; 32BIT-NEXT:    xxlxor 10, 10, 10
 ; 32BIT-NEXT:    xxlxor 11, 11, 11
 ; 32BIT-NEXT:    xxlxor 12, 12, 12
 ; 32BIT-NEXT:    xxlxor 13, 13, 13
+; 32BIT-NEXT:    li 3, 512
+; 32BIT-NEXT:    stw 3, 152(1)
+; 32BIT-NEXT:    li 3, 128
+; 32BIT-NEXT:    li 4, 256
 ; 32BIT-NEXT:    bl .callee[PR]
 ; 32BIT-NEXT:    nop
 ; 32BIT-NEXT:    addi 1, 1, 192
 ; 32BIT-NEXT:    lwz 0, 8(1)
 ; 32BIT-NEXT:    mtlr 0
 ; 32BIT-NEXT:    blr
 ;
 ; 64BIT-LABEL: caller:
 ; 64BIT:       # %bb.0: # %entry
 ; 64BIT-NEXT:    mflr 0
 ; 64BIT-NEXT:    stdu 1, -224(1)
 ; 64BIT-NEXT:    li 3, 2049
 ; 64BIT-NEXT:    std 0, 240(1)
 ; 64BIT-NEXT:    li 4, 1
 ; 64BIT-NEXT:    xxlxor 0, 0, 0
+; 64BIT-NEXT:    xxlxor 2, 2, 2
 ; 64BIT-NEXT:    rldic 3, 3, 51, 1
 ; 64BIT-NEXT:    rldic 4, 4, 62, 1
-; 64BIT-NEXT:    li 5, 0
-; 64BIT-NEXT:    xxlxor 1, 1, 1
-; 64BIT-NEXT:    std 3, 216(1)
-; 64BIT-NEXT:    li 3, 1023
-; 64BIT-NEXT:    xxlxor 2, 2, 2
-; 64BIT-NEXT:    li 6, 144
-; 64BIT-NEXT:    rldic 3, 3, 52, 2
-; 64BIT-NEXT:    std 4, 208(1)
-; 64BIT-NEXT:    li 4, 160
 ; 64BIT-NEXT:    xxlxor 34, 34, 34
-; 64BIT-NEXT:    std 3, 200(1)
-; 64BIT-NEXT:    ld 3, L..C0(2) # %const.0
-; 64BIT-NEXT:    std 5, 192(1)
 ; 64BIT-NEXT:    xxlxor 35, 35, 35
 ; 64BIT-NEXT:    xxlxor 36, 36, 36
-; 64BIT-NEXT:    stxvw4x 0, 1, 4
-; 64BIT-NEXT:    li 4, 80
 ; 64BIT-NEXT:    xxlxor 37, 37, 37
-; 64BIT-NEXT:    stxvw4x 0, 1, 6
-; 64BIT-NEXT:    li 6, 512
-; 64BIT-NEXT:    lxvd2x 32, 0, 3
+; 64BIT-NEXT:    std 3, 216(1)
+; 64BIT-NEXT:    li 3, 1023
+; 64BIT-NEXT:    std 4, 208(1)
+; 64BIT-NEXT:    li 4, 0
+; 64BIT-NEXT:    rldic 3, 3, 52, 2
+; 64BIT-NEXT:    std 4, 192(1)
 ; 64BIT-NEXT:    xxlxor 38, 38, 38
-; 64BIT-NEXT:    li 3, 128
 ; 64BIT-NEXT:    xxlxor 39, 39, 39
-; 64BIT-NEXT:    stxvw4x 0, 1, 3
 ; 64BIT-NEXT:    xxlxor 40, 40, 40
+; 64BIT-NEXT:    std 3, 200(1)
+; 64BIT-NEXT:    ld 3, L..C0(2) # %const.0
 ; 64BIT-NEXT:    xxlxor 41, 41, 41
-; 64BIT-NEXT:    stxvd2x 32, 1, 4
-; 64BIT-NEXT:    li 4, 256
-; 64BIT-NEXT:    std 6, 184(1)
 ; 64BIT-NEXT:    xxlxor 42, 42, 42
-; 64BIT-NEXT:    std 5, 176(1)
 ; 64BIT-NEXT:    xxlxor 43, 43, 43
 ; 64BIT-NEXT:    xxlxor 44, 44, 44
 ; 64BIT-NEXT:    xxlxor 45, 45, 45
 ; 64BIT-NEXT:    xxlxor 3, 3, 3
 ; 64BIT-NEXT:    xxlxor 4, 4, 4
+; 64BIT-NEXT:    lxvd2x 1, 0, 3
+; 64BIT-NEXT:    li 3, 160
 ; 64BIT-NEXT:    xxlxor 5, 5, 5
 ; 64BIT-NEXT:    xxlxor 6, 6, 6
 ; 64BIT-NEXT:    xxlxor 7, 7, 7
+; 64BIT-NEXT:    stxvw4x 0, 1, 3
+; 64BIT-NEXT:    li 3, 144
 ; 64BIT-NEXT:    xxlxor 8, 8, 8
 ; 64BIT-NEXT:    xxlxor 9, 9, 9
 ; 64BIT-NEXT:    xxlxor 10, 10, 10
+; 64BIT-NEXT:    stxvw4x 0, 1, 3
+; 64BIT-NEXT:    li 3, 128
 ; 64BIT-NEXT:    xxlxor 11, 11, 11
 ; 64BIT-NEXT:    xxlxor 12, 12, 12
 ; 64BIT-NEXT:    xxlxor 13, 13, 13
+; 64BIT-NEXT:    stxvw4x 0, 1, 3
+; 64BIT-NEXT:    li 3, 80
+; 64BIT-NEXT:    stxvd2x 1, 1, 3
+; 64BIT-NEXT:    xxlxor 1, 1, 1
+; 64BIT-NEXT:    li 3, 512
+; 64BIT-NEXT:    std 4, 176(1)
+; 64BIT-NEXT:    li 4, 256
+; 64BIT-NEXT:    std 3, 184(1)
+; 64BIT-NEXT:    li 3, 128
 ; 64BIT-NEXT:    bl .callee[PR]
 ; 64BIT-NEXT:    nop
 ; 64BIT-NEXT:    addi 1, 1, 224
 ; 64BIT-NEXT:    ld 0, 16(1)
 ; 64BIT-NEXT:    mtlr 0
 ; 64BIT-NEXT:    blr
 
   entry:
     %call = tail call double @callee(i32 signext 128, i32 signext 256, double 0.000000e+00, double 0.000000e+00, <2 x double> <double 0.000000e+00, double 0.000000e+00>, <2 x double> <double 0.000000e+00, double 0.000000e+00>, <2 x double> <double 0.000000e+00, double 0.000000e+00>, <2 x double> <double 0.000000e+00, double 0.000000e+00>, <2 x double> <double 0.000000e+00, double 0.000000e+00>, <2 x double> <double 0.000000e+00, double 0.000000e+00>, <2 x double> <double 0.000000e+00, double 0.000000e+00>, <2 x double> <double 0.000000e+00, double 0.000000e+00>, <2 x double> <double 0.000000e+00, double 0.000000e+00>, <2 x double> <double 0.000000e+00, double 0.000000e+00>, <2 x double> <double 0.000000e+00, double 0.000000e+00>, <2 x double> <double 0.000000e+00, double 0.000000e+00>, <2 x double> <double 2.400000e+01, double 2.500000e+01>, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, i32 signext 512, ptr nonnull byval(%struct.Test) align 4 @__const.caller.t)
       ret double %call
 }
 
 declare double @callee(i32 signext, i32 signext, double, double, <2 x double>, <2 x double>, <2 x double>, <2 x double>, <2 x double>, <2 x double>, <2 x double>, <2 x double>, <2 x double>, <2 x double>, <2 x double>, <2 x double>, <2 x double>, double, double, double, double, double, double, double, double, double, double, double, i32 signext, ptr byval(%struct.Test) align 8)

llvm/test/CodeGen/PowerPC/aix-vector-stack-caller.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \
 ; RUN:     -vec-extabi -mtriple powerpc-ibm-aix-xcoff < %s | \
 ; RUN: FileCheck %s --check-prefixes=32BIT,LITERAL
 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \
 ; RUN:     -vec-extabi -mtriple powerpc64-ibm-aix-xcoff < %s | \
 ; RUN: FileCheck %s --check-prefixes=64BIT,LITERAL
 
 define dso_local i32 @vec_caller() {
-; LITERAL:       L..CPI0_0:
-; LITERAL-NEXT:    .vbyte  4, 53
-; LITERAL-NEXT:    .vbyte  4, 54
-; LITERAL-NEXT:    .vbyte  4, 55
-; LITERAL-NEXT:    .vbyte  4, 56
-; LITERAL-NEXT:  L..CPI0_1:
-; LITERAL-NEXT:    .vbyte  4, 49
-; LITERAL-NEXT:    .vbyte  4, 50
-; LITERAL-NEXT:    .vbyte  4, 51
-; LITERAL-NEXT:    .vbyte  4, 52
-
 ; 32BIT-LABEL: vec_caller:
 ; 32BIT:       # %bb.0: # %entry
 ; 32BIT-NEXT:    mflr 0
 ; 32BIT-NEXT:    stwu 1, -64(1)
-; 32BIT-NEXT:    lwz 3, L..C0(2)
-; 32BIT-NEXT:    lwz 4, L..C1(2)
+; 32BIT-NEXT:    lwz 3, L..C0(2) # %const.0
 ; 32BIT-NEXT:    xxlxor 34, 34, 34
-; 32BIT-NEXT:    stw 0, 72(1)
 ; 32BIT-NEXT:    xxlxor 35, 35, 35
 ; 32BIT-NEXT:    xxlxor 36, 36, 36
-; 32BIT-NEXT:    lxvw4x 0, 0, 3
-; 32BIT-NEXT:    lxvw4x 1, 0, 4
 ; 32BIT-NEXT:    xxlxor 37, 37, 37
-; 32BIT-NEXT:    li 3, 48
 ; 32BIT-NEXT:    xxlxor 38, 38, 38
-; 32BIT-NEXT:    li 4, 32
 ; 32BIT-NEXT:    xxlxor 39, 39, 39
+; 32BIT-NEXT:    stw 0, 72(1)
+; 32BIT-NEXT:    lxvw4x 0, 0, 3
+; 32BIT-NEXT:    lwz 3, L..C1(2) # %const.1
 ; 32BIT-NEXT:    xxlxor 40, 40, 40
-; 32BIT-NEXT:    stxvw4x 0, 1, 3
 ; 32BIT-NEXT:    xxlxor 41, 41, 41
-; 32BIT-NEXT:    stxvw4x 1, 1, 4
 ; 32BIT-NEXT:    xxlxor 42, 42, 42
 ; 32BIT-NEXT:    xxlxor 43, 43, 43
 ; 32BIT-NEXT:    xxlxor 44, 44, 44
 ; 32BIT-NEXT:    xxlxor 45, 45, 45
+; 32BIT-NEXT:    lxvw4x 1, 0, 3
+; 32BIT-NEXT:    li 3, 48
+; 32BIT-NEXT:    stxvw4x 0, 1, 3
+; 32BIT-NEXT:    li 3, 32
+; 32BIT-NEXT:    stxvw4x 1, 1, 3
 ; 32BIT-NEXT:    bl .vec_callee_stack[PR]
 ; 32BIT-NEXT:    nop
 ; 32BIT-NEXT:    addi 1, 1, 64
 ; 32BIT-NEXT:    lwz 0, 8(1)
 ; 32BIT-NEXT:    mtlr 0
 ; 32BIT-NEXT:    blr
-
-
+;
 ; 64BIT-LABEL: vec_caller:
 ; 64BIT:       # %bb.0: # %entry
 ; 64BIT-NEXT:    mflr 0
 ; 64BIT-NEXT:    stdu 1, -112(1)
-; 64BIT-NEXT:    ld 3, L..C0(2)
-; 64BIT-NEXT:    ld 4, L..C1(2)
+; 64BIT-NEXT:    ld 3, L..C0(2) # %const.0
 ; 64BIT-NEXT:    xxlxor 34, 34, 34
-; 64BIT-NEXT:    std 0, 128(1)
 ; 64BIT-NEXT:    xxlxor 35, 35, 35
 ; 64BIT-NEXT:    xxlxor 36, 36, 36
-; 64BIT-NEXT:    lxvw4x 0, 0, 3
-; 64BIT-NEXT:    lxvw4x 1, 0, 4
 ; 64BIT-NEXT:    xxlxor 37, 37, 37
-; 64BIT-NEXT:    li 3, 64
 ; 64BIT-NEXT:    xxlxor 38, 38, 38
-; 64BIT-NEXT:    li 4, 48
 ; 64BIT-NEXT:    xxlxor 39, 39, 39
+; 64BIT-NEXT:    std 0, 128(1)
+; 64BIT-NEXT:    lxvw4x 0, 0, 3
+; 64BIT-NEXT:    ld 3, L..C1(2) # %const.1
 ; 64BIT-NEXT:    xxlxor 40, 40, 40
-; 64BIT-NEXT:    stxvw4x 0, 1, 3
 ; 64BIT-NEXT:    xxlxor 41, 41, 41
-; 64BIT-NEXT:    stxvw4x 1, 1, 4
 ; 64BIT-NEXT:    xxlxor 42, 42, 42
 ; 64BIT-NEXT:    xxlxor 43, 43, 43
 ; 64BIT-NEXT:    xxlxor 44, 44, 44
 ; 64BIT-NEXT:    xxlxor 45, 45, 45
+; 64BIT-NEXT:    lxvw4x 1, 0, 3
+; 64BIT-NEXT:    li 3, 64
+; 64BIT-NEXT:    stxvw4x 0, 1, 3
+; 64BIT-NEXT:    li 3, 48
+; 64BIT-NEXT:    stxvw4x 1, 1, 3
 ; 64BIT-NEXT:    bl .vec_callee_stack[PR]
 ; 64BIT-NEXT:    nop
 ; 64BIT-NEXT:    addi 1, 1, 112
 ; 64BIT-NEXT:    ld 0, 16(1)
 ; 64BIT-NEXT:    mtlr 0
 ; 64BIT-NEXT:    blr
 
-; LITERAL:         .toc
-; LITERAL:       L..C0:
-; LITERAL-NEXT:    .tc L..CPI0_0[TC],L..CPI0_0
-; LITERAL-NEXT:  L..C1:
-; LITERAL-NEXT:    .tc L..CPI0_1[TC],L..CPI0_1
+
+
+
 
 entry:
   %call = call i32 @vec_callee_stack(<4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 49, i32 50, i32 51, i32 52>, <4 x i32> <i32 53, i32 54, i32 55, i32 56>)
   ret i32 %call
 }
 
 declare i32 @vec_callee_stack(...)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; LITERAL: {{.*}}

llvm/test/CodeGen/PowerPC/aix-vsx-splatimm.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr7 \
 ; RUN:   -verify-machineinstrs -O2 -mattr=vsx < %s | \
 ; RUN:    FileCheck %s --check-prefix=CHECK-AIX
 ; RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 \
 ; RUN:   -verify-machineinstrs -O2 -mattr=vsx < %s | \
 ; RUN:    FileCheck %s
 
 define void @test_aix_splatimm(i32 %arg, i32 %arg1, i32 %arg2) {
 ; CHECK-AIX-LABEL: test_aix_splatimm:
 ; CHECK-AIX:       # %bb.0: # %bb
 ; CHECK-AIX-NEXT:    bclr 12, 20, 0
 ; CHECK-AIX-NEXT:  # %bb.1: # %bb3
-; CHECK-AIX-NEXT:    srwi 4, 4, 16
-; CHECK-AIX-NEXT:    srwi 5, 5, 16
 ; CHECK-AIX-NEXT:    slwi 3, 3, 8
-; CHECK-AIX-NEXT:    mullw 4, 5, 4
 ; CHECK-AIX-NEXT:    neg 3, 3
-; CHECK-AIX-NEXT:    lwz 5, 0(3)
+; CHECK-AIX-NEXT:    lwz 6, 0(3)
 ; CHECK-AIX-NEXT:    sth 3, -16(1)
 ; CHECK-AIX-NEXT:    addi 3, 1, -16
 ; CHECK-AIX-NEXT:    lxvw4x 34, 0, 3
-; CHECK-AIX-NEXT:    srwi 5, 5, 1
-; CHECK-AIX-NEXT:    mullw 3, 4, 5
+; CHECK-AIX-NEXT:    srwi 3, 4, 16
+; CHECK-AIX-NEXT:    srwi 4, 5, 16
+; CHECK-AIX-NEXT:    mullw 3, 4, 3
+; CHECK-AIX-NEXT:    srwi 4, 6, 1
+; CHECK-AIX-NEXT:    mullw 3, 3, 4
 ; CHECK-AIX-NEXT:    li 4, 0
-; CHECK-AIX-NEXT:    vsplth 2, 2, 0
 ; CHECK-AIX-NEXT:    neg 3, 3
+; CHECK-AIX-NEXT:    vsplth 2, 2, 0
 ; CHECK-AIX-NEXT:    stxvw4x 34, 0, 4
 ; CHECK-AIX-NEXT:    sth 3, -32(1)
 ; CHECK-AIX-NEXT:    addi 3, 1, -32
 ; CHECK-AIX-NEXT:    lxvw4x 34, 0, 3
 ; CHECK-AIX-NEXT:    vsplth 2, 2, 0
 ; CHECK-AIX-NEXT:    stxvw4x 34, 0, 3
 ;
 ; CHECK-LABEL: test_aix_splatimm:

llvm/test/CodeGen/PowerPC/all-atomics.ll

 ; CHECK-NEXT:    blr
 ;
 ; AIX32-LABEL: test_op_ignore:
 ; AIX32:       # %bb.0: # %entry
 ; AIX32-NEXT:    mflr 0
 ; AIX32-NEXT:    stwu 1, -160(1)
 ; AIX32-NEXT:    lwz 3, L..C0(2) # @sc
 ; AIX32-NEXT:    stw 0, 168(1)
+; AIX32-NEXT:    rlwinm 4, 3, 3, 27, 28
 ; AIX32-NEXT:    stw 15, 92(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 26, 136(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 28, 144(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    li 15, 1
-; AIX32-NEXT:    stw 16, 96(1) # 4-byte Folded Spill
-; AIX32-NEXT:    rlwinm 4, 3, 3, 27, 28
 ; AIX32-NEXT:    rlwinm 28, 3, 0, 0, 29
 ; AIX32-NEXT:    li 3, 255
 ; AIX32-NEXT:    xori 26, 4, 24
+; AIX32-NEXT:    stw 16, 96(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 17, 100(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 18, 104(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 19, 108(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 20, 112(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 21, 116(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 22, 120(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 23, 124(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 24, 128(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 25, 132(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 27, 140(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 29, 148(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 30, 152(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 31, 156(1) # 4-byte Folded Spill
+; AIX32-NEXT:    sync
 ; AIX32-NEXT:    slw 29, 15, 26
 ; AIX32-NEXT:    slw 3, 3, 26
-; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB0_1: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 28
 ; AIX32-NEXT:    add 5, 29, 4
 ; AIX32-NEXT:    andc 4, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 4, 5, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 28

 ; AIX32-NEXT:    add 5, 18, 4
 ; AIX32-NEXT:    andc 4, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 4, 5, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 27
 ; AIX32-NEXT:    bne 0, L..BB0_3
 ; AIX32-NEXT:  # %bb.4: # %entry
 ; AIX32-NEXT:    lwz 3, L..C2(2) # @ss
-; AIX32-NEXT:    li 5, 0
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:    rlwinm 4, 3, 3, 27, 27
 ; AIX32-NEXT:    rlwinm 25, 3, 0, 0, 29
-; AIX32-NEXT:    ori 3, 5, 65535
+; AIX32-NEXT:    li 3, 0
 ; AIX32-NEXT:    xori 22, 4, 16
+; AIX32-NEXT:    ori 3, 3, 65535
 ; AIX32-NEXT:    slw 17, 15, 22
 ; AIX32-NEXT:    slw 3, 3, 22
 ; AIX32-NEXT:  L..BB0_5: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 25
 ; AIX32-NEXT:    add 5, 17, 4
 ; AIX32-NEXT:    andc 4, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 4, 5, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 25
 ; AIX32-NEXT:    bne 0, L..BB0_5
 ; AIX32-NEXT:  # %bb.6: # %entry
 ; AIX32-NEXT:    lwz 3, L..C3(2) # @us
-; AIX32-NEXT:    li 5, 0
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:    rlwinm 4, 3, 3, 27, 27
 ; AIX32-NEXT:    rlwinm 23, 3, 0, 0, 29
-; AIX32-NEXT:    ori 3, 5, 65535
-; AIX32-NEXT:    xori 19, 4, 16
-; AIX32-NEXT:    slw 16, 15, 19
-; AIX32-NEXT:    slw 3, 3, 19
+; AIX32-NEXT:    li 3, 0
+; AIX32-NEXT:    xori 21, 4, 16
+; AIX32-NEXT:    ori 3, 3, 65535
+; AIX32-NEXT:    slw 16, 15, 21
+; AIX32-NEXT:    slw 3, 3, 21
 ; AIX32-NEXT:  L..BB0_7: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 23
 ; AIX32-NEXT:    add 5, 16, 4
 ; AIX32-NEXT:    andc 4, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 4, 5, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 23
 ; AIX32-NEXT:    bne 0, L..BB0_7
 ; AIX32-NEXT:  # %bb.8: # %entry
-; AIX32-NEXT:    lwz 21, L..C4(2) # @si
 ; AIX32-NEXT:    lwsync
+; AIX32-NEXT:    lwz 20, L..C4(2) # @si
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB0_9: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 3, 0, 21
+; AIX32-NEXT:    lwarx 3, 0, 20
 ; AIX32-NEXT:    addi 3, 3, 1
-; AIX32-NEXT:    stwcx. 3, 0, 21
+; AIX32-NEXT:    stwcx. 3, 0, 20
 ; AIX32-NEXT:    bne 0, L..BB0_9
 ; AIX32-NEXT:  # %bb.10: # %entry
-; AIX32-NEXT:    lwz 20, L..C5(2) # @ui
 ; AIX32-NEXT:    lwsync
+; AIX32-NEXT:    lwz 19, L..C5(2) # @ui
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB0_11: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 3, 0, 20
+; AIX32-NEXT:    lwarx 3, 0, 19
 ; AIX32-NEXT:    addi 3, 3, 1
-; AIX32-NEXT:    stwcx. 3, 0, 20
+; AIX32-NEXT:    stwcx. 3, 0, 19
 ; AIX32-NEXT:    bne 0, L..BB0_11
 ; AIX32-NEXT:  # %bb.12: # %entry
 ; AIX32-NEXT:    lwz 31, L..C6(2) # @sll
+; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 1
 ; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    mr 3, 31
 ; AIX32-NEXT:    bl .__atomic_fetch_add_8[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    lwz 30, L..C7(2) # @ull
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 1
-; AIX32-NEXT:    li 6, 5
 ; AIX32-NEXT:    mr 3, 30
+; AIX32-NEXT:    li 6, 5
 ; AIX32-NEXT:    bl .__atomic_fetch_add_8[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    li 3, 255
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:    slw 3, 3, 26
 ; AIX32-NEXT:  L..BB0_13: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 28
 ; AIX32-NEXT:    sub 5, 4, 29
 ; AIX32-NEXT:    andc 4, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 4, 5, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 28
 ; AIX32-NEXT:    bne 0, L..BB0_13
 ; AIX32-NEXT:  # %bb.14: # %entry
 ; AIX32-NEXT:    li 3, 255
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    slw 3, 3, 24
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 3, 3, 24
 ; AIX32-NEXT:  L..BB0_15: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 27
 ; AIX32-NEXT:    sub 5, 4, 18
 ; AIX32-NEXT:    andc 4, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 4, 5, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 27
 ; AIX32-NEXT:    bne 0, L..BB0_15
 ; AIX32-NEXT:  # %bb.16: # %entry
 ; AIX32-NEXT:    li 3, 0
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    ori 3, 3, 65535
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    ori 3, 3, 65535
 ; AIX32-NEXT:    slw 3, 3, 22
 ; AIX32-NEXT:  L..BB0_17: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 25
 ; AIX32-NEXT:    sub 5, 4, 17
 ; AIX32-NEXT:    andc 4, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 4, 5, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 25
 ; AIX32-NEXT:    bne 0, L..BB0_17
 ; AIX32-NEXT:  # %bb.18: # %entry
 ; AIX32-NEXT:    li 3, 0
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    ori 3, 3, 65535
 ; AIX32-NEXT:    sync
-; AIX32-NEXT:    slw 3, 3, 19
+; AIX32-NEXT:    ori 3, 3, 65535
+; AIX32-NEXT:    slw 3, 3, 21
 ; AIX32-NEXT:  L..BB0_19: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 23
 ; AIX32-NEXT:    sub 5, 4, 16
 ; AIX32-NEXT:    andc 4, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 4, 5, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 23
 ; AIX32-NEXT:    bne 0, L..BB0_19
 ; AIX32-NEXT:  # %bb.20: # %entry
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB0_21: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 3, 0, 21
+; AIX32-NEXT:    lwarx 3, 0, 20
 ; AIX32-NEXT:    sub 3, 3, 15
-; AIX32-NEXT:    stwcx. 3, 0, 21
+; AIX32-NEXT:    stwcx. 3, 0, 20
 ; AIX32-NEXT:    bne 0, L..BB0_21
 ; AIX32-NEXT:  # %bb.22: # %entry
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB0_23: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 3, 0, 20
+; AIX32-NEXT:    lwarx 3, 0, 19
 ; AIX32-NEXT:    sub 3, 3, 15
-; AIX32-NEXT:    stwcx. 3, 0, 20
+; AIX32-NEXT:    stwcx. 3, 0, 19
 ; AIX32-NEXT:    bne 0, L..BB0_23
 ; AIX32-NEXT:  # %bb.24: # %entry
-; AIX32-NEXT:    mr 3, 31
+; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 1
+; AIX32-NEXT:    mr 3, 31
 ; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    bl .__atomic_fetch_sub_8[PR]
 ; AIX32-NEXT:    nop
-; AIX32-NEXT:    mr 3, 30
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 1
+; AIX32-NEXT:    mr 3, 30
 ; AIX32-NEXT:    li 6, 5
 ; AIX32-NEXT:    bl .__atomic_fetch_sub_8[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    li 3, 255
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:    slw 3, 3, 26
 ; AIX32-NEXT:  L..BB0_25: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 28
 ; AIX32-NEXT:    or 5, 29, 4
 ; AIX32-NEXT:    andc 4, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 4, 5, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 28
 ; AIX32-NEXT:    bne 0, L..BB0_25
 ; AIX32-NEXT:  # %bb.26: # %entry
 ; AIX32-NEXT:    li 3, 255
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    slw 3, 3, 24
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 3, 3, 24
 ; AIX32-NEXT:  L..BB0_27: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 27
 ; AIX32-NEXT:    or 5, 18, 4
 ; AIX32-NEXT:    andc 4, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 4, 5, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 27
 ; AIX32-NEXT:    bne 0, L..BB0_27
 ; AIX32-NEXT:  # %bb.28: # %entry
 ; AIX32-NEXT:    li 3, 0
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    ori 3, 3, 65535
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    ori 3, 3, 65535
 ; AIX32-NEXT:    slw 3, 3, 22
 ; AIX32-NEXT:  L..BB0_29: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 25
 ; AIX32-NEXT:    or 5, 17, 4
 ; AIX32-NEXT:    andc 4, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 4, 5, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 25
 ; AIX32-NEXT:    bne 0, L..BB0_29
 ; AIX32-NEXT:  # %bb.30: # %entry
 ; AIX32-NEXT:    li 3, 0
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    ori 3, 3, 65535
 ; AIX32-NEXT:    sync
-; AIX32-NEXT:    slw 3, 3, 19
+; AIX32-NEXT:    ori 3, 3, 65535
+; AIX32-NEXT:    slw 3, 3, 21
 ; AIX32-NEXT:  L..BB0_31: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 23
 ; AIX32-NEXT:    or 5, 16, 4
 ; AIX32-NEXT:    andc 4, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 4, 5, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 23
 ; AIX32-NEXT:    bne 0, L..BB0_31
 ; AIX32-NEXT:  # %bb.32: # %entry
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB0_33: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 3, 0, 21
+; AIX32-NEXT:    lwarx 3, 0, 20
 ; AIX32-NEXT:    ori 3, 3, 1
-; AIX32-NEXT:    stwcx. 3, 0, 21
+; AIX32-NEXT:    stwcx. 3, 0, 20
 ; AIX32-NEXT:    bne 0, L..BB0_33
 ; AIX32-NEXT:  # %bb.34: # %entry
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB0_35: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 3, 0, 20
+; AIX32-NEXT:    lwarx 3, 0, 19
 ; AIX32-NEXT:    ori 3, 3, 1
-; AIX32-NEXT:    stwcx. 3, 0, 20
+; AIX32-NEXT:    stwcx. 3, 0, 19
 ; AIX32-NEXT:    bne 0, L..BB0_35
 ; AIX32-NEXT:  # %bb.36: # %entry
-; AIX32-NEXT:    mr 3, 31
+; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 1
+; AIX32-NEXT:    mr 3, 31
 ; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    bl .__atomic_fetch_or_8[PR]
 ; AIX32-NEXT:    nop
-; AIX32-NEXT:    mr 3, 30
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 1
+; AIX32-NEXT:    mr 3, 30
 ; AIX32-NEXT:    li 6, 5
 ; AIX32-NEXT:    bl .__atomic_fetch_or_8[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    li 3, 255
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:    slw 3, 3, 26
 ; AIX32-NEXT:  L..BB0_37: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 28
 ; AIX32-NEXT:    xor 5, 29, 4
 ; AIX32-NEXT:    andc 4, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 4, 5, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 28
 ; AIX32-NEXT:    bne 0, L..BB0_37
 ; AIX32-NEXT:  # %bb.38: # %entry
 ; AIX32-NEXT:    li 3, 255
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    slw 3, 3, 24
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 3, 3, 24
 ; AIX32-NEXT:  L..BB0_39: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 27
 ; AIX32-NEXT:    xor 5, 18, 4
 ; AIX32-NEXT:    andc 4, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 4, 5, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 27
 ; AIX32-NEXT:    bne 0, L..BB0_39
 ; AIX32-NEXT:  # %bb.40: # %entry
 ; AIX32-NEXT:    li 3, 0
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    ori 3, 3, 65535
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    ori 3, 3, 65535
 ; AIX32-NEXT:    slw 3, 3, 22
 ; AIX32-NEXT:  L..BB0_41: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 25
 ; AIX32-NEXT:    xor 5, 17, 4
 ; AIX32-NEXT:    andc 4, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 4, 5, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 25
 ; AIX32-NEXT:    bne 0, L..BB0_41
 ; AIX32-NEXT:  # %bb.42: # %entry
 ; AIX32-NEXT:    li 3, 0
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    ori 3, 3, 65535
 ; AIX32-NEXT:    sync
-; AIX32-NEXT:    slw 3, 3, 19
+; AIX32-NEXT:    ori 3, 3, 65535
+; AIX32-NEXT:    slw 3, 3, 21
 ; AIX32-NEXT:  L..BB0_43: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 23
 ; AIX32-NEXT:    xor 5, 16, 4
 ; AIX32-NEXT:    andc 4, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 4, 5, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 23
 ; AIX32-NEXT:    bne 0, L..BB0_43
 ; AIX32-NEXT:  # %bb.44: # %entry
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB0_45: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 3, 0, 21
+; AIX32-NEXT:    lwarx 3, 0, 20
 ; AIX32-NEXT:    xori 3, 3, 1
-; AIX32-NEXT:    stwcx. 3, 0, 21
+; AIX32-NEXT:    stwcx. 3, 0, 20
 ; AIX32-NEXT:    bne 0, L..BB0_45
 ; AIX32-NEXT:  # %bb.46: # %entry
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB0_47: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 3, 0, 20
+; AIX32-NEXT:    lwarx 3, 0, 19
 ; AIX32-NEXT:    xori 3, 3, 1
-; AIX32-NEXT:    stwcx. 3, 0, 20
+; AIX32-NEXT:    stwcx. 3, 0, 19
 ; AIX32-NEXT:    bne 0, L..BB0_47
 ; AIX32-NEXT:  # %bb.48: # %entry
-; AIX32-NEXT:    mr 3, 31
+; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 1
+; AIX32-NEXT:    mr 3, 31
 ; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    bl .__atomic_fetch_xor_8[PR]
 ; AIX32-NEXT:    nop
-; AIX32-NEXT:    mr 3, 30
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 1
+; AIX32-NEXT:    mr 3, 30
 ; AIX32-NEXT:    li 6, 5
 ; AIX32-NEXT:    bl .__atomic_fetch_xor_8[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    lwz 31, L..C8(2) # @u128
 ; AIX32-NEXT:    addi 30, 1, 72
 ; AIX32-NEXT:    addi 29, 1, 56
 ; AIX32-NEXT:    lwz 5, 12(31)
-; AIX32-NEXT:    lwz 3, 8(31)
-; AIX32-NEXT:    lwz 4, 4(31)
-; AIX32-NEXT:    lwz 9, 0(31)
+; AIX32-NEXT:    lwz 4, 8(31)
+; AIX32-NEXT:    lwz 6, 4(31)
+; AIX32-NEXT:    lwz 7, 0(31)
 ; AIX32-NEXT:    .align 4
 ; AIX32-NEXT:  L..BB0_49: # %atomicrmw.start
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    xori 6, 5, 1
-; AIX32-NEXT:    stw 4, 76(1)
+; AIX32-NEXT:    xori 3, 5, 1
+; AIX32-NEXT:    stw 7, 72(1)
+; AIX32-NEXT:    stw 7, 56(1)
 ; AIX32-NEXT:    li 7, 5
-; AIX32-NEXT:    stw 3, 80(1)
-; AIX32-NEXT:    stw 5, 84(1)
-; AIX32-NEXT:    stw 3, 64(1)
-; AIX32-NEXT:    stw 4, 60(1)
-; AIX32-NEXT:    stw 6, 68(1)
+; AIX32-NEXT:    stw 3, 68(1)
 ; AIX32-NEXT:    li 3, 16
+; AIX32-NEXT:    li 8, 5
+; AIX32-NEXT:    stw 6, 76(1)
+; AIX32-NEXT:    stw 4, 80(1)
+; AIX32-NEXT:    stw 5, 84(1)
+; AIX32-NEXT:    stw 4, 64(1)
+; AIX32-NEXT:    stw 6, 60(1)
 ; AIX32-NEXT:    mr 4, 31
 ; AIX32-NEXT:    mr 5, 30
 ; AIX32-NEXT:    mr 6, 29
-; AIX32-NEXT:    li 8, 5
-; AIX32-NEXT:    stw 9, 72(1)
-; AIX32-NEXT:    stw 9, 56(1)
 ; AIX32-NEXT:    bl .__atomic_compare_exchange[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    cmplwi 3, 0
 ; AIX32-NEXT:    lwz 5, 84(1)
-; AIX32-NEXT:    lwz 3, 80(1)
-; AIX32-NEXT:    lwz 4, 76(1)
-; AIX32-NEXT:    lwz 9, 72(1)
+; AIX32-NEXT:    lwz 4, 80(1)
+; AIX32-NEXT:    lwz 6, 76(1)
+; AIX32-NEXT:    lwz 7, 72(1)
 ; AIX32-NEXT:    beq 0, L..BB0_49
 ; AIX32-NEXT:  # %bb.50: # %atomicrmw.end
 ; AIX32-NEXT:    lwz 31, L..C9(2) # @s128
 ; AIX32-NEXT:    addi 30, 1, 72
 ; AIX32-NEXT:    addi 29, 1, 56
 ; AIX32-NEXT:    lwz 5, 12(31)
-; AIX32-NEXT:    lwz 3, 8(31)
-; AIX32-NEXT:    lwz 4, 4(31)
-; AIX32-NEXT:    lwz 9, 0(31)
+; AIX32-NEXT:    lwz 4, 8(31)
+; AIX32-NEXT:    lwz 6, 4(31)
+; AIX32-NEXT:    lwz 7, 0(31)
 ; AIX32-NEXT:    .align 4
 ; AIX32-NEXT:  L..BB0_51: # %atomicrmw.start2
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    xori 6, 5, 1
-; AIX32-NEXT:    stw 4, 76(1)
+; AIX32-NEXT:    xori 3, 5, 1
+; AIX32-NEXT:    stw 7, 72(1)
+; AIX32-NEXT:    stw 7, 56(1)
 ; AIX32-NEXT:    li 7, 5
-; AIX32-NEXT:    stw 3, 80(1)
-; AIX32-NEXT:    stw 5, 84(1)
-; AIX32-NEXT:    stw 3, 64(1)
-; AIX32-NEXT:    stw 4, 60(1)
-; AIX32-NEXT:    stw 6, 68(1)
+; AIX32-NEXT:    stw 3, 68(1)
 ; AIX32-NEXT:    li 3, 16
+; AIX32-NEXT:    li 8, 5
+; AIX32-NEXT:    stw 6, 76(1)
+; AIX32-NEXT:    stw 4, 80(1)
+; AIX32-NEXT:    stw 5, 84(1)
+; AIX32-NEXT:    stw 4, 64(1)
+; AIX32-NEXT:    stw 6, 60(1)
 ; AIX32-NEXT:    mr 4, 31
 ; AIX32-NEXT:    mr 5, 30
 ; AIX32-NEXT:    mr 6, 29
-; AIX32-NEXT:    li 8, 5
-; AIX32-NEXT:    stw 9, 72(1)
-; AIX32-NEXT:    stw 9, 56(1)
 ; AIX32-NEXT:    bl .__atomic_compare_exchange[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    cmplwi 3, 0
 ; AIX32-NEXT:    lwz 5, 84(1)
-; AIX32-NEXT:    lwz 3, 80(1)
-; AIX32-NEXT:    lwz 4, 76(1)
-; AIX32-NEXT:    lwz 9, 72(1)
+; AIX32-NEXT:    lwz 4, 80(1)
+; AIX32-NEXT:    lwz 6, 76(1)
+; AIX32-NEXT:    lwz 7, 72(1)
 ; AIX32-NEXT:    beq 0, L..BB0_51
 ; AIX32-NEXT:  # %bb.52: # %atomicrmw.end1
 ; AIX32-NEXT:    li 29, 1
 ; AIX32-NEXT:    li 3, 255
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:    slw 18, 29, 26
 ; AIX32-NEXT:    slw 3, 3, 26
 ; AIX32-NEXT:  L..BB0_53: # %atomicrmw.end1
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 28
 ; AIX32-NEXT:    nand 5, 18, 4
 ; AIX32-NEXT:    andc 4, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 4, 5, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 28
 ; AIX32-NEXT:    bne 0, L..BB0_53
 ; AIX32-NEXT:  # %bb.54: # %atomicrmw.end1
 ; AIX32-NEXT:    li 3, 255
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    slw 17, 29, 24
-; AIX32-NEXT:    slw 3, 3, 24
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 3, 3, 24
 ; AIX32-NEXT:  L..BB0_55: # %atomicrmw.end1
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 27
 ; AIX32-NEXT:    nand 5, 17, 4
 ; AIX32-NEXT:    andc 4, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 4, 5, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 27
 ; AIX32-NEXT:    bne 0, L..BB0_55
 ; AIX32-NEXT:  # %bb.56: # %atomicrmw.end1
 ; AIX32-NEXT:    li 3, 0
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    slw 16, 29, 22
-; AIX32-NEXT:    ori 3, 3, 65535
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    ori 3, 3, 65535
 ; AIX32-NEXT:    slw 3, 3, 22
 ; AIX32-NEXT:  L..BB0_57: # %atomicrmw.end1
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 25
 ; AIX32-NEXT:    nand 5, 16, 4
 ; AIX32-NEXT:    andc 4, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 4, 5, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 25
 ; AIX32-NEXT:    bne 0, L..BB0_57
 ; AIX32-NEXT:  # %bb.58: # %atomicrmw.end1
 ; AIX32-NEXT:    li 3, 0
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    slw 15, 29, 19
-; AIX32-NEXT:    ori 3, 3, 65535
+; AIX32-NEXT:    slw 15, 29, 21
 ; AIX32-NEXT:    sync
-; AIX32-NEXT:    slw 3, 3, 19
+; AIX32-NEXT:    ori 3, 3, 65535
+; AIX32-NEXT:    slw 3, 3, 21
 ; AIX32-NEXT:  L..BB0_59: # %atomicrmw.end1
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 23
 ; AIX32-NEXT:    nand 5, 15, 4
 ; AIX32-NEXT:    andc 4, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 4, 5, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 23
 ; AIX32-NEXT:    bne 0, L..BB0_59
 ; AIX32-NEXT:  # %bb.60: # %atomicrmw.end1
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB0_61: # %atomicrmw.end1
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 3, 0, 21
+; AIX32-NEXT:    lwarx 3, 0, 20
 ; AIX32-NEXT:    nand 3, 29, 3
-; AIX32-NEXT:    stwcx. 3, 0, 21
+; AIX32-NEXT:    stwcx. 3, 0, 20
 ; AIX32-NEXT:    bne 0, L..BB0_61
 ; AIX32-NEXT:  # %bb.62: # %atomicrmw.end1
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB0_63: # %atomicrmw.end1
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 3, 0, 20
+; AIX32-NEXT:    lwarx 3, 0, 19
 ; AIX32-NEXT:    nand 3, 29, 3
-; AIX32-NEXT:    stwcx. 3, 0, 20
+; AIX32-NEXT:    stwcx. 3, 0, 19
 ; AIX32-NEXT:    bne 0, L..BB0_63
 ; AIX32-NEXT:  # %bb.64: # %atomicrmw.end1
 ; AIX32-NEXT:    lwz 31, L..C6(2) # @sll
+; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 1
 ; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    mr 3, 31
 ; AIX32-NEXT:    bl .__atomic_fetch_nand_8[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    lwz 30, L..C7(2) # @ull
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 1
-; AIX32-NEXT:    li 6, 5
 ; AIX32-NEXT:    mr 3, 30
+; AIX32-NEXT:    li 6, 5
 ; AIX32-NEXT:    bl .__atomic_fetch_nand_8[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    li 3, 255
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:    slw 3, 3, 26
 ; AIX32-NEXT:  L..BB0_65: # %atomicrmw.end1
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 28
 ; AIX32-NEXT:    and 5, 18, 4
 ; AIX32-NEXT:    andc 4, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 4, 5, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 28
 ; AIX32-NEXT:    bne 0, L..BB0_65
 ; AIX32-NEXT:  # %bb.66: # %atomicrmw.end1
 ; AIX32-NEXT:    li 3, 255
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    slw 3, 3, 24
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 3, 3, 24
 ; AIX32-NEXT:  L..BB0_67: # %atomicrmw.end1
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 27
 ; AIX32-NEXT:    and 5, 17, 4
 ; AIX32-NEXT:    andc 4, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 4, 5, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 27
 ; AIX32-NEXT:    bne 0, L..BB0_67
 ; AIX32-NEXT:  # %bb.68: # %atomicrmw.end1
 ; AIX32-NEXT:    li 3, 0
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    ori 3, 3, 65535
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    ori 3, 3, 65535
 ; AIX32-NEXT:    slw 3, 3, 22
 ; AIX32-NEXT:  L..BB0_69: # %atomicrmw.end1
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 25
 ; AIX32-NEXT:    and 5, 16, 4
 ; AIX32-NEXT:    andc 4, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 4, 5, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 25
 ; AIX32-NEXT:    bne 0, L..BB0_69
 ; AIX32-NEXT:  # %bb.70: # %atomicrmw.end1
 ; AIX32-NEXT:    li 3, 0
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    ori 3, 3, 65535
 ; AIX32-NEXT:    sync
-; AIX32-NEXT:    slw 3, 3, 19
+; AIX32-NEXT:    ori 3, 3, 65535
+; AIX32-NEXT:    slw 3, 3, 21
 ; AIX32-NEXT:  L..BB0_71: # %atomicrmw.end1
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 23
 ; AIX32-NEXT:    and 5, 15, 4
 ; AIX32-NEXT:    andc 4, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 4, 5, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 23
 ; AIX32-NEXT:    bne 0, L..BB0_71
 ; AIX32-NEXT:  # %bb.72: # %atomicrmw.end1
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB0_73: # %atomicrmw.end1
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 3, 0, 21
+; AIX32-NEXT:    lwarx 3, 0, 20
 ; AIX32-NEXT:    and 3, 29, 3
-; AIX32-NEXT:    stwcx. 3, 0, 21
+; AIX32-NEXT:    stwcx. 3, 0, 20
 ; AIX32-NEXT:    bne 0, L..BB0_73
 ; AIX32-NEXT:  # %bb.74: # %atomicrmw.end1
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB0_75: # %atomicrmw.end1
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 3, 0, 20
+; AIX32-NEXT:    lwarx 3, 0, 19
 ; AIX32-NEXT:    and 3, 29, 3
-; AIX32-NEXT:    stwcx. 3, 0, 20
+; AIX32-NEXT:    stwcx. 3, 0, 19
 ; AIX32-NEXT:    bne 0, L..BB0_75
 ; AIX32-NEXT:  # %bb.76: # %atomicrmw.end1
-; AIX32-NEXT:    mr 3, 31
+; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 1
+; AIX32-NEXT:    mr 3, 31
 ; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    bl .__atomic_fetch_and_8[PR]
 ; AIX32-NEXT:    nop
-; AIX32-NEXT:    mr 3, 30
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 1
+; AIX32-NEXT:    mr 3, 30
 ; AIX32-NEXT:    li 6, 5
 ; AIX32-NEXT:    bl .__atomic_fetch_and_8[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    lwz 31, 156(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 30, 152(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 29, 148(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 28, 144(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 27, 140(1) # 4-byte Folded Reload

 ; CHECK-NEXT:    blr
 ;
 ; AIX32-LABEL: test_fetch_and_op:
 ; AIX32:       # %bb.0: # %entry
 ; AIX32-NEXT:    mflr 0
 ; AIX32-NEXT:    stwu 1, -144(1)
 ; AIX32-NEXT:    lwz 4, L..C0(2) # @sc
 ; AIX32-NEXT:    stw 0, 152(1)
-; AIX32-NEXT:    stw 26, 120(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    li 7, 11
+; AIX32-NEXT:    stw 26, 120(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 13, 68(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 14, 72(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 15, 76(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    rlwinm 3, 4, 3, 27, 28
 ; AIX32-NEXT:    stw 16, 80(1) # 4-byte Folded Spill
-; AIX32-NEXT:    xori 26, 3, 24
-; AIX32-NEXT:    li 3, 255
 ; AIX32-NEXT:    stw 17, 84(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 18, 88(1) # 4-byte Folded Spill
+; AIX32-NEXT:    xori 26, 3, 24
+; AIX32-NEXT:    li 3, 255
+; AIX32-NEXT:    slw 3, 3, 26
 ; AIX32-NEXT:    stw 19, 92(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 20, 96(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 21, 100(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 22, 104(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 23, 108(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 24, 112(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 25, 116(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 27, 124(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 28, 128(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 29, 132(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 30, 136(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 31, 140(1) # 4-byte Folded Spill
-; AIX32-NEXT:    stw 4, 64(1) # 4-byte Folded Spill
-; AIX32-NEXT:    rlwinm 24, 4, 0, 0, 29
-; AIX32-NEXT:    slw 23, 7, 26
-; AIX32-NEXT:    slw 4, 3, 26
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    rlwinm 25, 4, 0, 0, 29
+; AIX32-NEXT:    slw 24, 7, 26
+; AIX32-NEXT:    stw 4, 64(1) # 4-byte Folded Spill
 ; AIX32-NEXT:  L..BB1_1: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 3, 0, 24
-; AIX32-NEXT:    add 5, 23, 3
-; AIX32-NEXT:    andc 6, 3, 4
-; AIX32-NEXT:    and 5, 5, 4
+; AIX32-NEXT:    lwarx 4, 0, 25
+; AIX32-NEXT:    add 5, 24, 4
+; AIX32-NEXT:    andc 6, 4, 3
+; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 5, 5, 6
-; AIX32-NEXT:    stwcx. 5, 0, 24
+; AIX32-NEXT:    stwcx. 5, 0, 25
 ; AIX32-NEXT:    bne 0, L..BB1_1
 ; AIX32-NEXT:  # %bb.2: # %entry
-; AIX32-NEXT:    lwz 27, L..C1(2) # @uc
+; AIX32-NEXT:    srw 3, 4, 26
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    srw 3, 3, 26
+; AIX32-NEXT:    lwz 27, L..C1(2) # @uc
 ; AIX32-NEXT:    lwz 4, 64(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    clrlwi 3, 3, 24
+; AIX32-NEXT:    rlwinm 21, 27, 0, 0, 29
 ; AIX32-NEXT:    stb 3, 0(4)
 ; AIX32-NEXT:    rlwinm 3, 27, 3, 27, 28
+; AIX32-NEXT:    sync
 ; AIX32-NEXT:    xori 22, 3, 24
 ; AIX32-NEXT:    li 3, 255
-; AIX32-NEXT:    sync
-; AIX32-NEXT:    rlwinm 21, 27, 0, 0, 29
-; AIX32-NEXT:    slw 19, 7, 22
+; AIX32-NEXT:    slw 20, 7, 22
 ; AIX32-NEXT:    slw 3, 3, 22
 ; AIX32-NEXT:  L..BB1_3: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 21
-; AIX32-NEXT:    add 5, 19, 4
+; AIX32-NEXT:    add 5, 20, 4
 ; AIX32-NEXT:    andc 6, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 5, 5, 6
 ; AIX32-NEXT:    stwcx. 5, 0, 21
 ; AIX32-NEXT:    bne 0, L..BB1_3
 ; AIX32-NEXT:  # %bb.4: # %entry
-; AIX32-NEXT:    lwz 25, L..C2(2) # @ss
 ; AIX32-NEXT:    srw 3, 4, 22
+; AIX32-NEXT:    lwz 23, L..C2(2) # @ss
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    clrlwi 3, 3, 24
+; AIX32-NEXT:    rlwinm 17, 23, 0, 0, 29
 ; AIX32-NEXT:    stb 3, 0(27)
-; AIX32-NEXT:    rlwinm 3, 25, 3, 27, 27
-; AIX32-NEXT:    rlwinm 17, 25, 0, 0, 29
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    rlwinm 3, 23, 3, 27, 27
 ; AIX32-NEXT:    xori 18, 3, 16
-; AIX32-NEXT:    ori 3, 4, 65535
+; AIX32-NEXT:    li 3, 0
+; AIX32-NEXT:    ori 3, 3, 65535
 ; AIX32-NEXT:    slw 16, 7, 18
 ; AIX32-NEXT:    slw 3, 3, 18
 ; AIX32-NEXT:  L..BB1_5: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 17
 ; AIX32-NEXT:    add 5, 16, 4
 ; AIX32-NEXT:    andc 6, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 5, 5, 6
 ; AIX32-NEXT:    stwcx. 5, 0, 17
 ; AIX32-NEXT:    bne 0, L..BB1_5
 ; AIX32-NEXT:  # %bb.6: # %entry
-; AIX32-NEXT:    lwz 20, L..C3(2) # @us
 ; AIX32-NEXT:    srw 3, 4, 18
+; AIX32-NEXT:    lwz 19, L..C3(2) # @us
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    clrlwi 3, 3, 16
-; AIX32-NEXT:    sth 3, 0(25)
-; AIX32-NEXT:    rlwinm 3, 20, 3, 27, 27
-; AIX32-NEXT:    rlwinm 13, 20, 0, 0, 29
+; AIX32-NEXT:    rlwinm 14, 19, 0, 0, 29
+; AIX32-NEXT:    sth 3, 0(23)
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    rlwinm 3, 19, 3, 27, 27
 ; AIX32-NEXT:    xori 15, 3, 16
-; AIX32-NEXT:    ori 3, 4, 65535
-; AIX32-NEXT:    slw 29, 7, 15
+; AIX32-NEXT:    li 3, 0
+; AIX32-NEXT:    ori 3, 3, 65535
+; AIX32-NEXT:    slw 13, 7, 15
 ; AIX32-NEXT:    slw 3, 3, 15
 ; AIX32-NEXT:  L..BB1_7: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 4, 0, 13
-; AIX32-NEXT:    add 5, 29, 4
+; AIX32-NEXT:    lwarx 4, 0, 14
+; AIX32-NEXT:    add 5, 13, 4
 ; AIX32-NEXT:    andc 6, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 5, 5, 6
-; AIX32-NEXT:    stwcx. 5, 0, 13
+; AIX32-NEXT:    stwcx. 5, 0, 14
 ; AIX32-NEXT:    bne 0, L..BB1_7
 ; AIX32-NEXT:  # %bb.8: # %entry
 ; AIX32-NEXT:    srw 3, 4, 15
-; AIX32-NEXT:    lwz 28, L..C4(2) # @si
 ; AIX32-NEXT:    lwsync
+; AIX32-NEXT:    lwz 29, L..C4(2) # @si
 ; AIX32-NEXT:    clrlwi 3, 3, 16
-; AIX32-NEXT:    sth 3, 0(20)
+; AIX32-NEXT:    sth 3, 0(19)
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB1_9: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 3, 0, 28
+; AIX32-NEXT:    lwarx 3, 0, 29
 ; AIX32-NEXT:    addi 4, 3, 11
-; AIX32-NEXT:    stwcx. 4, 0, 28
+; AIX32-NEXT:    stwcx. 4, 0, 29
 ; AIX32-NEXT:    bne 0, L..BB1_9
 ; AIX32-NEXT:  # %bb.10: # %entry
-; AIX32-NEXT:    lwz 14, L..C5(2) # @ui
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    stw 3, 0(28)
+; AIX32-NEXT:    stw 3, 0(29)
+; AIX32-NEXT:    lwz 28, L..C5(2) # @ui
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB1_11: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 3, 0, 14
+; AIX32-NEXT:    lwarx 3, 0, 28
 ; AIX32-NEXT:    addi 4, 3, 11
-; AIX32-NEXT:    stwcx. 4, 0, 14
+; AIX32-NEXT:    stwcx. 4, 0, 28
 ; AIX32-NEXT:    bne 0, L..BB1_11
 ; AIX32-NEXT:  # %bb.12: # %entry
 ; AIX32-NEXT:    lwz 31, L..C6(2) # @sll
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    stw 3, 0(14)
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 11
 ; AIX32-NEXT:    li 6, 5
+; AIX32-NEXT:    stw 3, 0(28)
 ; AIX32-NEXT:    mr 3, 31
 ; AIX32-NEXT:    bl .__atomic_fetch_add_8[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    lwz 30, L..C7(2) # @ull
-; AIX32-NEXT:    mr 7, 3
-; AIX32-NEXT:    mr 8, 4
+; AIX32-NEXT:    stw 4, 4(31)
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 11
 ; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    stw 8, 4(31)
-; AIX32-NEXT:    stw 7, 0(31)
+; AIX32-NEXT:    stw 3, 0(31)
 ; AIX32-NEXT:    mr 3, 30
 ; AIX32-NEXT:    bl .__atomic_fetch_add_8[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    li 5, 255
 ; AIX32-NEXT:    stw 4, 4(30)
 ; AIX32-NEXT:    stw 3, 0(30)
-; AIX32-NEXT:    slw 3, 5, 26
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 3, 5, 26
 ; AIX32-NEXT:  L..BB1_13: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 4, 0, 24
-; AIX32-NEXT:    sub 5, 4, 23
+; AIX32-NEXT:    lwarx 4, 0, 25
+; AIX32-NEXT:    sub 5, 4, 24
 ; AIX32-NEXT:    andc 6, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 5, 5, 6
-; AIX32-NEXT:    stwcx. 5, 0, 24
+; AIX32-NEXT:    stwcx. 5, 0, 25
 ; AIX32-NEXT:    bne 0, L..BB1_13
 ; AIX32-NEXT:  # %bb.14: # %entry
-; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    srw 3, 4, 26
+; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    lwz 4, 64(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    clrlwi 3, 3, 24
 ; AIX32-NEXT:    stb 3, 0(4)
 ; AIX32-NEXT:    li 3, 255
-; AIX32-NEXT:    slw 3, 3, 22
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 3, 3, 22
 ; AIX32-NEXT:  L..BB1_15: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 21
-; AIX32-NEXT:    sub 5, 4, 19
+; AIX32-NEXT:    sub 5, 4, 20
 ; AIX32-NEXT:    andc 6, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 5, 5, 6
 ; AIX32-NEXT:    stwcx. 5, 0, 21
 ; AIX32-NEXT:    bne 0, L..BB1_15
 ; AIX32-NEXT:  # %bb.16: # %entry
 ; AIX32-NEXT:    srw 3, 4, 22
-; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    li 8, 11
+; AIX32-NEXT:    li 7, 11
 ; AIX32-NEXT:    clrlwi 3, 3, 24
 ; AIX32-NEXT:    stb 3, 0(27)
-; AIX32-NEXT:    ori 3, 4, 65535
-; AIX32-NEXT:    slw 3, 3, 18
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    li 3, 0
+; AIX32-NEXT:    ori 3, 3, 65535
+; AIX32-NEXT:    slw 3, 3, 18
 ; AIX32-NEXT:  L..BB1_17: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 17
 ; AIX32-NEXT:    sub 5, 4, 16
 ; AIX32-NEXT:    andc 6, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 5, 5, 6
 ; AIX32-NEXT:    stwcx. 5, 0, 17
 ; AIX32-NEXT:    bne 0, L..BB1_17
 ; AIX32-NEXT:  # %bb.18: # %entry
 ; AIX32-NEXT:    srw 3, 4, 18
-; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    clrlwi 3, 3, 16
-; AIX32-NEXT:    sth 3, 0(25)
-; AIX32-NEXT:    ori 3, 4, 65535
-; AIX32-NEXT:    slw 3, 3, 15
+; AIX32-NEXT:    sth 3, 0(23)
+; AIX32-NEXT:    li 3, 0
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    ori 3, 3, 65535
+; AIX32-NEXT:    slw 3, 3, 15
 ; AIX32-NEXT:  L..BB1_19: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 4, 0, 13
-; AIX32-NEXT:    sub 5, 4, 29
+; AIX32-NEXT:    lwarx 4, 0, 14
+; AIX32-NEXT:    sub 5, 4, 13
 ; AIX32-NEXT:    andc 6, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 5, 5, 6
-; AIX32-NEXT:    stwcx. 5, 0, 13
+; AIX32-NEXT:    stwcx. 5, 0, 14
 ; AIX32-NEXT:    bne 0, L..BB1_19
 ; AIX32-NEXT:  # %bb.20: # %entry
 ; AIX32-NEXT:    srw 3, 4, 15
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    clrlwi 3, 3, 16
-; AIX32-NEXT:    sth 3, 0(20)
+; AIX32-NEXT:    sth 3, 0(19)
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB1_21: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 3, 0, 28
-; AIX32-NEXT:    sub 4, 3, 8
-; AIX32-NEXT:    stwcx. 4, 0, 28
+; AIX32-NEXT:    lwarx 3, 0, 29
+; AIX32-NEXT:    sub 4, 3, 7
+; AIX32-NEXT:    stwcx. 4, 0, 29
 ; AIX32-NEXT:    bne 0, L..BB1_21
 ; AIX32-NEXT:  # %bb.22: # %entry
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    stw 3, 0(28)
+; AIX32-NEXT:    stw 3, 0(29)
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB1_23: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 7, 0, 14
-; AIX32-NEXT:    sub 3, 7, 8
-; AIX32-NEXT:    stwcx. 3, 0, 14
+; AIX32-NEXT:    lwarx 3, 0, 28
+; AIX32-NEXT:    sub 4, 3, 7
+; AIX32-NEXT:    stwcx. 4, 0, 28
 ; AIX32-NEXT:    bne 0, L..BB1_23
 ; AIX32-NEXT:  # %bb.24: # %entry
-; AIX32-NEXT:    mr 3, 31
+; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 11
 ; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    stw 7, 0(14)
+; AIX32-NEXT:    stw 3, 0(28)
+; AIX32-NEXT:    mr 3, 31
 ; AIX32-NEXT:    bl .__atomic_fetch_sub_8[PR]
 ; AIX32-NEXT:    nop
-; AIX32-NEXT:    mr 7, 3
-; AIX32-NEXT:    mr 8, 4
-; AIX32-NEXT:    mr 3, 30
+; AIX32-NEXT:    stw 4, 4(31)
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 11
 ; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    stw 8, 4(31)
-; AIX32-NEXT:    stw 7, 0(31)
+; AIX32-NEXT:    stw 3, 0(31)
+; AIX32-NEXT:    mr 3, 30
 ; AIX32-NEXT:    bl .__atomic_fetch_sub_8[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    li 5, 255
 ; AIX32-NEXT:    stw 4, 4(30)
 ; AIX32-NEXT:    stw 3, 0(30)
-; AIX32-NEXT:    slw 3, 5, 26
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 3, 5, 26
 ; AIX32-NEXT:  L..BB1_25: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 4, 0, 24
-; AIX32-NEXT:    or 5, 23, 4
+; AIX32-NEXT:    lwarx 4, 0, 25
+; AIX32-NEXT:    or 5, 24, 4
 ; AIX32-NEXT:    andc 6, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 5, 5, 6
-; AIX32-NEXT:    stwcx. 5, 0, 24
+; AIX32-NEXT:    stwcx. 5, 0, 25
 ; AIX32-NEXT:    bne 0, L..BB1_25
 ; AIX32-NEXT:  # %bb.26: # %entry
-; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    srw 3, 4, 26
+; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    lwz 4, 64(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    clrlwi 3, 3, 24
 ; AIX32-NEXT:    stb 3, 0(4)
 ; AIX32-NEXT:    li 3, 255
-; AIX32-NEXT:    slw 3, 3, 22
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 3, 3, 22
 ; AIX32-NEXT:  L..BB1_27: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 21
-; AIX32-NEXT:    or 5, 19, 4
+; AIX32-NEXT:    or 5, 20, 4
 ; AIX32-NEXT:    andc 6, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 5, 5, 6
 ; AIX32-NEXT:    stwcx. 5, 0, 21
 ; AIX32-NEXT:    bne 0, L..BB1_27
 ; AIX32-NEXT:  # %bb.28: # %entry
 ; AIX32-NEXT:    srw 3, 4, 22
-; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    clrlwi 3, 3, 24
 ; AIX32-NEXT:    stb 3, 0(27)
-; AIX32-NEXT:    ori 3, 4, 65535
-; AIX32-NEXT:    slw 3, 3, 18
+; AIX32-NEXT:    li 3, 0
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    ori 3, 3, 65535
+; AIX32-NEXT:    slw 3, 3, 18
 ; AIX32-NEXT:  L..BB1_29: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 17
 ; AIX32-NEXT:    or 5, 16, 4
 ; AIX32-NEXT:    andc 6, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 5, 5, 6
 ; AIX32-NEXT:    stwcx. 5, 0, 17
 ; AIX32-NEXT:    bne 0, L..BB1_29
 ; AIX32-NEXT:  # %bb.30: # %entry
 ; AIX32-NEXT:    srw 3, 4, 18
-; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    clrlwi 3, 3, 16
-; AIX32-NEXT:    sth 3, 0(25)
-; AIX32-NEXT:    ori 3, 4, 65535
-; AIX32-NEXT:    slw 3, 3, 15
+; AIX32-NEXT:    sth 3, 0(23)
+; AIX32-NEXT:    li 3, 0
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    ori 3, 3, 65535
+; AIX32-NEXT:    slw 3, 3, 15
 ; AIX32-NEXT:  L..BB1_31: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 4, 0, 13
-; AIX32-NEXT:    or 5, 29, 4
+; AIX32-NEXT:    lwarx 4, 0, 14
+; AIX32-NEXT:    or 5, 13, 4
 ; AIX32-NEXT:    andc 6, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 5, 5, 6
-; AIX32-NEXT:    stwcx. 5, 0, 13
+; AIX32-NEXT:    stwcx. 5, 0, 14
 ; AIX32-NEXT:    bne 0, L..BB1_31
 ; AIX32-NEXT:  # %bb.32: # %entry
 ; AIX32-NEXT:    srw 3, 4, 15
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    clrlwi 3, 3, 16
-; AIX32-NEXT:    sth 3, 0(20)
+; AIX32-NEXT:    sth 3, 0(19)
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB1_33: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 3, 0, 28
+; AIX32-NEXT:    lwarx 3, 0, 29
 ; AIX32-NEXT:    ori 4, 3, 11
-; AIX32-NEXT:    stwcx. 4, 0, 28
+; AIX32-NEXT:    stwcx. 4, 0, 29
 ; AIX32-NEXT:    bne 0, L..BB1_33
 ; AIX32-NEXT:  # %bb.34: # %entry
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    stw 3, 0(28)
+; AIX32-NEXT:    stw 3, 0(29)
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB1_35: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 7, 0, 14
-; AIX32-NEXT:    ori 3, 7, 11
-; AIX32-NEXT:    stwcx. 3, 0, 14
+; AIX32-NEXT:    lwarx 3, 0, 28
+; AIX32-NEXT:    ori 4, 3, 11
+; AIX32-NEXT:    stwcx. 4, 0, 28
 ; AIX32-NEXT:    bne 0, L..BB1_35
 ; AIX32-NEXT:  # %bb.36: # %entry
-; AIX32-NEXT:    mr 3, 31
+; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 11
 ; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    stw 7, 0(14)
+; AIX32-NEXT:    stw 3, 0(28)
+; AIX32-NEXT:    mr 3, 31
 ; AIX32-NEXT:    bl .__atomic_fetch_or_8[PR]
 ; AIX32-NEXT:    nop
-; AIX32-NEXT:    mr 7, 3
-; AIX32-NEXT:    mr 8, 4
-; AIX32-NEXT:    mr 3, 30
+; AIX32-NEXT:    stw 4, 4(31)
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 11
 ; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    stw 8, 4(31)
-; AIX32-NEXT:    stw 7, 0(31)
+; AIX32-NEXT:    stw 3, 0(31)
+; AIX32-NEXT:    mr 3, 30
 ; AIX32-NEXT:    bl .__atomic_fetch_or_8[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    li 5, 255
 ; AIX32-NEXT:    stw 4, 4(30)
 ; AIX32-NEXT:    stw 3, 0(30)
-; AIX32-NEXT:    slw 3, 5, 26
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 3, 5, 26
 ; AIX32-NEXT:  L..BB1_37: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 4, 0, 24
-; AIX32-NEXT:    xor 5, 23, 4
+; AIX32-NEXT:    lwarx 4, 0, 25
+; AIX32-NEXT:    xor 5, 24, 4
 ; AIX32-NEXT:    andc 6, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 5, 5, 6
-; AIX32-NEXT:    stwcx. 5, 0, 24
+; AIX32-NEXT:    stwcx. 5, 0, 25
 ; AIX32-NEXT:    bne 0, L..BB1_37
 ; AIX32-NEXT:  # %bb.38: # %entry
-; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    srw 3, 4, 26
+; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    lwz 4, 64(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    clrlwi 3, 3, 24
 ; AIX32-NEXT:    stb 3, 0(4)
 ; AIX32-NEXT:    li 3, 255
-; AIX32-NEXT:    slw 3, 3, 22
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 3, 3, 22
 ; AIX32-NEXT:  L..BB1_39: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 21
-; AIX32-NEXT:    xor 5, 19, 4
+; AIX32-NEXT:    xor 5, 20, 4
 ; AIX32-NEXT:    andc 6, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 5, 5, 6
 ; AIX32-NEXT:    stwcx. 5, 0, 21
 ; AIX32-NEXT:    bne 0, L..BB1_39
 ; AIX32-NEXT:  # %bb.40: # %entry
 ; AIX32-NEXT:    srw 3, 4, 22
-; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    clrlwi 3, 3, 24
 ; AIX32-NEXT:    stb 3, 0(27)
-; AIX32-NEXT:    ori 3, 4, 65535
-; AIX32-NEXT:    slw 3, 3, 18
+; AIX32-NEXT:    li 3, 0
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    ori 3, 3, 65535
+; AIX32-NEXT:    slw 3, 3, 18
 ; AIX32-NEXT:  L..BB1_41: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 17
 ; AIX32-NEXT:    xor 5, 16, 4
 ; AIX32-NEXT:    andc 6, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 5, 5, 6
 ; AIX32-NEXT:    stwcx. 5, 0, 17
 ; AIX32-NEXT:    bne 0, L..BB1_41
 ; AIX32-NEXT:  # %bb.42: # %entry
 ; AIX32-NEXT:    srw 3, 4, 18
-; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    clrlwi 3, 3, 16
-; AIX32-NEXT:    sth 3, 0(25)
-; AIX32-NEXT:    ori 3, 4, 65535
-; AIX32-NEXT:    slw 3, 3, 15
+; AIX32-NEXT:    sth 3, 0(23)
+; AIX32-NEXT:    li 3, 0
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    ori 3, 3, 65535
+; AIX32-NEXT:    slw 3, 3, 15
 ; AIX32-NEXT:  L..BB1_43: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 4, 0, 13
-; AIX32-NEXT:    xor 5, 29, 4
+; AIX32-NEXT:    lwarx 4, 0, 14
+; AIX32-NEXT:    xor 5, 13, 4
 ; AIX32-NEXT:    andc 6, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 5, 5, 6
-; AIX32-NEXT:    stwcx. 5, 0, 13
+; AIX32-NEXT:    stwcx. 5, 0, 14
 ; AIX32-NEXT:    bne 0, L..BB1_43
 ; AIX32-NEXT:  # %bb.44: # %entry
 ; AIX32-NEXT:    srw 3, 4, 15
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    clrlwi 3, 3, 16
-; AIX32-NEXT:    sth 3, 0(20)
+; AIX32-NEXT:    sth 3, 0(19)
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB1_45: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 3, 0, 28
+; AIX32-NEXT:    lwarx 3, 0, 29
 ; AIX32-NEXT:    xori 4, 3, 11
-; AIX32-NEXT:    stwcx. 4, 0, 28
+; AIX32-NEXT:    stwcx. 4, 0, 29
 ; AIX32-NEXT:    bne 0, L..BB1_45
 ; AIX32-NEXT:  # %bb.46: # %entry
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    stw 3, 0(28)
+; AIX32-NEXT:    stw 3, 0(29)
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB1_47: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 7, 0, 14
-; AIX32-NEXT:    xori 3, 7, 11
-; AIX32-NEXT:    stwcx. 3, 0, 14
+; AIX32-NEXT:    lwarx 3, 0, 28
+; AIX32-NEXT:    xori 4, 3, 11
+; AIX32-NEXT:    stwcx. 4, 0, 28
 ; AIX32-NEXT:    bne 0, L..BB1_47
 ; AIX32-NEXT:  # %bb.48: # %entry
-; AIX32-NEXT:    mr 3, 31
+; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 11
 ; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    stw 7, 0(14)
+; AIX32-NEXT:    stw 3, 0(28)
+; AIX32-NEXT:    mr 3, 31
 ; AIX32-NEXT:    bl .__atomic_fetch_xor_8[PR]
 ; AIX32-NEXT:    nop
-; AIX32-NEXT:    mr 7, 3
-; AIX32-NEXT:    mr 8, 4
-; AIX32-NEXT:    mr 3, 30
+; AIX32-NEXT:    stw 4, 4(31)
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 11
 ; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    stw 8, 4(31)
-; AIX32-NEXT:    stw 7, 0(31)
+; AIX32-NEXT:    stw 3, 0(31)
+; AIX32-NEXT:    mr 3, 30
 ; AIX32-NEXT:    bl .__atomic_fetch_xor_8[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    li 5, 255
 ; AIX32-NEXT:    stw 4, 4(30)
 ; AIX32-NEXT:    stw 3, 0(30)
-; AIX32-NEXT:    slw 3, 5, 26
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 3, 5, 26
 ; AIX32-NEXT:  L..BB1_49: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 4, 0, 24
-; AIX32-NEXT:    nand 5, 23, 4
+; AIX32-NEXT:    lwarx 4, 0, 25
+; AIX32-NEXT:    nand 5, 24, 4
 ; AIX32-NEXT:    andc 6, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 5, 5, 6
-; AIX32-NEXT:    stwcx. 5, 0, 24
+; AIX32-NEXT:    stwcx. 5, 0, 25
 ; AIX32-NEXT:    bne 0, L..BB1_49
 ; AIX32-NEXT:  # %bb.50: # %entry
-; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    srw 3, 4, 26
-; AIX32-NEXT:    li 8, 11
+; AIX32-NEXT:    lwsync
+; AIX32-NEXT:    li 7, 11
 ; AIX32-NEXT:    lwz 4, 64(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    clrlwi 3, 3, 24
 ; AIX32-NEXT:    stb 3, 0(4)
+; AIX32-NEXT:    sync
 ; AIX32-NEXT:    li 3, 255
 ; AIX32-NEXT:    slw 3, 3, 22
-; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB1_51: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 21
-; AIX32-NEXT:    nand 5, 19, 4
+; AIX32-NEXT:    nand 5, 20, 4
 ; AIX32-NEXT:    andc 6, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 5, 5, 6
 ; AIX32-NEXT:    stwcx. 5, 0, 21
 ; AIX32-NEXT:    bne 0, L..BB1_51
 ; AIX32-NEXT:  # %bb.52: # %entry
 ; AIX32-NEXT:    srw 3, 4, 22
-; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    clrlwi 3, 3, 24
 ; AIX32-NEXT:    stb 3, 0(27)
-; AIX32-NEXT:    ori 3, 4, 65535
-; AIX32-NEXT:    slw 3, 3, 18
+; AIX32-NEXT:    li 3, 0
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    ori 3, 3, 65535
+; AIX32-NEXT:    slw 3, 3, 18
 ; AIX32-NEXT:  L..BB1_53: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 17
 ; AIX32-NEXT:    nand 5, 16, 4
 ; AIX32-NEXT:    andc 6, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 5, 5, 6
 ; AIX32-NEXT:    stwcx. 5, 0, 17
 ; AIX32-NEXT:    bne 0, L..BB1_53
 ; AIX32-NEXT:  # %bb.54: # %entry
 ; AIX32-NEXT:    srw 3, 4, 18
-; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    clrlwi 3, 3, 16
-; AIX32-NEXT:    sth 3, 0(25)
-; AIX32-NEXT:    ori 3, 4, 65535
-; AIX32-NEXT:    slw 3, 3, 15
+; AIX32-NEXT:    sth 3, 0(23)
+; AIX32-NEXT:    li 3, 0
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    ori 3, 3, 65535
+; AIX32-NEXT:    slw 3, 3, 15
 ; AIX32-NEXT:  L..BB1_55: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 4, 0, 13
-; AIX32-NEXT:    nand 5, 29, 4
+; AIX32-NEXT:    lwarx 4, 0, 14
+; AIX32-NEXT:    nand 5, 13, 4
 ; AIX32-NEXT:    andc 6, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 5, 5, 6
-; AIX32-NEXT:    stwcx. 5, 0, 13
+; AIX32-NEXT:    stwcx. 5, 0, 14
 ; AIX32-NEXT:    bne 0, L..BB1_55
 ; AIX32-NEXT:  # %bb.56: # %entry
 ; AIX32-NEXT:    srw 3, 4, 15
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    clrlwi 3, 3, 16
-; AIX32-NEXT:    sth 3, 0(20)
+; AIX32-NEXT:    sth 3, 0(19)
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB1_57: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 3, 0, 28
-; AIX32-NEXT:    nand 4, 8, 3
-; AIX32-NEXT:    stwcx. 4, 0, 28
+; AIX32-NEXT:    lwarx 3, 0, 29
+; AIX32-NEXT:    nand 4, 7, 3
+; AIX32-NEXT:    stwcx. 4, 0, 29
 ; AIX32-NEXT:    bne 0, L..BB1_57
 ; AIX32-NEXT:  # %bb.58: # %entry
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    stw 3, 0(28)
+; AIX32-NEXT:    stw 3, 0(29)
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB1_59: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 7, 0, 14
-; AIX32-NEXT:    nand 3, 8, 7
-; AIX32-NEXT:    stwcx. 3, 0, 14
+; AIX32-NEXT:    lwarx 3, 0, 28
+; AIX32-NEXT:    nand 4, 7, 3
+; AIX32-NEXT:    stwcx. 4, 0, 28
 ; AIX32-NEXT:    bne 0, L..BB1_59
 ; AIX32-NEXT:  # %bb.60: # %entry
-; AIX32-NEXT:    mr 3, 31
+; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 11
 ; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    stw 7, 0(14)
+; AIX32-NEXT:    stw 3, 0(28)
+; AIX32-NEXT:    mr 3, 31
 ; AIX32-NEXT:    bl .__atomic_fetch_nand_8[PR]
 ; AIX32-NEXT:    nop
-; AIX32-NEXT:    mr 7, 3
-; AIX32-NEXT:    mr 8, 4
-; AIX32-NEXT:    mr 3, 30
+; AIX32-NEXT:    stw 4, 4(31)
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 11
 ; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    stw 8, 4(31)
-; AIX32-NEXT:    stw 7, 0(31)
+; AIX32-NEXT:    stw 3, 0(31)
+; AIX32-NEXT:    mr 3, 30
 ; AIX32-NEXT:    bl .__atomic_fetch_nand_8[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    li 5, 255
 ; AIX32-NEXT:    stw 4, 4(30)
 ; AIX32-NEXT:    stw 3, 0(30)
-; AIX32-NEXT:    slw 3, 5, 26
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 3, 5, 26
 ; AIX32-NEXT:  L..BB1_61: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 4, 0, 24
-; AIX32-NEXT:    and 5, 23, 4
+; AIX32-NEXT:    lwarx 4, 0, 25
+; AIX32-NEXT:    and 5, 24, 4
 ; AIX32-NEXT:    andc 6, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 5, 5, 6
-; AIX32-NEXT:    stwcx. 5, 0, 24
+; AIX32-NEXT:    stwcx. 5, 0, 25
 ; AIX32-NEXT:    bne 0, L..BB1_61
 ; AIX32-NEXT:  # %bb.62: # %entry
-; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    srw 3, 4, 26
+; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    lwz 4, 64(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    clrlwi 3, 3, 24
 ; AIX32-NEXT:    stb 3, 0(4)
 ; AIX32-NEXT:    li 3, 255
-; AIX32-NEXT:    slw 3, 3, 22
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 3, 3, 22
 ; AIX32-NEXT:  L..BB1_63: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 21
-; AIX32-NEXT:    and 5, 19, 4
+; AIX32-NEXT:    and 5, 20, 4
 ; AIX32-NEXT:    andc 6, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 5, 5, 6
 ; AIX32-NEXT:    stwcx. 5, 0, 21
 ; AIX32-NEXT:    bne 0, L..BB1_63
 ; AIX32-NEXT:  # %bb.64: # %entry
 ; AIX32-NEXT:    srw 3, 4, 22
-; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    li 8, 11
+; AIX32-NEXT:    li 7, 11
 ; AIX32-NEXT:    clrlwi 3, 3, 24
 ; AIX32-NEXT:    stb 3, 0(27)
-; AIX32-NEXT:    ori 3, 4, 65535
-; AIX32-NEXT:    slw 3, 3, 18
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    li 3, 0
+; AIX32-NEXT:    ori 3, 3, 65535
+; AIX32-NEXT:    slw 3, 3, 18
 ; AIX32-NEXT:  L..BB1_65: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 17
 ; AIX32-NEXT:    and 5, 16, 4
 ; AIX32-NEXT:    andc 6, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 5, 5, 6
 ; AIX32-NEXT:    stwcx. 5, 0, 17
 ; AIX32-NEXT:    bne 0, L..BB1_65
 ; AIX32-NEXT:  # %bb.66: # %entry
 ; AIX32-NEXT:    srw 3, 4, 18
-; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    clrlwi 3, 3, 16
-; AIX32-NEXT:    sth 3, 0(25)
-; AIX32-NEXT:    ori 3, 4, 65535
-; AIX32-NEXT:    slw 3, 3, 15
+; AIX32-NEXT:    sth 3, 0(23)
+; AIX32-NEXT:    li 3, 0
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    ori 3, 3, 65535
+; AIX32-NEXT:    slw 3, 3, 15
 ; AIX32-NEXT:  L..BB1_67: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 4, 0, 13
-; AIX32-NEXT:    and 5, 29, 4
+; AIX32-NEXT:    lwarx 4, 0, 14
+; AIX32-NEXT:    and 5, 13, 4
 ; AIX32-NEXT:    andc 6, 4, 3
 ; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    or 5, 5, 6
-; AIX32-NEXT:    stwcx. 5, 0, 13
+; AIX32-NEXT:    stwcx. 5, 0, 14
 ; AIX32-NEXT:    bne 0, L..BB1_67
 ; AIX32-NEXT:  # %bb.68: # %entry
 ; AIX32-NEXT:    srw 3, 4, 15
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    clrlwi 3, 3, 16
-; AIX32-NEXT:    sth 3, 0(20)
+; AIX32-NEXT:    sth 3, 0(19)
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB1_69: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 3, 0, 28
-; AIX32-NEXT:    and 4, 8, 3
-; AIX32-NEXT:    stwcx. 4, 0, 28
+; AIX32-NEXT:    lwarx 3, 0, 29
+; AIX32-NEXT:    and 4, 7, 3
+; AIX32-NEXT:    stwcx. 4, 0, 29
 ; AIX32-NEXT:    bne 0, L..BB1_69
 ; AIX32-NEXT:  # %bb.70: # %entry
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    stw 3, 0(28)
+; AIX32-NEXT:    stw 3, 0(29)
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB1_71: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 7, 0, 14
-; AIX32-NEXT:    and 3, 8, 7
-; AIX32-NEXT:    stwcx. 3, 0, 14
+; AIX32-NEXT:    lwarx 3, 0, 28
+; AIX32-NEXT:    and 4, 7, 3
+; AIX32-NEXT:    stwcx. 4, 0, 28
 ; AIX32-NEXT:    bne 0, L..BB1_71
 ; AIX32-NEXT:  # %bb.72: # %entry
-; AIX32-NEXT:    mr 3, 31
+; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 11
 ; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    stw 7, 0(14)
+; AIX32-NEXT:    stw 3, 0(28)
+; AIX32-NEXT:    mr 3, 31
 ; AIX32-NEXT:    bl .__atomic_fetch_and_8[PR]
 ; AIX32-NEXT:    nop
-; AIX32-NEXT:    mr 7, 3
-; AIX32-NEXT:    mr 8, 4
-; AIX32-NEXT:    mr 3, 30
+; AIX32-NEXT:    stw 4, 4(31)
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 11
 ; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    stw 8, 4(31)
-; AIX32-NEXT:    stw 7, 0(31)
+; AIX32-NEXT:    stw 3, 0(31)
+; AIX32-NEXT:    mr 3, 30
 ; AIX32-NEXT:    bl .__atomic_fetch_and_8[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    stw 4, 4(30)
 ; AIX32-NEXT:    stw 3, 0(30)
 ; AIX32-NEXT:    lwz 31, 140(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 30, 136(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 29, 132(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 28, 128(1) # 4-byte Folded Reload

 ; CHECK-NEXT:    ld 16, -128(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    blr
 ;
 ; AIX32-LABEL: test_op_and_fetch:
 ; AIX32:       # %bb.0: # %entry
 ; AIX32-NEXT:    mflr 0
 ; AIX32-NEXT:    stwu 1, -176(1)
 ; AIX32-NEXT:    stw 0, 184(1)
-; AIX32-NEXT:    stw 24, 144(1) # 4-byte Folded Spill
-; AIX32-NEXT:    lwz 24, L..C0(2) # @sc
+; AIX32-NEXT:    stw 27, 156(1) # 4-byte Folded Spill
+; AIX32-NEXT:    lwz 27, L..C0(2) # @sc
 ; AIX32-NEXT:    stw 26, 152(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    lwz 26, L..C1(2) # @uc
-; AIX32-NEXT:    stw 23, 140(1) # 4-byte Folded Spill
+; AIX32-NEXT:    lbz 3, 0(26)
+; AIX32-NEXT:    rlwinm 4, 27, 3, 27, 28
+; AIX32-NEXT:    stw 24, 144(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    li 5, 255
 ; AIX32-NEXT:    stw 13, 100(1) # 4-byte Folded Spill
-; AIX32-NEXT:    rlwinm 4, 24, 3, 27, 28
 ; AIX32-NEXT:    stw 14, 104(1) # 4-byte Folded Spill
-; AIX32-NEXT:    lbz 3, 0(26)
-; AIX32-NEXT:    xori 23, 4, 24
 ; AIX32-NEXT:    stw 15, 108(1) # 4-byte Folded Spill
+; AIX32-NEXT:    xori 24, 4, 24
 ; AIX32-NEXT:    stw 16, 112(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 17, 116(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 18, 120(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 19, 124(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 20, 128(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 21, 132(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 22, 136(1) # 4-byte Folded Spill
+; AIX32-NEXT:    stw 23, 140(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 25, 148(1) # 4-byte Folded Spill
-; AIX32-NEXT:    stw 27, 156(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 28, 160(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 29, 164(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 30, 168(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 31, 172(1) # 4-byte Folded Spill
-; AIX32-NEXT:    rlwinm 22, 24, 0, 0, 29
-; AIX32-NEXT:    li 25, -1
-; AIX32-NEXT:    slw 4, 3, 23
-; AIX32-NEXT:    slw 6, 5, 23
+; AIX32-NEXT:    li 17, -1
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    rlwinm 22, 27, 0, 0, 29
+; AIX32-NEXT:    slw 4, 3, 24
+; AIX32-NEXT:    slw 5, 5, 24
 ; AIX32-NEXT:  L..BB2_1: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 5, 0, 22
-; AIX32-NEXT:    add 7, 4, 5
-; AIX32-NEXT:    andc 8, 5, 6
-; AIX32-NEXT:    and 7, 7, 6
+; AIX32-NEXT:    lwarx 6, 0, 22
+; AIX32-NEXT:    add 7, 4, 6
+; AIX32-NEXT:    andc 8, 6, 5
+; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:    or 7, 7, 8
 ; AIX32-NEXT:    stwcx. 7, 0, 22
 ; AIX32-NEXT:    bne 0, L..BB2_1
 ; AIX32-NEXT:  # %bb.2: # %entry
-; AIX32-NEXT:    srw 4, 5, 23
+; AIX32-NEXT:    srw 4, 6, 24
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    rlwinm 5, 26, 3, 27, 28
-; AIX32-NEXT:    clrlwi 4, 4, 24
-; AIX32-NEXT:    xori 21, 5, 24
 ; AIX32-NEXT:    li 5, 255
-; AIX32-NEXT:    add 4, 4, 3
-; AIX32-NEXT:    lbz 3, 0(26)
 ; AIX32-NEXT:    rlwinm 19, 26, 0, 0, 29
-; AIX32-NEXT:    stb 4, 0(24)
+; AIX32-NEXT:    clrlwi 4, 4, 24
+; AIX32-NEXT:    add 3, 4, 3
+; AIX32-NEXT:    rlwinm 4, 26, 3, 27, 28
+; AIX32-NEXT:    stb 3, 0(27)
+; AIX32-NEXT:    lbz 3, 0(26)
+; AIX32-NEXT:    xori 21, 4, 24
+; AIX32-NEXT:    sync
 ; AIX32-NEXT:    slw 5, 5, 21
 ; AIX32-NEXT:    slw 4, 3, 21
-; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB2_3: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 6, 0, 19
 ; AIX32-NEXT:    add 7, 4, 6
 ; AIX32-NEXT:    andc 8, 6, 5
 ; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:    or 7, 7, 8
 ; AIX32-NEXT:    stwcx. 7, 0, 19
 ; AIX32-NEXT:    bne 0, L..BB2_3
 ; AIX32-NEXT:  # %bb.4: # %entry
-; AIX32-NEXT:    lwz 9, L..C2(2) # @ss
 ; AIX32-NEXT:    srw 4, 6, 21
+; AIX32-NEXT:    lwz 23, L..C2(2) # @ss
 ; AIX32-NEXT:    li 5, 0
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    clrlwi 4, 4, 24
 ; AIX32-NEXT:    ori 5, 5, 65535
+; AIX32-NEXT:    rlwinm 16, 23, 0, 0, 29
 ; AIX32-NEXT:    add 3, 4, 3
-; AIX32-NEXT:    rlwinm 4, 9, 3, 27, 27
+; AIX32-NEXT:    rlwinm 4, 23, 3, 27, 27
+; AIX32-NEXT:    xori 18, 4, 16
 ; AIX32-NEXT:    stb 3, 0(26)
 ; AIX32-NEXT:    clrlwi 3, 3, 24
-; AIX32-NEXT:    xori 18, 4, 16
 ; AIX32-NEXT:    sync
-; AIX32-NEXT:    rlwinm 17, 9, 0, 0, 29
 ; AIX32-NEXT:    slw 4, 3, 18
 ; AIX32-NEXT:    slw 5, 5, 18
 ; AIX32-NEXT:  L..BB2_5: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 6, 0, 17
+; AIX32-NEXT:    lwarx 6, 0, 16
 ; AIX32-NEXT:    add 7, 4, 6
 ; AIX32-NEXT:    andc 8, 6, 5
 ; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:    or 7, 7, 8
-; AIX32-NEXT:    stwcx. 7, 0, 17
+; AIX32-NEXT:    stwcx. 7, 0, 16
 ; AIX32-NEXT:    bne 0, L..BB2_5
 ; AIX32-NEXT:  # %bb.6: # %entry
 ; AIX32-NEXT:    srw 4, 6, 18
 ; AIX32-NEXT:    lwz 20, L..C3(2) # @us
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    li 5, 0
 ; AIX32-NEXT:    clrlwi 4, 4, 16
 ; AIX32-NEXT:    ori 5, 5, 65535
+; AIX32-NEXT:    rlwinm 14, 20, 0, 0, 29
 ; AIX32-NEXT:    add 3, 4, 3
-; AIX32-NEXT:    sth 3, 0(9)
-; AIX32-NEXT:    lbz 3, 0(26)
 ; AIX32-NEXT:    rlwinm 4, 20, 3, 27, 27
 ; AIX32-NEXT:    xori 15, 4, 16
-; AIX32-NEXT:    rlwinm 14, 20, 0, 0, 29
+; AIX32-NEXT:    sth 3, 0(23)
+; AIX32-NEXT:    lbz 3, 0(26)
 ; AIX32-NEXT:    sync
-; AIX32-NEXT:    slw 4, 3, 15
 ; AIX32-NEXT:    slw 5, 5, 15
+; AIX32-NEXT:    slw 4, 3, 15
 ; AIX32-NEXT:  L..BB2_7: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 6, 0, 14
 ; AIX32-NEXT:    add 7, 4, 6
 ; AIX32-NEXT:    andc 8, 6, 5
 ; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:    or 7, 7, 8
 ; AIX32-NEXT:    stwcx. 7, 0, 14

 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB2_9: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 13
 ; AIX32-NEXT:    add 4, 3, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 13
 ; AIX32-NEXT:    bne 0, L..BB2_9
 ; AIX32-NEXT:  # %bb.10: # %entry
-; AIX32-NEXT:    stw 9, 60(1) # 4-byte Folded Spill
-; AIX32-NEXT:    lwz 16, L..C5(2) # @ui
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    stw 4, 0(13)
+; AIX32-NEXT:    lwz 25, L..C5(2) # @ui
 ; AIX32-NEXT:    lbz 3, 0(26)
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB2_11: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 4, 0, 16
+; AIX32-NEXT:    lwarx 4, 0, 25
 ; AIX32-NEXT:    add 4, 3, 4
-; AIX32-NEXT:    stwcx. 4, 0, 16
+; AIX32-NEXT:    stwcx. 4, 0, 25
 ; AIX32-NEXT:    bne 0, L..BB2_11
 ; AIX32-NEXT:  # %bb.12: # %entry
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    lwz 31, L..C6(2) # @sll
-; AIX32-NEXT:    stw 4, 0(16)
+; AIX32-NEXT:    stw 4, 0(25)
+; AIX32-NEXT:    lbz 30, 0(26)
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    lbz 29, 0(26)
-; AIX32-NEXT:    li 27, 0
+; AIX32-NEXT:    li 28, 0
 ; AIX32-NEXT:    mr 3, 31
-; AIX32-NEXT:    mr 5, 29
+; AIX32-NEXT:    mr 5, 30
 ; AIX32-NEXT:    bl .__atomic_fetch_add_8[PR]
 ; AIX32-NEXT:    nop
+; AIX32-NEXT:    addc 4, 4, 30
+; AIX32-NEXT:    lbz 29, 0(26)
 ; AIX32-NEXT:    lwz 30, L..C7(2) # @ull
-; AIX32-NEXT:    lbz 28, 0(26)
-; AIX32-NEXT:    addc 7, 4, 29
-; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    addze 8, 3
-; AIX32-NEXT:    stw 7, 4(31)
-; AIX32-NEXT:    mr 5, 28
-; AIX32-NEXT:    stw 8, 0(31)
+; AIX32-NEXT:    addze 3, 3
+; AIX32-NEXT:    stw 4, 4(31)
+; AIX32-NEXT:    li 4, 0
+; AIX32-NEXT:    stw 3, 0(31)
 ; AIX32-NEXT:    mr 3, 30
+; AIX32-NEXT:    mr 5, 29
 ; AIX32-NEXT:    bl .__atomic_fetch_add_8[PR]
 ; AIX32-NEXT:    nop
-; AIX32-NEXT:    lbz 5, 0(26)
-; AIX32-NEXT:    addc 4, 4, 28
+; AIX32-NEXT:    addc 4, 4, 29
+; AIX32-NEXT:    li 5, 255
 ; AIX32-NEXT:    addze 3, 3
-; AIX32-NEXT:    stw 4, 4(30)
-; AIX32-NEXT:    li 4, 255
 ; AIX32-NEXT:    stw 3, 0(30)
-; AIX32-NEXT:    slw 3, 5, 23
-; AIX32-NEXT:    slw 4, 4, 23
+; AIX32-NEXT:    lbz 3, 0(26)
+; AIX32-NEXT:    slw 5, 5, 24
+; AIX32-NEXT:    stw 4, 4(30)
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 4, 3, 24
 ; AIX32-NEXT:  L..BB2_13: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 6, 0, 22
-; AIX32-NEXT:    sub 7, 6, 3
-; AIX32-NEXT:    andc 8, 6, 4
-; AIX32-NEXT:    and 7, 7, 4
+; AIX32-NEXT:    sub 7, 6, 4
+; AIX32-NEXT:    andc 8, 6, 5
+; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:    or 7, 7, 8
 ; AIX32-NEXT:    stwcx. 7, 0, 22
 ; AIX32-NEXT:    bne 0, L..BB2_13
 ; AIX32-NEXT:  # %bb.14: # %entry
-; AIX32-NEXT:    srw 3, 6, 23
+; AIX32-NEXT:    srw 4, 6, 24
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    clrlwi 3, 3, 24
-; AIX32-NEXT:    sub 4, 3, 5
-; AIX32-NEXT:    lbz 3, 0(26)
 ; AIX32-NEXT:    li 5, 255
-; AIX32-NEXT:    stb 4, 0(24)
+; AIX32-NEXT:    clrlwi 4, 4, 24
 ; AIX32-NEXT:    slw 5, 5, 21
-; AIX32-NEXT:    slw 4, 3, 21
+; AIX32-NEXT:    sub 3, 4, 3
+; AIX32-NEXT:    stb 3, 0(27)
+; AIX32-NEXT:    lbz 3, 0(26)
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 4, 3, 21
 ; AIX32-NEXT:  L..BB2_15: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 6, 0, 19
 ; AIX32-NEXT:    sub 7, 6, 4
 ; AIX32-NEXT:    andc 8, 6, 5
 ; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:    or 7, 7, 8
 ; AIX32-NEXT:    stwcx. 7, 0, 19
 ; AIX32-NEXT:    bne 0, L..BB2_15
 ; AIX32-NEXT:  # %bb.16: # %entry
 ; AIX32-NEXT:    srw 4, 6, 21
+; AIX32-NEXT:    li 5, 0
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    clrlwi 4, 4, 24
+; AIX32-NEXT:    ori 5, 5, 65535
 ; AIX32-NEXT:    sub 3, 4, 3
-; AIX32-NEXT:    li 4, 0
+; AIX32-NEXT:    slw 5, 5, 18
 ; AIX32-NEXT:    stb 3, 0(26)
+; AIX32-NEXT:    sync
 ; AIX32-NEXT:    clrlwi 3, 3, 24
-; AIX32-NEXT:    ori 5, 4, 65535
 ; AIX32-NEXT:    slw 4, 3, 18
-; AIX32-NEXT:    slw 5, 5, 18
-; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB2_17: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 6, 0, 17
+; AIX32-NEXT:    lwarx 6, 0, 16
 ; AIX32-NEXT:    sub 7, 6, 4
 ; AIX32-NEXT:    andc 8, 6, 5
 ; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:    or 7, 7, 8
-; AIX32-NEXT:    stwcx. 7, 0, 17
+; AIX32-NEXT:    stwcx. 7, 0, 16
 ; AIX32-NEXT:    bne 0, L..BB2_17
 ; AIX32-NEXT:  # %bb.18: # %entry
 ; AIX32-NEXT:    srw 4, 6, 18
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    li 5, 0
 ; AIX32-NEXT:    clrlwi 4, 4, 16
-; AIX32-NEXT:    lwz 6, 60(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    ori 5, 5, 65535
-; AIX32-NEXT:    sub 4, 4, 3
-; AIX32-NEXT:    lbz 3, 0(26)
+; AIX32-NEXT:    sub 3, 4, 3
 ; AIX32-NEXT:    slw 5, 5, 15
-; AIX32-NEXT:    sth 4, 0(6)
-; AIX32-NEXT:    slw 4, 3, 15
+; AIX32-NEXT:    sth 3, 0(23)
+; AIX32-NEXT:    lbz 3, 0(26)
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 4, 3, 15
 ; AIX32-NEXT:  L..BB2_19: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 6, 0, 14
 ; AIX32-NEXT:    sub 7, 6, 4
 ; AIX32-NEXT:    andc 8, 6, 5
 ; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:    or 7, 7, 8
 ; AIX32-NEXT:    stwcx. 7, 0, 14

 ; AIX32-NEXT:    bne 0, L..BB2_21
 ; AIX32-NEXT:  # %bb.22: # %entry
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    stw 4, 0(13)
 ; AIX32-NEXT:    lbz 3, 0(26)
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB2_23: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 4, 0, 16
-; AIX32-NEXT:    sub 7, 4, 3
-; AIX32-NEXT:    stwcx. 7, 0, 16
+; AIX32-NEXT:    lwarx 4, 0, 25
+; AIX32-NEXT:    sub 4, 4, 3
+; AIX32-NEXT:    stwcx. 4, 0, 25
 ; AIX32-NEXT:    bne 0, L..BB2_23
 ; AIX32-NEXT:  # %bb.24: # %entry
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    mr 3, 31
+; AIX32-NEXT:    stw 4, 0(25)
 ; AIX32-NEXT:    li 4, 0
-; AIX32-NEXT:    li 6, 5
 ; AIX32-NEXT:    lbz 29, 0(26)
-; AIX32-NEXT:    stw 7, 0(16)
+; AIX32-NEXT:    li 6, 5
+; AIX32-NEXT:    mr 3, 31
 ; AIX32-NEXT:    mr 5, 29
 ; AIX32-NEXT:    bl .__atomic_fetch_sub_8[PR]
 ; AIX32-NEXT:    nop
-; AIX32-NEXT:    lbz 28, 0(26)
-; AIX32-NEXT:    subc 7, 4, 29
-; AIX32-NEXT:    li 4, 0
+; AIX32-NEXT:    subc 4, 4, 29
+; AIX32-NEXT:    lbz 29, 0(26)
 ; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    subfe 8, 27, 3
+; AIX32-NEXT:    mr 5, 29
+; AIX32-NEXT:    subfe 3, 28, 3
+; AIX32-NEXT:    stw 4, 4(31)
+; AIX32-NEXT:    li 4, 0
+; AIX32-NEXT:    stw 3, 0(31)
 ; AIX32-NEXT:    mr 3, 30
-; AIX32-NEXT:    mr 5, 28
-; AIX32-NEXT:    stw 7, 4(31)
-; AIX32-NEXT:    stw 8, 0(31)
 ; AIX32-NEXT:    bl .__atomic_fetch_sub_8[PR]
 ; AIX32-NEXT:    nop
-; AIX32-NEXT:    lbz 5, 0(26)
-; AIX32-NEXT:    subc 4, 4, 28
-; AIX32-NEXT:    subfe 3, 27, 3
+; AIX32-NEXT:    subc 4, 4, 29
+; AIX32-NEXT:    li 5, 255
+; AIX32-NEXT:    subfe 3, 28, 3
 ; AIX32-NEXT:    stw 4, 4(30)
-; AIX32-NEXT:    li 4, 255
+; AIX32-NEXT:    slw 5, 5, 24
 ; AIX32-NEXT:    stw 3, 0(30)
-; AIX32-NEXT:    slw 3, 5, 23
-; AIX32-NEXT:    slw 4, 4, 23
+; AIX32-NEXT:    lbz 3, 0(26)
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 4, 3, 24
 ; AIX32-NEXT:  L..BB2_25: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 6, 0, 22
-; AIX32-NEXT:    or 7, 3, 6
-; AIX32-NEXT:    andc 8, 6, 4
-; AIX32-NEXT:    and 7, 7, 4
+; AIX32-NEXT:    or 7, 4, 6
+; AIX32-NEXT:    andc 8, 6, 5
+; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:    or 7, 7, 8
 ; AIX32-NEXT:    stwcx. 7, 0, 22
 ; AIX32-NEXT:    bne 0, L..BB2_25
 ; AIX32-NEXT:  # %bb.26: # %entry
-; AIX32-NEXT:    srw 3, 6, 23
+; AIX32-NEXT:    srw 4, 6, 24
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    clrlwi 3, 3, 24
-; AIX32-NEXT:    or 4, 3, 5
-; AIX32-NEXT:    lbz 3, 0(26)
 ; AIX32-NEXT:    li 5, 255
-; AIX32-NEXT:    stb 4, 0(24)
+; AIX32-NEXT:    clrlwi 4, 4, 24
 ; AIX32-NEXT:    slw 5, 5, 21
+; AIX32-NEXT:    or 3, 4, 3
+; AIX32-NEXT:    stb 3, 0(27)
+; AIX32-NEXT:    lbz 3, 0(26)
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:    slw 4, 3, 21
-; AIX32-NEXT:    lwz 27, 60(1) # 4-byte Folded Reload
 ; AIX32-NEXT:  L..BB2_27: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 6, 0, 19
 ; AIX32-NEXT:    or 7, 4, 6
 ; AIX32-NEXT:    andc 8, 6, 5
 ; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:    or 7, 7, 8
 ; AIX32-NEXT:    stwcx. 7, 0, 19
 ; AIX32-NEXT:    bne 0, L..BB2_27
 ; AIX32-NEXT:  # %bb.28: # %entry
 ; AIX32-NEXT:    srw 4, 6, 21
+; AIX32-NEXT:    li 5, 0
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    clrlwi 4, 4, 24
+; AIX32-NEXT:    ori 5, 5, 65535
 ; AIX32-NEXT:    or 3, 4, 3
-; AIX32-NEXT:    li 4, 0
+; AIX32-NEXT:    slw 5, 5, 18
 ; AIX32-NEXT:    stb 3, 0(26)
+; AIX32-NEXT:    sync
 ; AIX32-NEXT:    clrlwi 3, 3, 24
-; AIX32-NEXT:    ori 5, 4, 65535
 ; AIX32-NEXT:    slw 4, 3, 18
-; AIX32-NEXT:    slw 5, 5, 18
-; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB2_29: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 6, 0, 17
+; AIX32-NEXT:    lwarx 6, 0, 16
 ; AIX32-NEXT:    or 7, 4, 6
 ; AIX32-NEXT:    andc 8, 6, 5
 ; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:    or 7, 7, 8
-; AIX32-NEXT:    stwcx. 7, 0, 17
+; AIX32-NEXT:    stwcx. 7, 0, 16
 ; AIX32-NEXT:    bne 0, L..BB2_29
 ; AIX32-NEXT:  # %bb.30: # %entry
 ; AIX32-NEXT:    srw 4, 6, 18
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    li 5, 0
 ; AIX32-NEXT:    clrlwi 4, 4, 16
 ; AIX32-NEXT:    ori 5, 5, 65535
-; AIX32-NEXT:    or 4, 4, 3
-; AIX32-NEXT:    lbz 3, 0(26)
+; AIX32-NEXT:    or 3, 4, 3
 ; AIX32-NEXT:    slw 5, 5, 15
-; AIX32-NEXT:    sth 4, 0(27)
-; AIX32-NEXT:    slw 4, 3, 15
+; AIX32-NEXT:    sth 3, 0(23)
+; AIX32-NEXT:    lbz 3, 0(26)
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 4, 3, 15
 ; AIX32-NEXT:  L..BB2_31: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 6, 0, 14
 ; AIX32-NEXT:    or 7, 4, 6
 ; AIX32-NEXT:    andc 8, 6, 5
 ; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:    or 7, 7, 8
 ; AIX32-NEXT:    stwcx. 7, 0, 14

 ; AIX32-NEXT:    bne 0, L..BB2_33
 ; AIX32-NEXT:  # %bb.34: # %entry
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    stw 4, 0(13)
 ; AIX32-NEXT:    lbz 3, 0(26)
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB2_35: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 4, 0, 16
-; AIX32-NEXT:    or 7, 3, 4
-; AIX32-NEXT:    stwcx. 7, 0, 16
+; AIX32-NEXT:    lwarx 4, 0, 25
+; AIX32-NEXT:    or 4, 3, 4
+; AIX32-NEXT:    stwcx. 4, 0, 25
 ; AIX32-NEXT:    bne 0, L..BB2_35
 ; AIX32-NEXT:  # %bb.36: # %entry
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    mr 3, 31
+; AIX32-NEXT:    stw 4, 0(25)
 ; AIX32-NEXT:    li 4, 0
-; AIX32-NEXT:    li 6, 5
 ; AIX32-NEXT:    lbz 29, 0(26)
-; AIX32-NEXT:    stw 7, 0(16)
+; AIX32-NEXT:    li 6, 5
+; AIX32-NEXT:    mr 3, 31
 ; AIX32-NEXT:    mr 5, 29
 ; AIX32-NEXT:    bl .__atomic_fetch_or_8[PR]
 ; AIX32-NEXT:    nop
-; AIX32-NEXT:    lbz 28, 0(26)
-; AIX32-NEXT:    mr 7, 3
-; AIX32-NEXT:    or 8, 4, 29
-; AIX32-NEXT:    mr 3, 30
-; AIX32-NEXT:    li 4, 0
+; AIX32-NEXT:    or 4, 4, 29
+; AIX32-NEXT:    lbz 29, 0(26)
 ; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    mr 5, 28
-; AIX32-NEXT:    stw 7, 0(31)
-; AIX32-NEXT:    stw 8, 4(31)
+; AIX32-NEXT:    mr 5, 29
+; AIX32-NEXT:    stw 4, 4(31)
+; AIX32-NEXT:    li 4, 0
+; AIX32-NEXT:    stw 3, 0(31)
+; AIX32-NEXT:    mr 3, 30
 ; AIX32-NEXT:    bl .__atomic_fetch_or_8[PR]
 ; AIX32-NEXT:    nop
-; AIX32-NEXT:    lbz 5, 0(26)
-; AIX32-NEXT:    or 4, 4, 28
 ; AIX32-NEXT:    stw 3, 0(30)
+; AIX32-NEXT:    lbz 3, 0(26)
+; AIX32-NEXT:    or 4, 4, 29
+; AIX32-NEXT:    li 5, 255
 ; AIX32-NEXT:    stw 4, 4(30)
-; AIX32-NEXT:    li 4, 255
-; AIX32-NEXT:    slw 3, 5, 23
-; AIX32-NEXT:    slw 4, 4, 23
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 5, 5, 24
+; AIX32-NEXT:    slw 4, 3, 24
 ; AIX32-NEXT:  L..BB2_37: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 6, 0, 22
-; AIX32-NEXT:    xor 7, 3, 6
-; AIX32-NEXT:    andc 8, 6, 4
-; AIX32-NEXT:    and 7, 7, 4
+; AIX32-NEXT:    xor 7, 4, 6
+; AIX32-NEXT:    andc 8, 6, 5
+; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:    or 7, 7, 8
 ; AIX32-NEXT:    stwcx. 7, 0, 22
 ; AIX32-NEXT:    bne 0, L..BB2_37
 ; AIX32-NEXT:  # %bb.38: # %entry
-; AIX32-NEXT:    srw 3, 6, 23
+; AIX32-NEXT:    srw 4, 6, 24
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    clrlwi 3, 3, 24
-; AIX32-NEXT:    xor 4, 3, 5
-; AIX32-NEXT:    lbz 3, 0(26)
 ; AIX32-NEXT:    li 5, 255
-; AIX32-NEXT:    stb 4, 0(24)
+; AIX32-NEXT:    clrlwi 4, 4, 24
 ; AIX32-NEXT:    slw 5, 5, 21
-; AIX32-NEXT:    slw 4, 3, 21
+; AIX32-NEXT:    xor 3, 4, 3
+; AIX32-NEXT:    stb 3, 0(27)
+; AIX32-NEXT:    lbz 3, 0(26)
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 4, 3, 21
 ; AIX32-NEXT:  L..BB2_39: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 6, 0, 19
 ; AIX32-NEXT:    xor 7, 4, 6
 ; AIX32-NEXT:    andc 8, 6, 5
 ; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:    or 7, 7, 8
 ; AIX32-NEXT:    stwcx. 7, 0, 19
 ; AIX32-NEXT:    bne 0, L..BB2_39
 ; AIX32-NEXT:  # %bb.40: # %entry
 ; AIX32-NEXT:    srw 4, 6, 21
+; AIX32-NEXT:    li 5, 0
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    clrlwi 4, 4, 24
+; AIX32-NEXT:    ori 5, 5, 65535
 ; AIX32-NEXT:    xor 3, 4, 3
-; AIX32-NEXT:    li 4, 0
+; AIX32-NEXT:    slw 5, 5, 18
 ; AIX32-NEXT:    stb 3, 0(26)
+; AIX32-NEXT:    sync
 ; AIX32-NEXT:    clrlwi 3, 3, 24
-; AIX32-NEXT:    ori 5, 4, 65535
 ; AIX32-NEXT:    slw 4, 3, 18
-; AIX32-NEXT:    slw 5, 5, 18
-; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB2_41: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 6, 0, 17
+; AIX32-NEXT:    lwarx 6, 0, 16
 ; AIX32-NEXT:    xor 7, 4, 6
 ; AIX32-NEXT:    andc 8, 6, 5
 ; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:    or 7, 7, 8
-; AIX32-NEXT:    stwcx. 7, 0, 17
+; AIX32-NEXT:    stwcx. 7, 0, 16
 ; AIX32-NEXT:    bne 0, L..BB2_41
 ; AIX32-NEXT:  # %bb.42: # %entry
 ; AIX32-NEXT:    srw 4, 6, 18
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    li 5, 0
 ; AIX32-NEXT:    clrlwi 4, 4, 16
 ; AIX32-NEXT:    ori 5, 5, 65535
-; AIX32-NEXT:    xor 4, 4, 3
-; AIX32-NEXT:    lbz 3, 0(26)
+; AIX32-NEXT:    xor 3, 4, 3
 ; AIX32-NEXT:    slw 5, 5, 15
-; AIX32-NEXT:    sth 4, 0(27)
-; AIX32-NEXT:    slw 4, 3, 15
+; AIX32-NEXT:    sth 3, 0(23)
+; AIX32-NEXT:    lbz 3, 0(26)
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 4, 3, 15
 ; AIX32-NEXT:  L..BB2_43: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 6, 0, 14
 ; AIX32-NEXT:    xor 7, 4, 6
 ; AIX32-NEXT:    andc 8, 6, 5
 ; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:    or 7, 7, 8
 ; AIX32-NEXT:    stwcx. 7, 0, 14

 ; AIX32-NEXT:    bne 0, L..BB2_45
 ; AIX32-NEXT:  # %bb.46: # %entry
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    stw 4, 0(13)
 ; AIX32-NEXT:    lbz 3, 0(26)
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB2_47: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 4, 0, 16
-; AIX32-NEXT:    xor 7, 3, 4
-; AIX32-NEXT:    stwcx. 7, 0, 16
+; AIX32-NEXT:    lwarx 4, 0, 25
+; AIX32-NEXT:    xor 4, 3, 4
+; AIX32-NEXT:    stwcx. 4, 0, 25
 ; AIX32-NEXT:    bne 0, L..BB2_47
 ; AIX32-NEXT:  # %bb.48: # %entry
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    mr 3, 31
+; AIX32-NEXT:    stw 4, 0(25)
 ; AIX32-NEXT:    li 4, 0
-; AIX32-NEXT:    li 6, 5
 ; AIX32-NEXT:    lbz 29, 0(26)
-; AIX32-NEXT:    stw 7, 0(16)
+; AIX32-NEXT:    li 6, 5
+; AIX32-NEXT:    mr 3, 31
 ; AIX32-NEXT:    mr 5, 29
 ; AIX32-NEXT:    bl .__atomic_fetch_xor_8[PR]
 ; AIX32-NEXT:    nop
-; AIX32-NEXT:    lbz 28, 0(26)
-; AIX32-NEXT:    mr 7, 3
-; AIX32-NEXT:    xor 8, 4, 29
-; AIX32-NEXT:    mr 3, 30
-; AIX32-NEXT:    li 4, 0
+; AIX32-NEXT:    xor 4, 4, 29
+; AIX32-NEXT:    lbz 29, 0(26)
 ; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    mr 5, 28
-; AIX32-NEXT:    stw 7, 0(31)
-; AIX32-NEXT:    stw 8, 4(31)
+; AIX32-NEXT:    mr 5, 29
+; AIX32-NEXT:    stw 4, 4(31)
+; AIX32-NEXT:    li 4, 0
+; AIX32-NEXT:    stw 3, 0(31)
+; AIX32-NEXT:    mr 3, 30
 ; AIX32-NEXT:    bl .__atomic_fetch_xor_8[PR]
 ; AIX32-NEXT:    nop
-; AIX32-NEXT:    lbz 5, 0(26)
-; AIX32-NEXT:    xor 4, 4, 28
+; AIX32-NEXT:    xor 4, 4, 29
 ; AIX32-NEXT:    stw 3, 0(30)
+; AIX32-NEXT:    lbz 3, 0(26)
+; AIX32-NEXT:    li 5, 255
 ; AIX32-NEXT:    stw 4, 4(30)
-; AIX32-NEXT:    li 4, 255
-; AIX32-NEXT:    slw 3, 5, 23
-; AIX32-NEXT:    slw 4, 4, 23
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 4, 3, 24
+; AIX32-NEXT:    slw 5, 5, 24
 ; AIX32-NEXT:  L..BB2_49: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 6, 0, 22
-; AIX32-NEXT:    nand 7, 3, 6
-; AIX32-NEXT:    andc 8, 6, 4
-; AIX32-NEXT:    and 7, 7, 4
+; AIX32-NEXT:    nand 7, 4, 6
+; AIX32-NEXT:    andc 8, 6, 5
+; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:    or 7, 7, 8
 ; AIX32-NEXT:    stwcx. 7, 0, 22
 ; AIX32-NEXT:    bne 0, L..BB2_49
 ; AIX32-NEXT:  # %bb.50: # %entry
-; AIX32-NEXT:    srw 3, 6, 23
+; AIX32-NEXT:    srw 4, 6, 24
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    clrlwi 3, 3, 24
-; AIX32-NEXT:    nand 4, 3, 5
-; AIX32-NEXT:    lbz 3, 0(26)
 ; AIX32-NEXT:    li 5, 255
-; AIX32-NEXT:    stb 4, 0(24)
+; AIX32-NEXT:    clrlwi 4, 4, 24
 ; AIX32-NEXT:    slw 5, 5, 21
-; AIX32-NEXT:    slw 4, 3, 21
+; AIX32-NEXT:    nand 3, 4, 3
+; AIX32-NEXT:    stb 3, 0(27)
+; AIX32-NEXT:    lbz 3, 0(26)
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 4, 3, 21
 ; AIX32-NEXT:  L..BB2_51: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 6, 0, 19
 ; AIX32-NEXT:    nand 7, 4, 6
 ; AIX32-NEXT:    andc 8, 6, 5
 ; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:    or 7, 7, 8
 ; AIX32-NEXT:    stwcx. 7, 0, 19
 ; AIX32-NEXT:    bne 0, L..BB2_51
 ; AIX32-NEXT:  # %bb.52: # %entry
 ; AIX32-NEXT:    srw 4, 6, 21
+; AIX32-NEXT:    li 5, 0
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    clrlwi 4, 4, 24
+; AIX32-NEXT:    ori 5, 5, 65535
 ; AIX32-NEXT:    nand 3, 4, 3
-; AIX32-NEXT:    li 4, 0
+; AIX32-NEXT:    slw 5, 5, 18
 ; AIX32-NEXT:    stb 3, 0(26)
+; AIX32-NEXT:    sync
 ; AIX32-NEXT:    clrlwi 3, 3, 24
-; AIX32-NEXT:    ori 5, 4, 65535
 ; AIX32-NEXT:    slw 4, 3, 18
-; AIX32-NEXT:    slw 5, 5, 18
-; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB2_53: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 6, 0, 17
+; AIX32-NEXT:    lwarx 6, 0, 16
 ; AIX32-NEXT:    nand 7, 4, 6
 ; AIX32-NEXT:    andc 8, 6, 5
 ; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:    or 7, 7, 8
-; AIX32-NEXT:    stwcx. 7, 0, 17
+; AIX32-NEXT:    stwcx. 7, 0, 16
 ; AIX32-NEXT:    bne 0, L..BB2_53
 ; AIX32-NEXT:  # %bb.54: # %entry
 ; AIX32-NEXT:    srw 4, 6, 18
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    li 5, 0
 ; AIX32-NEXT:    clrlwi 4, 4, 16
 ; AIX32-NEXT:    ori 5, 5, 65535
-; AIX32-NEXT:    nand 4, 4, 3
-; AIX32-NEXT:    lbz 3, 0(26)
+; AIX32-NEXT:    nand 3, 4, 3
 ; AIX32-NEXT:    slw 5, 5, 15
-; AIX32-NEXT:    sth 4, 0(27)
-; AIX32-NEXT:    slw 4, 3, 15
+; AIX32-NEXT:    sth 3, 0(23)
+; AIX32-NEXT:    lbz 3, 0(26)
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 4, 3, 15
 ; AIX32-NEXT:  L..BB2_55: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 6, 0, 14
 ; AIX32-NEXT:    nand 7, 4, 6
 ; AIX32-NEXT:    andc 8, 6, 5
 ; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:    or 7, 7, 8
 ; AIX32-NEXT:    stwcx. 7, 0, 14
 ; AIX32-NEXT:    bne 0, L..BB2_55
 ; AIX32-NEXT:  # %bb.56: # %entry
 ; AIX32-NEXT:    srw 4, 6, 15
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    clrlwi 4, 4, 16
 ; AIX32-NEXT:    nand 3, 4, 3
 ; AIX32-NEXT:    sth 3, 0(20)
 ; AIX32-NEXT:    lbz 3, 0(26)
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB2_57: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 13
 ; AIX32-NEXT:    nand 4, 3, 4
 ; AIX32-NEXT:    stwcx. 4, 0, 13
 ; AIX32-NEXT:    bne 0, L..BB2_57
 ; AIX32-NEXT:  # %bb.58: # %entry
-; AIX32-NEXT:    stw 24, 56(1) # 4-byte Folded Spill
+; AIX32-NEXT:    stw 23, 56(1) # 4-byte Folded Spill
+; AIX32-NEXT:    stw 27, 60(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    stw 4, 0(13)
 ; AIX32-NEXT:    lbz 3, 0(26)
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB2_59: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 4, 0, 16
-; AIX32-NEXT:    nand 7, 3, 4
-; AIX32-NEXT:    stwcx. 7, 0, 16
+; AIX32-NEXT:    lwarx 4, 0, 25
+; AIX32-NEXT:    nand 4, 3, 4
+; AIX32-NEXT:    stwcx. 4, 0, 25
 ; AIX32-NEXT:    bne 0, L..BB2_59
 ; AIX32-NEXT:  # %bb.60: # %entry
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    mr 3, 31
+; AIX32-NEXT:    stw 4, 0(25)
 ; AIX32-NEXT:    li 4, 0
-; AIX32-NEXT:    li 6, 5
 ; AIX32-NEXT:    lbz 29, 0(26)
-; AIX32-NEXT:    stw 7, 0(16)
+; AIX32-NEXT:    li 6, 5
+; AIX32-NEXT:    mr 3, 31
 ; AIX32-NEXT:    mr 5, 29
 ; AIX32-NEXT:    bl .__atomic_fetch_nand_8[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    lbz 28, 0(26)
-; AIX32-NEXT:    nand 7, 4, 29
-; AIX32-NEXT:    mr 3, 30
+; AIX32-NEXT:    nand 3, 4, 29
 ; AIX32-NEXT:    li 4, 0
-; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    stw 7, 4(31)
 ; AIX32-NEXT:    mr 5, 28
-; AIX32-NEXT:    stw 25, 0(31)
+; AIX32-NEXT:    li 6, 5
+; AIX32-NEXT:    stw 3, 4(31)
+; AIX32-NEXT:    mr 3, 30
+; AIX32-NEXT:    stw 17, 0(31)
 ; AIX32-NEXT:    bl .__atomic_fetch_nand_8[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    lwz 29, L..C8(2) # @u128
+; AIX32-NEXT:    lbz 23, 0(26)
 ; AIX32-NEXT:    nand 3, 4, 28
-; AIX32-NEXT:    lbz 24, 0(26)
 ; AIX32-NEXT:    addi 28, 1, 80
 ; AIX32-NEXT:    addi 27, 1, 64
+; AIX32-NEXT:    stw 17, 0(30)
+; AIX32-NEXT:    lwz 5, 12(29)
+; AIX32-NEXT:    lwz 6, 8(29)
+; AIX32-NEXT:    lwz 4, 4(29)
+; AIX32-NEXT:    lwz 7, 0(29)
 ; AIX32-NEXT:    stw 3, 4(30)
-; AIX32-NEXT:    stw 25, 0(30)
-; AIX32-NEXT:    lwz 3, 12(29)
-; AIX32-NEXT:    lwz 4, 8(29)
-; AIX32-NEXT:    lwz 5, 4(29)
-; AIX32-NEXT:    lwz 6, 0(29)
 ; AIX32-NEXT:    .align 4
 ; AIX32-NEXT:  L..BB2_61: # %atomicrmw.start
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    and 7, 3, 24
-; AIX32-NEXT:    stw 3, 92(1)
+; AIX32-NEXT:    and 3, 5, 23
+; AIX32-NEXT:    stw 7, 80(1)
+; AIX32-NEXT:    li 7, 5
 ; AIX32-NEXT:    li 8, 5
-; AIX32-NEXT:    xor 3, 7, 25
-; AIX32-NEXT:    stw 6, 80(1)
+; AIX32-NEXT:    xor 3, 3, 17
+; AIX32-NEXT:    stw 4, 84(1)
+; AIX32-NEXT:    stw 6, 88(1)
+; AIX32-NEXT:    stw 5, 92(1)
+; AIX32-NEXT:    mr 4, 29
+; AIX32-NEXT:    mr 5, 28
 ; AIX32-NEXT:    mr 6, 27
-; AIX32-NEXT:    stw 5, 84(1)
-; AIX32-NEXT:    stw 4, 88(1)
 ; AIX32-NEXT:    stw 3, 76(1)
 ; AIX32-NEXT:    li 3, 16
-; AIX32-NEXT:    mr 4, 29
-; AIX32-NEXT:    mr 5, 28
-; AIX32-NEXT:    li 7, 5
-; AIX32-NEXT:    stw 25, 72(1)
-; AIX32-NEXT:    stw 25, 68(1)
-; AIX32-NEXT:    stw 25, 64(1)
+; AIX32-NEXT:    stw 17, 72(1)
+; AIX32-NEXT:    stw 17, 68(1)
+; AIX32-NEXT:    stw 17, 64(1)
 ; AIX32-NEXT:    bl .__atomic_compare_exchange[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    cmplwi 3, 0
-; AIX32-NEXT:    lwz 3, 92(1)
-; AIX32-NEXT:    lwz 4, 88(1)
-; AIX32-NEXT:    lwz 5, 84(1)
-; AIX32-NEXT:    lwz 6, 80(1)
+; AIX32-NEXT:    lwz 5, 92(1)
+; AIX32-NEXT:    lwz 6, 88(1)
+; AIX32-NEXT:    lwz 4, 84(1)
+; AIX32-NEXT:    lwz 7, 80(1)
 ; AIX32-NEXT:    beq 0, L..BB2_61
 ; AIX32-NEXT:  # %bb.62: # %atomicrmw.end
-; AIX32-NEXT:    lwz 28, L..C9(2) # @s128
-; AIX32-NEXT:    and 3, 3, 24
-; AIX32-NEXT:    lbz 24, 0(26)
-; AIX32-NEXT:    stw 25, 0(29)
-; AIX32-NEXT:    xor 3, 3, 25
-; AIX32-NEXT:    stw 25, 4(29)
+; AIX32-NEXT:    and 3, 5, 23
+; AIX32-NEXT:    stw 17, 0(29)
+; AIX32-NEXT:    lbz 23, 0(26)
+; AIX32-NEXT:    stw 17, 4(29)
+; AIX32-NEXT:    stw 17, 8(29)
+; AIX32-NEXT:    xor 3, 3, 17
+; AIX32-NEXT:    addi 28, 1, 80
 ; AIX32-NEXT:    addi 27, 1, 64
 ; AIX32-NEXT:    stw 3, 12(29)
-; AIX32-NEXT:    stw 25, 8(29)
-; AIX32-NEXT:    lwz 3, 12(28)
-; AIX32-NEXT:    lwz 4, 8(28)
-; AIX32-NEXT:    addi 29, 1, 80
-; AIX32-NEXT:    lwz 5, 4(28)
-; AIX32-NEXT:    lwz 6, 0(28)
+; AIX32-NEXT:    lwz 29, L..C9(2) # @s128
+; AIX32-NEXT:    lwz 4, 12(29)
+; AIX32-NEXT:    lwz 5, 8(29)
+; AIX32-NEXT:    lwz 6, 4(29)
+; AIX32-NEXT:    lwz 7, 0(29)
 ; AIX32-NEXT:    .align 4
 ; AIX32-NEXT:  L..BB2_63: # %atomicrmw.start2
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    and 7, 3, 24
-; AIX32-NEXT:    stw 3, 92(1)
+; AIX32-NEXT:    and 3, 4, 23
+; AIX32-NEXT:    stw 7, 80(1)
+; AIX32-NEXT:    li 7, 5
 ; AIX32-NEXT:    li 8, 5
-; AIX32-NEXT:    xor 3, 7, 25
-; AIX32-NEXT:    stw 6, 80(1)
+; AIX32-NEXT:    xor 3, 3, 17
+; AIX32-NEXT:    stw 6, 84(1)
+; AIX32-NEXT:    stw 5, 88(1)
+; AIX32-NEXT:    stw 4, 92(1)
+; AIX32-NEXT:    mr 4, 29
+; AIX32-NEXT:    mr 5, 28
 ; AIX32-NEXT:    mr 6, 27
-; AIX32-NEXT:    stw 5, 84(1)
-; AIX32-NEXT:    stw 4, 88(1)
 ; AIX32-NEXT:    stw 3, 76(1)
 ; AIX32-NEXT:    li 3, 16
-; AIX32-NEXT:    mr 4, 28
-; AIX32-NEXT:    mr 5, 29
-; AIX32-NEXT:    li 7, 5
-; AIX32-NEXT:    stw 25, 72(1)
-; AIX32-NEXT:    stw 25, 68(1)
-; AIX32-NEXT:    stw 25, 64(1)
+; AIX32-NEXT:    stw 17, 72(1)
+; AIX32-NEXT:    stw 17, 68(1)
+; AIX32-NEXT:    stw 17, 64(1)
 ; AIX32-NEXT:    bl .__atomic_compare_exchange[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    cmplwi 3, 0
-; AIX32-NEXT:    lwz 3, 92(1)
-; AIX32-NEXT:    lwz 4, 88(1)
-; AIX32-NEXT:    lwz 5, 84(1)
-; AIX32-NEXT:    lwz 6, 80(1)
+; AIX32-NEXT:    lwz 4, 92(1)
+; AIX32-NEXT:    lwz 5, 88(1)
+; AIX32-NEXT:    lwz 6, 84(1)
+; AIX32-NEXT:    lwz 7, 80(1)
 ; AIX32-NEXT:    beq 0, L..BB2_63
 ; AIX32-NEXT:  # %bb.64: # %atomicrmw.end1
-; AIX32-NEXT:    and 3, 3, 24
+; AIX32-NEXT:    and 3, 4, 23
 ; AIX32-NEXT:    li 5, 255
-; AIX32-NEXT:    xor 4, 3, 25
+; AIX32-NEXT:    xor 3, 3, 17
+; AIX32-NEXT:    stw 17, 0(29)
+; AIX32-NEXT:    stw 17, 4(29)
+; AIX32-NEXT:    stw 17, 8(29)
+; AIX32-NEXT:    slw 5, 5, 24
+; AIX32-NEXT:    stw 3, 12(29)
 ; AIX32-NEXT:    lbz 3, 0(26)
-; AIX32-NEXT:    stw 25, 0(28)
-; AIX32-NEXT:    stw 25, 4(28)
-; AIX32-NEXT:    stw 25, 8(28)
-; AIX32-NEXT:    stw 4, 12(28)
-; AIX32-NEXT:    slw 4, 3, 23
-; AIX32-NEXT:    slw 5, 5, 23
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 4, 3, 24
 ; AIX32-NEXT:  L..BB2_65: # %atomicrmw.end1
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 6, 0, 22
 ; AIX32-NEXT:    and 7, 4, 6
 ; AIX32-NEXT:    andc 8, 6, 5
 ; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:    or 7, 7, 8
 ; AIX32-NEXT:    stwcx. 7, 0, 22
 ; AIX32-NEXT:    bne 0, L..BB2_65
 ; AIX32-NEXT:  # %bb.66: # %atomicrmw.end1
-; AIX32-NEXT:    srw 4, 6, 23
+; AIX32-NEXT:    srw 4, 6, 24
 ; AIX32-NEXT:    lwsync
+; AIX32-NEXT:    li 5, 255
 ; AIX32-NEXT:    clrlwi 4, 4, 24
-; AIX32-NEXT:    lwz 5, 56(1) # 4-byte Folded Reload
-; AIX32-NEXT:    and 4, 4, 3
+; AIX32-NEXT:    slw 5, 5, 21
+; AIX32-NEXT:    and 3, 4, 3
+; AIX32-NEXT:    lwz 4, 60(1) # 4-byte Folded Reload
+; AIX32-NEXT:    stb 3, 0(4)
 ; AIX32-NEXT:    lbz 3, 0(26)
-; AIX32-NEXT:    stb 4, 0(5)
-; AIX32-NEXT:    li 5, 255
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    lwz 9, 56(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    slw 4, 3, 21
-; AIX32-NEXT:    slw 5, 5, 21
-; AIX32-NEXT:    lwz 9, 60(1) # 4-byte Folded Reload
 ; AIX32-NEXT:  L..BB2_67: # %atomicrmw.end1
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 6, 0, 19
 ; AIX32-NEXT:    and 7, 4, 6
 ; AIX32-NEXT:    andc 8, 6, 5
 ; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:    or 7, 7, 8
 ; AIX32-NEXT:    stwcx. 7, 0, 19
 ; AIX32-NEXT:    bne 0, L..BB2_67
 ; AIX32-NEXT:  # %bb.68: # %atomicrmw.end1
 ; AIX32-NEXT:    srw 4, 6, 21
+; AIX32-NEXT:    li 5, 0
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    clrlwi 4, 4, 24
+; AIX32-NEXT:    ori 5, 5, 65535
 ; AIX32-NEXT:    and 3, 4, 3
-; AIX32-NEXT:    li 4, 0
-; AIX32-NEXT:    ori 5, 4, 65535
-; AIX32-NEXT:    stb 3, 0(26)
-; AIX32-NEXT:    slw 4, 3, 18
 ; AIX32-NEXT:    slw 5, 5, 18
+; AIX32-NEXT:    stb 3, 0(26)
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 4, 3, 18
 ; AIX32-NEXT:  L..BB2_69: # %atomicrmw.end1
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 6, 0, 17
+; AIX32-NEXT:    lwarx 6, 0, 16
 ; AIX32-NEXT:    and 7, 4, 6
 ; AIX32-NEXT:    andc 8, 6, 5
 ; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:    or 7, 7, 8
-; AIX32-NEXT:    stwcx. 7, 0, 17
+; AIX32-NEXT:    stwcx. 7, 0, 16
 ; AIX32-NEXT:    bne 0, L..BB2_69
 ; AIX32-NEXT:  # %bb.70: # %atomicrmw.end1
 ; AIX32-NEXT:    srw 4, 6, 18
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    li 5, 0
 ; AIX32-NEXT:    clrlwi 4, 4, 16
 ; AIX32-NEXT:    ori 5, 5, 65535
-; AIX32-NEXT:    and 4, 4, 3
-; AIX32-NEXT:    lbz 3, 0(26)
+; AIX32-NEXT:    and 3, 4, 3
 ; AIX32-NEXT:    slw 5, 5, 15
-; AIX32-NEXT:    sth 4, 0(9)
-; AIX32-NEXT:    slw 4, 3, 15
+; AIX32-NEXT:    sth 3, 0(9)
+; AIX32-NEXT:    lbz 3, 0(26)
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 4, 3, 15
 ; AIX32-NEXT:  L..BB2_71: # %atomicrmw.end1
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 6, 0, 14
 ; AIX32-NEXT:    and 7, 4, 6
 ; AIX32-NEXT:    andc 8, 6, 5
 ; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:    or 7, 7, 8
 ; AIX32-NEXT:    stwcx. 7, 0, 14

 ; AIX32-NEXT:    bne 0, L..BB2_73
 ; AIX32-NEXT:  # %bb.74: # %atomicrmw.end1
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    stw 4, 0(13)
 ; AIX32-NEXT:    lbz 3, 0(26)
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB2_75: # %atomicrmw.end1
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 4, 0, 16
-; AIX32-NEXT:    and 7, 3, 4
-; AIX32-NEXT:    stwcx. 7, 0, 16
+; AIX32-NEXT:    lwarx 4, 0, 25
+; AIX32-NEXT:    and 4, 3, 4
+; AIX32-NEXT:    stwcx. 4, 0, 25
 ; AIX32-NEXT:    bne 0, L..BB2_75
 ; AIX32-NEXT:  # %bb.76: # %atomicrmw.end1
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    mr 3, 31
+; AIX32-NEXT:    stw 4, 0(25)
 ; AIX32-NEXT:    li 4, 0
-; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    li 27, 0
 ; AIX32-NEXT:    lbz 29, 0(26)
-; AIX32-NEXT:    stw 7, 0(16)
+; AIX32-NEXT:    li 6, 5
+; AIX32-NEXT:    mr 3, 31
+; AIX32-NEXT:    li 28, 0
 ; AIX32-NEXT:    mr 5, 29
 ; AIX32-NEXT:    bl .__atomic_fetch_and_8[PR]
 ; AIX32-NEXT:    nop
-; AIX32-NEXT:    lbz 28, 0(26)
-; AIX32-NEXT:    and 7, 4, 29
-; AIX32-NEXT:    mr 3, 30
+; AIX32-NEXT:    and 3, 4, 29
+; AIX32-NEXT:    stw 28, 0(31)
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    stw 7, 4(31)
-; AIX32-NEXT:    mr 5, 28
-; AIX32-NEXT:    stw 27, 0(31)
+; AIX32-NEXT:    stw 3, 4(31)
+; AIX32-NEXT:    lbz 31, 0(26)
+; AIX32-NEXT:    mr 3, 30
+; AIX32-NEXT:    mr 5, 31
 ; AIX32-NEXT:    bl .__atomic_fetch_and_8[PR]
 ; AIX32-NEXT:    nop
-; AIX32-NEXT:    and 3, 4, 28
-; AIX32-NEXT:    stw 27, 0(30)
+; AIX32-NEXT:    and 3, 4, 31
+; AIX32-NEXT:    stw 28, 0(30)
 ; AIX32-NEXT:    lwz 31, 172(1) # 4-byte Folded Reload
-; AIX32-NEXT:    stw 3, 4(30)
-; AIX32-NEXT:    lwz 30, 168(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 29, 164(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 28, 160(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 27, 156(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 26, 152(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 25, 148(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 24, 144(1) # 4-byte Folded Reload
+; AIX32-NEXT:    stw 3, 4(30)
+; AIX32-NEXT:    lwz 30, 168(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 23, 140(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 22, 136(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 21, 132(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 20, 128(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 19, 124(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 18, 120(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 17, 116(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 16, 112(1) # 4-byte Folded Reload

 ; AIX32:       # %bb.0: # %entry
 ; AIX32-NEXT:    mflr 0
 ; AIX32-NEXT:    stwu 1, -128(1)
 ; AIX32-NEXT:    stw 0, 136(1)
 ; AIX32-NEXT:    stw 28, 112(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    lwz 28, L..C0(2) # @sc
 ; AIX32-NEXT:    stw 29, 116(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    lwz 29, L..C1(2) # @uc
-; AIX32-NEXT:    stw 23, 92(1) # 4-byte Folded Spill
+; AIX32-NEXT:    lbz 3, 0(29)
+; AIX32-NEXT:    rlwinm 5, 28, 3, 27, 28
+; AIX32-NEXT:    stw 21, 84(1) # 4-byte Folded Spill
+; AIX32-NEXT:    lbz 4, 0(28)
 ; AIX32-NEXT:    stw 17, 68(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 18, 72(1) # 4-byte Folded Spill
-; AIX32-NEXT:    lbz 3, 0(28)
-; AIX32-NEXT:    rlwinm 4, 28, 3, 27, 28
 ; AIX32-NEXT:    stw 19, 76(1) # 4-byte Folded Spill
-; AIX32-NEXT:    lbz 5, 0(29)
-; AIX32-NEXT:    xori 23, 4, 24
-; AIX32-NEXT:    li 4, 255
-; AIX32-NEXT:    slw 6, 3, 23
-; AIX32-NEXT:    slw 3, 4, 23
-; AIX32-NEXT:    slw 5, 5, 23
 ; AIX32-NEXT:    stw 20, 80(1) # 4-byte Folded Spill
-; AIX32-NEXT:    and 4, 6, 3
-; AIX32-NEXT:    stw 21, 84(1) # 4-byte Folded Spill
+; AIX32-NEXT:    xori 21, 5, 24
 ; AIX32-NEXT:    stw 22, 88(1) # 4-byte Folded Spill
+; AIX32-NEXT:    stw 23, 92(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 24, 96(1) # 4-byte Folded Spill
+; AIX32-NEXT:    slw 5, 3, 21
+; AIX32-NEXT:    li 3, 255
+; AIX32-NEXT:    slw 4, 4, 21
 ; AIX32-NEXT:    stw 25, 100(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 26, 104(1) # 4-byte Folded Spill
+; AIX32-NEXT:    slw 3, 3, 21
 ; AIX32-NEXT:    stw 27, 108(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 30, 120(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 31, 124(1) # 4-byte Folded Spill
-; AIX32-NEXT:    rlwinm 19, 28, 0, 0, 29
-; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    rlwinm 18, 28, 0, 0, 29
+; AIX32-NEXT:    and 4, 4, 3
+; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:  L..BB3_1: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 7, 0, 19
+; AIX32-NEXT:    lwarx 7, 0, 18
 ; AIX32-NEXT:    and 6, 7, 3
 ; AIX32-NEXT:    cmpw 6, 5
 ; AIX32-NEXT:    bne 0, L..BB3_3
 ; AIX32-NEXT:  # %bb.2: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    andc 7, 7, 3
 ; AIX32-NEXT:    or 7, 7, 4
-; AIX32-NEXT:    stwcx. 7, 0, 19
+; AIX32-NEXT:    stwcx. 7, 0, 18
 ; AIX32-NEXT:    bne 0, L..BB3_1
 ; AIX32-NEXT:  L..BB3_3: # %entry
+; AIX32-NEXT:    rlwinm 5, 29, 3, 27, 28
+; AIX32-NEXT:    srw 3, 6, 21
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    rlwinm 4, 29, 3, 27, 28
-; AIX32-NEXT:    srw 3, 6, 23
-; AIX32-NEXT:    lbz 5, 0(29)
-; AIX32-NEXT:    xori 25, 4, 24
+; AIX32-NEXT:    lbz 4, 0(29)
+; AIX32-NEXT:    rlwinm 20, 29, 0, 0, 29
+; AIX32-NEXT:    xori 24, 5, 24
+; AIX32-NEXT:    slw 5, 3, 24
 ; AIX32-NEXT:    stb 3, 0(28)
-; AIX32-NEXT:    slw 4, 3, 25
 ; AIX32-NEXT:    li 3, 255
 ; AIX32-NEXT:    sync
-; AIX32-NEXT:    slw 6, 5, 25
-; AIX32-NEXT:    slw 3, 3, 25
-; AIX32-NEXT:    rlwinm 22, 29, 0, 0, 29
-; AIX32-NEXT:    and 5, 4, 3
-; AIX32-NEXT:    and 6, 6, 3
+; AIX32-NEXT:    slw 6, 4, 24
+; AIX32-NEXT:    slw 3, 3, 24
+; AIX32-NEXT:    and 4, 5, 3
+; AIX32-NEXT:    and 5, 6, 3
 ; AIX32-NEXT:  L..BB3_4: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 7, 0, 22
-; AIX32-NEXT:    and 4, 7, 3
-; AIX32-NEXT:    cmpw 4, 6
+; AIX32-NEXT:    lwarx 7, 0, 20
+; AIX32-NEXT:    and 6, 7, 3
+; AIX32-NEXT:    cmpw 6, 5
 ; AIX32-NEXT:    bne 0, L..BB3_6
 ; AIX32-NEXT:  # %bb.5: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    andc 7, 7, 3
-; AIX32-NEXT:    or 7, 7, 5
-; AIX32-NEXT:    stwcx. 7, 0, 22
+; AIX32-NEXT:    or 7, 7, 4
+; AIX32-NEXT:    stwcx. 7, 0, 20
 ; AIX32-NEXT:    bne 0, L..BB3_4
 ; AIX32-NEXT:  L..BB3_6: # %entry
-; AIX32-NEXT:    lwz 3, L..C2(2) # @ss
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    li 7, 0
-; AIX32-NEXT:    srw 4, 4, 25
-; AIX32-NEXT:    lbz 5, 0(28)
+; AIX32-NEXT:    srw 4, 6, 24
+; AIX32-NEXT:    lbz 3, 0(28)
+; AIX32-NEXT:    extsb 5, 3
+; AIX32-NEXT:    lwz 3, L..C2(2) # @ss
 ; AIX32-NEXT:    stb 4, 0(29)
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:    rlwinm 6, 3, 3, 27, 27
-; AIX32-NEXT:    extsb 5, 5
-; AIX32-NEXT:    xori 24, 6, 16
-; AIX32-NEXT:    ori 6, 7, 65535
-; AIX32-NEXT:    slw 5, 5, 24
-; AIX32-NEXT:    slw 7, 4, 24
-; AIX32-NEXT:    slw 4, 6, 24
-; AIX32-NEXT:    rlwinm 20, 3, 0, 0, 29
-; AIX32-NEXT:    and 6, 5, 4
-; AIX32-NEXT:    and 7, 7, 4
+; AIX32-NEXT:    rlwinm 22, 3, 0, 0, 29
+; AIX32-NEXT:    xori 26, 6, 16
+; AIX32-NEXT:    slw 6, 4, 26
+; AIX32-NEXT:    li 4, 0
+; AIX32-NEXT:    slw 5, 5, 26
+; AIX32-NEXT:    ori 4, 4, 65535
+; AIX32-NEXT:    slw 4, 4, 26
+; AIX32-NEXT:    and 5, 5, 4
+; AIX32-NEXT:    and 6, 6, 4
 ; AIX32-NEXT:  L..BB3_7: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 8, 0, 20
-; AIX32-NEXT:    and 5, 8, 4
-; AIX32-NEXT:    cmpw 5, 7
+; AIX32-NEXT:    lwarx 8, 0, 22
+; AIX32-NEXT:    and 7, 8, 4
+; AIX32-NEXT:    cmpw 7, 6
 ; AIX32-NEXT:    bne 0, L..BB3_9
 ; AIX32-NEXT:  # %bb.8: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    andc 8, 8, 4
-; AIX32-NEXT:    or 8, 8, 6
-; AIX32-NEXT:    stwcx. 8, 0, 20
+; AIX32-NEXT:    or 8, 8, 5
+; AIX32-NEXT:    stwcx. 8, 0, 22
 ; AIX32-NEXT:    bne 0, L..BB3_7
 ; AIX32-NEXT:  L..BB3_9: # %entry
-; AIX32-NEXT:    lwz 4, L..C3(2) # @us
+; AIX32-NEXT:    srw 4, 7, 26
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    srw 5, 5, 24
-; AIX32-NEXT:    lbz 6, 0(28)
-; AIX32-NEXT:    sth 5, 0(3)
-; AIX32-NEXT:    li 5, 0
-; AIX32-NEXT:    lbz 7, 0(29)
-; AIX32-NEXT:    sync
-; AIX32-NEXT:    rlwinm 3, 4, 3, 27, 27
-; AIX32-NEXT:    extsb 6, 6
-; AIX32-NEXT:    xori 21, 3, 16
-; AIX32-NEXT:    ori 3, 5, 65535
-; AIX32-NEXT:    slw 5, 6, 21
-; AIX32-NEXT:    slw 7, 7, 21
-; AIX32-NEXT:    slw 3, 3, 21
-; AIX32-NEXT:    rlwinm 18, 4, 0, 0, 29
-; AIX32-NEXT:    and 6, 5, 3
-; AIX32-NEXT:    and 7, 7, 3
+; AIX32-NEXT:    sth 4, 0(3)
+; AIX32-NEXT:    lbz 3, 0(28)
+; AIX32-NEXT:    lbz 4, 0(29)
+; AIX32-NEXT:    sync
+; AIX32-NEXT:    extsb 5, 3
+; AIX32-NEXT:    lwz 3, L..C3(2) # @us
+; AIX32-NEXT:    rlwinm 6, 3, 3, 27, 27
+; AIX32-NEXT:    rlwinm 19, 3, 0, 0, 29
+; AIX32-NEXT:    xori 23, 6, 16
+; AIX32-NEXT:    slw 6, 4, 23
+; AIX32-NEXT:    li 4, 0
+; AIX32-NEXT:    slw 5, 5, 23
+; AIX32-NEXT:    ori 4, 4, 65535
+; AIX32-NEXT:    slw 4, 4, 23
+; AIX32-NEXT:    and 5, 5, 4
+; AIX32-NEXT:    and 6, 6, 4
 ; AIX32-NEXT:  L..BB3_10: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 8, 0, 18
-; AIX32-NEXT:    and 5, 8, 3
-; AIX32-NEXT:    cmpw 5, 7
+; AIX32-NEXT:    lwarx 8, 0, 19
+; AIX32-NEXT:    and 7, 8, 4
+; AIX32-NEXT:    cmpw 7, 6
 ; AIX32-NEXT:    bne 0, L..BB3_12
 ; AIX32-NEXT:  # %bb.11: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    andc 8, 8, 3
-; AIX32-NEXT:    or 8, 8, 6
-; AIX32-NEXT:    stwcx. 8, 0, 18
+; AIX32-NEXT:    andc 8, 8, 4
+; AIX32-NEXT:    or 8, 8, 5
+; AIX32-NEXT:    stwcx. 8, 0, 19
 ; AIX32-NEXT:    bne 0, L..BB3_10
 ; AIX32-NEXT:  L..BB3_12: # %entry
+; AIX32-NEXT:    srw 4, 7, 23
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    srw 3, 5, 21
 ; AIX32-NEXT:    lwz 17, L..C4(2) # @si
-; AIX32-NEXT:    lbz 5, 0(28)
-; AIX32-NEXT:    sth 3, 0(4)
+; AIX32-NEXT:    sth 4, 0(3)
+; AIX32-NEXT:    lbz 4, 0(28)
 ; AIX32-NEXT:    lbz 3, 0(29)
 ; AIX32-NEXT:    sync
-; AIX32-NEXT:    extsb 4, 5
+; AIX32-NEXT:    extsb 4, 4
 ; AIX32-NEXT:  L..BB3_13: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 5, 0, 17
 ; AIX32-NEXT:    cmpw 5, 3
 ; AIX32-NEXT:    bne 0, L..BB3_15
 ; AIX32-NEXT:  # %bb.14: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    stwcx. 4, 0, 17
 ; AIX32-NEXT:    bne 0, L..BB3_13
 ; AIX32-NEXT:  L..BB3_15: # %entry
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    lwz 27, L..C5(2) # @ui
 ; AIX32-NEXT:    stw 5, 0(17)
+; AIX32-NEXT:    lwz 27, L..C5(2) # @ui
 ; AIX32-NEXT:    lbz 4, 0(28)
 ; AIX32-NEXT:    lbz 3, 0(29)
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:    extsb 4, 4
 ; AIX32-NEXT:  L..BB3_16: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 5, 0, 27
 ; AIX32-NEXT:    cmpw 5, 3
 ; AIX32-NEXT:    bne 0, L..BB3_18
 ; AIX32-NEXT:  # %bb.17: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    stwcx. 4, 0, 27
 ; AIX32-NEXT:    bne 0, L..BB3_16
 ; AIX32-NEXT:  L..BB3_18: # %entry
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    lwz 31, L..C6(2) # @sll
 ; AIX32-NEXT:    stw 5, 0(27)
-; AIX32-NEXT:    li 26, 0
+; AIX32-NEXT:    lbz 3, 0(28)
+; AIX32-NEXT:    li 25, 0
+; AIX32-NEXT:    addi 4, 1, 56
 ; AIX32-NEXT:    li 7, 5
-; AIX32-NEXT:    lbz 4, 0(28)
-; AIX32-NEXT:    lbz 3, 0(29)
 ; AIX32-NEXT:    li 8, 5
-; AIX32-NEXT:    stw 26, 56(1)
-; AIX32-NEXT:    extsb 6, 4
-; AIX32-NEXT:    stw 3, 60(1)
-; AIX32-NEXT:    addi 4, 1, 56
+; AIX32-NEXT:    stw 25, 56(1)
+; AIX32-NEXT:    extsb 6, 3
+; AIX32-NEXT:    lbz 3, 0(29)
 ; AIX32-NEXT:    srawi 5, 6, 31
+; AIX32-NEXT:    stw 3, 60(1)
 ; AIX32-NEXT:    mr 3, 31
 ; AIX32-NEXT:    bl .__atomic_compare_exchange_8[PR]
 ; AIX32-NEXT:    nop
-; AIX32-NEXT:    lbz 5, 0(28)
+; AIX32-NEXT:    lwz 3, 56(1)
+; AIX32-NEXT:    lwz 4, 60(1)
 ; AIX32-NEXT:    lwz 30, L..C7(2) # @ull
-; AIX32-NEXT:    lwz 3, 60(1)
 ; AIX32-NEXT:    li 7, 5
 ; AIX32-NEXT:    li 8, 5
-; AIX32-NEXT:    lwz 4, 56(1)
-; AIX32-NEXT:    lbz 9, 0(29)
-; AIX32-NEXT:    extsb 6, 5
-; AIX32-NEXT:    stw 3, 4(31)
-; AIX32-NEXT:    stw 4, 0(31)
-; AIX32-NEXT:    srawi 5, 6, 31
+; AIX32-NEXT:    stw 25, 56(1)
+; AIX32-NEXT:    stw 3, 0(31)
+; AIX32-NEXT:    lbz 3, 0(28)
+; AIX32-NEXT:    extsb 6, 3
+; AIX32-NEXT:    lbz 3, 0(29)
+; AIX32-NEXT:    stw 4, 4(31)
 ; AIX32-NEXT:    addi 4, 1, 56
+; AIX32-NEXT:    srawi 5, 6, 31
+; AIX32-NEXT:    stw 3, 60(1)
 ; AIX32-NEXT:    mr 3, 30
-; AIX32-NEXT:    stw 9, 60(1)
-; AIX32-NEXT:    stw 26, 56(1)
 ; AIX32-NEXT:    bl .__atomic_compare_exchange_8[PR]
 ; AIX32-NEXT:    nop
-; AIX32-NEXT:    lwz 3, 60(1)
-; AIX32-NEXT:    lwz 5, 56(1)
-; AIX32-NEXT:    lbz 6, 0(28)
-; AIX32-NEXT:    lbz 4, 0(29)
-; AIX32-NEXT:    stw 3, 4(30)
-; AIX32-NEXT:    li 3, 255
-; AIX32-NEXT:    stw 5, 0(30)
-; AIX32-NEXT:    slw 5, 6, 23
-; AIX32-NEXT:    slw 6, 4, 23
-; AIX32-NEXT:    slw 3, 3, 23
+; AIX32-NEXT:    lwz 4, 60(1)
+; AIX32-NEXT:    lwz 3, 56(1)
+; AIX32-NEXT:    stw 4, 4(30)
+; AIX32-NEXT:    lbz 4, 0(28)
+; AIX32-NEXT:    stw 3, 0(30)
+; AIX32-NEXT:    lbz 3, 0(29)
 ; AIX32-NEXT:    sync
-; AIX32-NEXT:    and 5, 5, 3
-; AIX32-NEXT:    and 6, 6, 3
+; AIX32-NEXT:    slw 5, 4, 21
+; AIX32-NEXT:    li 4, 255
+; AIX32-NEXT:    slw 6, 3, 21
+; AIX32-NEXT:    slw 4, 4, 21
+; AIX32-NEXT:    and 5, 5, 4
+; AIX32-NEXT:    and 6, 6, 4
 ; AIX32-NEXT:  L..BB3_19: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 8, 0, 19
-; AIX32-NEXT:    and 7, 8, 3
+; AIX32-NEXT:    lwarx 8, 0, 18
+; AIX32-NEXT:    and 7, 8, 4
 ; AIX32-NEXT:    cmpw 7, 6
 ; AIX32-NEXT:    bne 0, L..BB3_21
 ; AIX32-NEXT:  # %bb.20: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    andc 8, 8, 3
+; AIX32-NEXT:    andc 8, 8, 4
 ; AIX32-NEXT:    or 8, 8, 5
-; AIX32-NEXT:    stwcx. 8, 0, 19
+; AIX32-NEXT:    stwcx. 8, 0, 18
 ; AIX32-NEXT:    bne 0, L..BB3_19
 ; AIX32-NEXT:  L..BB3_21: # %entry
-; AIX32-NEXT:    srw 5, 7, 23
+; AIX32-NEXT:    srw 4, 7, 21
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    li 3, 1
-; AIX32-NEXT:    li 7, 255
-; AIX32-NEXT:    cmpw 5, 4
 ; AIX32-NEXT:    lbz 5, 0(28)
+; AIX32-NEXT:    cmpw 4, 3
+; AIX32-NEXT:    li 3, 1
+; AIX32-NEXT:    slw 6, 5, 24
+; AIX32-NEXT:    li 5, 255
+; AIX32-NEXT:    slw 5, 5, 24
+; AIX32-NEXT:    iseleq 4, 3, 25
+; AIX32-NEXT:    and 6, 6, 5
+; AIX32-NEXT:    stw 4, 0(27)
 ; AIX32-NEXT:    lbz 4, 0(29)
-; AIX32-NEXT:    iseleq 6, 3, 26
-; AIX32-NEXT:    stw 6, 0(27)
-; AIX32-NEXT:    slw 5, 5, 25
-; AIX32-NEXT:    slw 8, 4, 25
-; AIX32-NEXT:    slw 6, 7, 25
-; AIX32-NEXT:    sync
-; AIX32-NEXT:    and 7, 5, 6
-; AIX32-NEXT:    and 8, 8, 6
+; AIX32-NEXT:    sync
+; AIX32-NEXT:    slw 7, 4, 24
+; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:  L..BB3_22: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 9, 0, 22
-; AIX32-NEXT:    and 5, 9, 6
-; AIX32-NEXT:    cmpw 5, 8
+; AIX32-NEXT:    lwarx 9, 0, 20
+; AIX32-NEXT:    and 8, 9, 5
+; AIX32-NEXT:    cmpw 8, 7
 ; AIX32-NEXT:    bne 0, L..BB3_24
 ; AIX32-NEXT:  # %bb.23: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    andc 9, 9, 6
-; AIX32-NEXT:    or 9, 9, 7
-; AIX32-NEXT:    stwcx. 9, 0, 22
+; AIX32-NEXT:    andc 9, 9, 5
+; AIX32-NEXT:    or 9, 9, 6
+; AIX32-NEXT:    stwcx. 9, 0, 20
 ; AIX32-NEXT:    bne 0, L..BB3_22
 ; AIX32-NEXT:  L..BB3_24: # %entry
+; AIX32-NEXT:    srw 5, 8, 24
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    srw 5, 5, 25
-; AIX32-NEXT:    lbz 6, 0(28)
 ; AIX32-NEXT:    cmpw 5, 4
+; AIX32-NEXT:    lbz 5, 0(28)
+; AIX32-NEXT:    extsb 5, 5
+; AIX32-NEXT:    slw 6, 5, 26
 ; AIX32-NEXT:    li 5, 0
+; AIX32-NEXT:    iseleq 4, 3, 25
+; AIX32-NEXT:    stw 4, 0(27)
 ; AIX32-NEXT:    lbz 4, 0(29)
-; AIX32-NEXT:    iseleq 7, 3, 26
-; AIX32-NEXT:    ori 5, 5, 65535
-; AIX32-NEXT:    extsb 6, 6
-; AIX32-NEXT:    stw 7, 0(27)
-; AIX32-NEXT:    slw 7, 6, 24
-; AIX32-NEXT:    slw 8, 4, 24
 ; AIX32-NEXT:    sync
-; AIX32-NEXT:    slw 6, 5, 24
-; AIX32-NEXT:    and 7, 7, 6
-; AIX32-NEXT:    and 8, 8, 6
+; AIX32-NEXT:    ori 5, 5, 65535
+; AIX32-NEXT:    slw 5, 5, 26
+; AIX32-NEXT:    slw 7, 4, 26
+; AIX32-NEXT:    and 6, 6, 5
+; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:  L..BB3_25: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 9, 0, 20
-; AIX32-NEXT:    and 5, 9, 6
-; AIX32-NEXT:    cmpw 5, 8
+; AIX32-NEXT:    lwarx 9, 0, 22
+; AIX32-NEXT:    and 8, 9, 5
+; AIX32-NEXT:    cmpw 8, 7
 ; AIX32-NEXT:    bne 0, L..BB3_27
 ; AIX32-NEXT:  # %bb.26: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    andc 9, 9, 6
-; AIX32-NEXT:    or 9, 9, 7
-; AIX32-NEXT:    stwcx. 9, 0, 20
+; AIX32-NEXT:    andc 9, 9, 5
+; AIX32-NEXT:    or 9, 9, 6
+; AIX32-NEXT:    stwcx. 9, 0, 22
 ; AIX32-NEXT:    bne 0, L..BB3_25
 ; AIX32-NEXT:  L..BB3_27: # %entry
+; AIX32-NEXT:    srw 5, 8, 26
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    srw 5, 5, 24
-; AIX32-NEXT:    lbz 6, 0(28)
 ; AIX32-NEXT:    cmpw 5, 4
+; AIX32-NEXT:    lbz 5, 0(28)
+; AIX32-NEXT:    extsb 5, 5
+; AIX32-NEXT:    slw 6, 5, 23
 ; AIX32-NEXT:    li 5, 0
+; AIX32-NEXT:    iseleq 4, 3, 25
+; AIX32-NEXT:    stw 4, 0(27)
 ; AIX32-NEXT:    lbz 4, 0(29)
-; AIX32-NEXT:    iseleq 7, 3, 26
-; AIX32-NEXT:    ori 5, 5, 65535
-; AIX32-NEXT:    extsb 6, 6
-; AIX32-NEXT:    stw 7, 0(27)
-; AIX32-NEXT:    slw 6, 6, 21
-; AIX32-NEXT:    slw 7, 4, 21
 ; AIX32-NEXT:    sync
-; AIX32-NEXT:    slw 5, 5, 21
+; AIX32-NEXT:    ori 5, 5, 65535
+; AIX32-NEXT:    slw 5, 5, 23
+; AIX32-NEXT:    slw 7, 4, 23
 ; AIX32-NEXT:    and 6, 6, 5
 ; AIX32-NEXT:    and 7, 7, 5
 ; AIX32-NEXT:  L..BB3_28: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 9, 0, 18
+; AIX32-NEXT:    lwarx 9, 0, 19
 ; AIX32-NEXT:    and 8, 9, 5
 ; AIX32-NEXT:    cmpw 8, 7
 ; AIX32-NEXT:    bne 0, L..BB3_30
 ; AIX32-NEXT:  # %bb.29: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    andc 9, 9, 5
 ; AIX32-NEXT:    or 9, 9, 6
-; AIX32-NEXT:    stwcx. 9, 0, 18
+; AIX32-NEXT:    stwcx. 9, 0, 19
 ; AIX32-NEXT:    bne 0, L..BB3_28
 ; AIX32-NEXT:  L..BB3_30: # %entry
-; AIX32-NEXT:    srw 5, 8, 21
+; AIX32-NEXT:    srw 5, 8, 23
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    cmpw 5, 4
 ; AIX32-NEXT:    lbz 5, 0(28)
-; AIX32-NEXT:    iseleq 4, 3, 26
+; AIX32-NEXT:    extsb 5, 5
+; AIX32-NEXT:    iseleq 4, 3, 25
 ; AIX32-NEXT:    stw 4, 0(27)
 ; AIX32-NEXT:    lbz 4, 0(29)
-; AIX32-NEXT:    extsb 5, 5
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB3_31: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 6, 0, 17
 ; AIX32-NEXT:    cmpw 1, 6, 4
 ; AIX32-NEXT:    bne 1, L..BB3_33
 ; AIX32-NEXT:  # %bb.32: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    stwcx. 5, 0, 17
 ; AIX32-NEXT:    bne 0, L..BB3_31
 ; AIX32-NEXT:  L..BB3_33: # %entry
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    isel 4, 3, 26, 6
+; AIX32-NEXT:    isel 4, 3, 25, 6
 ; AIX32-NEXT:    lbz 5, 0(28)
 ; AIX32-NEXT:    stw 4, 0(27)
 ; AIX32-NEXT:    lbz 4, 0(29)
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:    extsb 5, 5
 ; AIX32-NEXT:  L..BB3_34: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 6, 0, 27
 ; AIX32-NEXT:    cmpw 1, 6, 4
 ; AIX32-NEXT:    bne 1, L..BB3_36
 ; AIX32-NEXT:  # %bb.35: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    stwcx. 5, 0, 27
 ; AIX32-NEXT:    bne 0, L..BB3_34
 ; AIX32-NEXT:  L..BB3_36: # %entry
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    isel 3, 3, 26, 6
+; AIX32-NEXT:    isel 3, 3, 25, 6
+; AIX32-NEXT:    addi 4, 1, 56
 ; AIX32-NEXT:    li 7, 5
-; AIX32-NEXT:    li 8, 5
-; AIX32-NEXT:    lbz 4, 0(28)
-; AIX32-NEXT:    lbz 9, 0(29)
 ; AIX32-NEXT:    stw 3, 0(27)
-; AIX32-NEXT:    mr 3, 31
-; AIX32-NEXT:    extsb 6, 4
-; AIX32-NEXT:    addi 4, 1, 56
+; AIX32-NEXT:    lbz 3, 0(28)
+; AIX32-NEXT:    li 8, 5
+; AIX32-NEXT:    stw 25, 56(1)
+; AIX32-NEXT:    extsb 6, 3
+; AIX32-NEXT:    lbz 3, 0(29)
 ; AIX32-NEXT:    srawi 5, 6, 31
-; AIX32-NEXT:    stw 9, 60(1)
-; AIX32-NEXT:    stw 26, 56(1)
+; AIX32-NEXT:    stw 3, 60(1)
+; AIX32-NEXT:    mr 3, 31
 ; AIX32-NEXT:    bl .__atomic_compare_exchange_8[PR]
 ; AIX32-NEXT:    nop
-; AIX32-NEXT:    lbz 4, 0(28)
-; AIX32-NEXT:    lbz 9, 0(29)
-; AIX32-NEXT:    li 7, 5
-; AIX32-NEXT:    li 8, 5
 ; AIX32-NEXT:    stw 3, 0(27)
-; AIX32-NEXT:    mr 3, 30
-; AIX32-NEXT:    extsb 6, 4
+; AIX32-NEXT:    lbz 3, 0(28)
 ; AIX32-NEXT:    addi 4, 1, 56
+; AIX32-NEXT:    li 7, 5
+; AIX32-NEXT:    li 8, 5
+; AIX32-NEXT:    extsb 6, 3
+; AIX32-NEXT:    lbz 3, 0(29)
+; AIX32-NEXT:    stw 25, 56(1)
 ; AIX32-NEXT:    srawi 5, 6, 31
-; AIX32-NEXT:    stw 9, 60(1)
-; AIX32-NEXT:    stw 26, 56(1)
+; AIX32-NEXT:    stw 3, 60(1)
+; AIX32-NEXT:    mr 3, 30
 ; AIX32-NEXT:    bl .__atomic_compare_exchange_8[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    stw 3, 0(27)
 ; AIX32-NEXT:    lwz 31, 124(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 30, 120(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 29, 116(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 28, 112(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 27, 108(1) # 4-byte Folded Reload

 ; AIX32-LABEL: test_lock:
 ; AIX32:       # %bb.0: # %entry
 ; AIX32-NEXT:    mflr 0
 ; AIX32-NEXT:    stwu 1, -96(1)
 ; AIX32-NEXT:    stw 0, 104(1)
 ; AIX32-NEXT:    stw 29, 84(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    lwz 29, L..C0(2) # @sc
 ; AIX32-NEXT:    li 3, 1
-; AIX32-NEXT:    li 5, 255
+; AIX32-NEXT:    li 6, 255
 ; AIX32-NEXT:    stw 23, 60(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 24, 64(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    rlwinm 4, 29, 3, 27, 28
 ; AIX32-NEXT:    stw 25, 68(1) # 4-byte Folded Spill
-; AIX32-NEXT:    xori 4, 4, 24
 ; AIX32-NEXT:    stw 26, 72(1) # 4-byte Folded Spill
-; AIX32-NEXT:    slw 8, 3, 4
-; AIX32-NEXT:    slw 6, 5, 4
 ; AIX32-NEXT:    stw 27, 76(1) # 4-byte Folded Spill
+; AIX32-NEXT:    xori 4, 4, 24
 ; AIX32-NEXT:    stw 28, 80(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 30, 88(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 31, 92(1) # 4-byte Folded Spill
-; AIX32-NEXT:    rlwinm 7, 29, 0, 0, 29
-; AIX32-NEXT:    and 8, 8, 6
+; AIX32-NEXT:    slw 7, 3, 4
+; AIX32-NEXT:    slw 6, 6, 4
 ; AIX32-NEXT:    sync
+; AIX32-NEXT:    rlwinm 5, 29, 0, 0, 29
+; AIX32-NEXT:    and 7, 7, 6
 ; AIX32-NEXT:  L..BB4_1: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 5, 0, 7
-; AIX32-NEXT:    andc 9, 5, 6
-; AIX32-NEXT:    or 9, 8, 9
-; AIX32-NEXT:    stwcx. 9, 0, 7
+; AIX32-NEXT:    lwarx 8, 0, 5
+; AIX32-NEXT:    andc 9, 8, 6
+; AIX32-NEXT:    or 9, 7, 9
+; AIX32-NEXT:    stwcx. 9, 0, 5
 ; AIX32-NEXT:    bne 0, L..BB4_1
 ; AIX32-NEXT:  # %bb.2: # %entry
+; AIX32-NEXT:    srw 4, 8, 4
 ; AIX32-NEXT:    lwz 28, L..C1(2) # @uc
-; AIX32-NEXT:    srw 4, 5, 4
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    li 5, 255
+; AIX32-NEXT:    li 6, 255
 ; AIX32-NEXT:    clrlwi 4, 4, 24
+; AIX32-NEXT:    rlwinm 5, 28, 0, 0, 29
 ; AIX32-NEXT:    stb 4, 0(29)
 ; AIX32-NEXT:    rlwinm 4, 28, 3, 27, 28
-; AIX32-NEXT:    rlwinm 6, 28, 0, 0, 29
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:    xori 4, 4, 24
 ; AIX32-NEXT:    slw 7, 3, 4
-; AIX32-NEXT:    slw 5, 5, 4
-; AIX32-NEXT:    and 7, 7, 5
+; AIX32-NEXT:    slw 6, 6, 4
+; AIX32-NEXT:    and 7, 7, 6
 ; AIX32-NEXT:  L..BB4_3: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 8, 0, 6
-; AIX32-NEXT:    andc 9, 8, 5
+; AIX32-NEXT:    lwarx 8, 0, 5
+; AIX32-NEXT:    andc 9, 8, 6
 ; AIX32-NEXT:    or 9, 7, 9
-; AIX32-NEXT:    stwcx. 9, 0, 6
+; AIX32-NEXT:    stwcx. 9, 0, 5
 ; AIX32-NEXT:    bne 0, L..BB4_3
 ; AIX32-NEXT:  # %bb.4: # %entry
-; AIX32-NEXT:    lwz 27, L..C2(2) # @ss
 ; AIX32-NEXT:    srw 4, 8, 4
+; AIX32-NEXT:    lwz 27, L..C2(2) # @ss
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    li 5, 0
+; AIX32-NEXT:    li 6, 0
 ; AIX32-NEXT:    clrlwi 4, 4, 24
-; AIX32-NEXT:    ori 5, 5, 65535
+; AIX32-NEXT:    ori 6, 6, 65535
+; AIX32-NEXT:    rlwinm 5, 27, 0, 0, 29
 ; AIX32-NEXT:    stb 4, 0(28)
 ; AIX32-NEXT:    rlwinm 4, 27, 3, 27, 27
-; AIX32-NEXT:    rlwinm 6, 27, 0, 0, 29
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:    xori 4, 4, 16
 ; AIX32-NEXT:    slw 7, 3, 4
-; AIX32-NEXT:    slw 5, 5, 4
-; AIX32-NEXT:    and 7, 7, 5
+; AIX32-NEXT:    slw 6, 6, 4
+; AIX32-NEXT:    and 7, 7, 6
 ; AIX32-NEXT:  L..BB4_5: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 8, 0, 6
-; AIX32-NEXT:    andc 9, 8, 5
+; AIX32-NEXT:    lwarx 8, 0, 5
+; AIX32-NEXT:    andc 9, 8, 6
 ; AIX32-NEXT:    or 9, 7, 9
-; AIX32-NEXT:    stwcx. 9, 0, 6
+; AIX32-NEXT:    stwcx. 9, 0, 5
 ; AIX32-NEXT:    bne 0, L..BB4_5
 ; AIX32-NEXT:  # %bb.6: # %entry
-; AIX32-NEXT:    lwz 26, L..C3(2) # @us
 ; AIX32-NEXT:    srw 4, 8, 4
+; AIX32-NEXT:    lwz 26, L..C3(2) # @us
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    li 5, 0
+; AIX32-NEXT:    li 6, 0
 ; AIX32-NEXT:    clrlwi 4, 4, 16
-; AIX32-NEXT:    ori 5, 5, 65535
+; AIX32-NEXT:    ori 6, 6, 65535
+; AIX32-NEXT:    rlwinm 5, 26, 0, 0, 29
 ; AIX32-NEXT:    sth 4, 0(27)
 ; AIX32-NEXT:    rlwinm 4, 26, 3, 27, 27
-; AIX32-NEXT:    rlwinm 6, 26, 0, 0, 29
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:    xori 4, 4, 16
 ; AIX32-NEXT:    slw 7, 3, 4
-; AIX32-NEXT:    slw 5, 5, 4
-; AIX32-NEXT:    and 7, 7, 5
+; AIX32-NEXT:    slw 6, 6, 4
+; AIX32-NEXT:    and 7, 7, 6
 ; AIX32-NEXT:  L..BB4_7: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 8, 0, 6
-; AIX32-NEXT:    andc 9, 8, 5
+; AIX32-NEXT:    lwarx 8, 0, 5
+; AIX32-NEXT:    andc 9, 8, 6
 ; AIX32-NEXT:    or 9, 7, 9
-; AIX32-NEXT:    stwcx. 9, 0, 6
+; AIX32-NEXT:    stwcx. 9, 0, 5
 ; AIX32-NEXT:    bne 0, L..BB4_7
 ; AIX32-NEXT:  # %bb.8: # %entry
 ; AIX32-NEXT:    srw 4, 8, 4
-; AIX32-NEXT:    lwz 25, L..C4(2) # @si
 ; AIX32-NEXT:    lwsync
+; AIX32-NEXT:    lwz 25, L..C4(2) # @si
 ; AIX32-NEXT:    clrlwi 4, 4, 16
 ; AIX32-NEXT:    sth 4, 0(26)
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB4_9: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 25
 ; AIX32-NEXT:    stwcx. 3, 0, 25
 ; AIX32-NEXT:    bne 0, L..BB4_9
 ; AIX32-NEXT:  # %bb.10: # %entry
-; AIX32-NEXT:    lwz 24, L..C5(2) # @ui
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    stw 4, 0(25)
+; AIX32-NEXT:    lwz 24, L..C5(2) # @ui
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB4_11: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 24
 ; AIX32-NEXT:    stwcx. 3, 0, 24
 ; AIX32-NEXT:    bne 0, L..BB4_11
 ; AIX32-NEXT:  # %bb.12: # %entry
 ; AIX32-NEXT:    lwz 31, L..C6(2) # @sll
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    stw 4, 0(24)
+; AIX32-NEXT:    mr 3, 31
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 1
 ; AIX32-NEXT:    li 6, 5
 ; AIX32-NEXT:    li 23, 0
-; AIX32-NEXT:    mr 3, 31
 ; AIX32-NEXT:    bl .__atomic_exchange_8[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    lwz 30, L..C7(2) # @ull
-; AIX32-NEXT:    mr 7, 3
-; AIX32-NEXT:    mr 8, 4
+; AIX32-NEXT:    stw 4, 4(31)
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 1
 ; AIX32-NEXT:    li 6, 5
-; AIX32-NEXT:    stw 8, 4(31)
-; AIX32-NEXT:    stw 7, 0(31)
+; AIX32-NEXT:    stw 3, 0(31)
 ; AIX32-NEXT:    mr 3, 30
 ; AIX32-NEXT:    bl .__atomic_exchange_8[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    stw 4, 4(30)
 ; AIX32-NEXT:    stw 3, 0(30)
 ; AIX32-NEXT:    sync
-; AIX32-NEXT:    mr 3, 31
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 0
-; AIX32-NEXT:    li 6, 3
+; AIX32-NEXT:    mr 3, 31
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    stb 23, 0(29)
+; AIX32-NEXT:    li 6, 3
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    stb 23, 0(28)
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    sth 23, 0(27)
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    sth 23, 0(26)
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    stw 23, 0(25)
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    stw 23, 0(24)
 ; AIX32-NEXT:    bl .__atomic_store_8[PR]
 ; AIX32-NEXT:    nop
-; AIX32-NEXT:    mr 3, 30
 ; AIX32-NEXT:    li 4, 0
 ; AIX32-NEXT:    li 5, 0
+; AIX32-NEXT:    mr 3, 30
 ; AIX32-NEXT:    li 6, 3
 ; AIX32-NEXT:    bl .__atomic_store_8[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    lwz 31, 92(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 30, 88(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 29, 84(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 28, 80(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    lwz 27, 76(1) # 4-byte Folded Reload

 ; CHECK-NEXT:    li 4, 55
 ; CHECK-NEXT:    isel 3, 4, 3, 6
 ; CHECK-NEXT:    blr
 ;
 ; AIX32-LABEL: cmpswplp:
 ; AIX32:       # %bb.0: # %entry
 ; AIX32-NEXT:    mflr 0
 ; AIX32-NEXT:    stwu 1, -64(1)
-; AIX32-NEXT:    addic 7, 6, 1
+; AIX32-NEXT:    addic 9, 6, 1
 ; AIX32-NEXT:    stw 0, 72(1)
-; AIX32-NEXT:    addi 4, 1, 56
-; AIX32-NEXT:    addze 8, 5
-; AIX32-NEXT:    stw 6, 60(1)
-; AIX32-NEXT:    mr 6, 7
+; AIX32-NEXT:    addze 7, 5
 ; AIX32-NEXT:    stw 5, 56(1)
-; AIX32-NEXT:    mr 5, 8
+; AIX32-NEXT:    addi 4, 1, 56
+; AIX32-NEXT:    mr 5, 7
 ; AIX32-NEXT:    li 7, 0
 ; AIX32-NEXT:    li 8, 0
+; AIX32-NEXT:    stw 6, 60(1)
+; AIX32-NEXT:    mr 6, 9
 ; AIX32-NEXT:    bl .__atomic_compare_exchange_8[PR]
 ; AIX32-NEXT:    nop
 ; AIX32-NEXT:    andi. 3, 3, 1
-; AIX32-NEXT:    li 4, 55
 ; AIX32-NEXT:    li 3, 66
+; AIX32-NEXT:    li 4, 55
 ; AIX32-NEXT:    iselgt 4, 4, 3
 ; AIX32-NEXT:    li 3, 0
 ; AIX32-NEXT:    addi 1, 1, 64
 ; AIX32-NEXT:    lwz 0, 8(1)
 ; AIX32-NEXT:    mtlr 0
 ; AIX32-NEXT:    blr
 entry:
   %add = add nsw i64 %newval, 1

 ; CHECK-NEXT:    isel 3, 4, 3, 5
 ; CHECK-NEXT:    blr
 ;
 ; AIX32-LABEL: atommax8:
 ; AIX32:       # %bb.0: # %entry
 ; AIX32-NEXT:    mflr 0
 ; AIX32-NEXT:    stwu 1, -80(1)
 ; AIX32-NEXT:    stw 0, 88(1)
+; AIX32-NEXT:    stw 30, 72(1) # 4-byte Folded Spill
+; AIX32-NEXT:    mr 30, 4
+; AIX32-NEXT:    lwz 4, 4(3)
+; AIX32-NEXT:    lwz 7, 0(3)
 ; AIX32-NEXT:    stw 28, 64(1) # 4-byte Folded Spill
-; AIX32-NEXT:    lwz 9, 4(3)
-; AIX32-NEXT:    lwz 10, 0(3)
 ; AIX32-NEXT:    addi 28, 1, 56
 ; AIX32-NEXT:    stw 29, 68(1) # 4-byte Folded Spill
-; AIX32-NEXT:    stw 30, 72(1) # 4-byte Folded Spill
+; AIX32-NEXT:    mr 29, 3
 ; AIX32-NEXT:    stw 31, 76(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    mr 31, 5
-; AIX32-NEXT:    mr 29, 3
-; AIX32-NEXT:    mr 30, 4
 ; AIX32-NEXT:    .align 4
 ; AIX32-NEXT:  L..BB7_1: # %atomicrmw.start
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    cmplw 10, 30
-; AIX32-NEXT:    cmpw 1, 10, 30
+; AIX32-NEXT:    cmplw 7, 30
+; AIX32-NEXT:    stw 7, 56(1)
 ; AIX32-NEXT:    mr 3, 29
-; AIX32-NEXT:    mr 4, 28
-; AIX32-NEXT:    crandc 20, 5, 2
-; AIX32-NEXT:    cmplw 1, 9, 31
-; AIX32-NEXT:    li 7, 5
+; AIX32-NEXT:    cmpw 1, 7, 30
 ; AIX32-NEXT:    li 8, 5
+; AIX32-NEXT:    crandc 20, 5, 2
+; AIX32-NEXT:    cmplw 1, 4, 31
+; AIX32-NEXT:    stw 4, 60(1)
 ; AIX32-NEXT:    crand 21, 2, 5
-; AIX32-NEXT:    stw 10, 56(1)
-; AIX32-NEXT:    stw 9, 60(1)
 ; AIX32-NEXT:    cror 20, 21, 20
-; AIX32-NEXT:    isel 5, 10, 30, 20
-; AIX32-NEXT:    isel 6, 9, 31, 20
+; AIX32-NEXT:    isel 5, 7, 30, 20
+; AIX32-NEXT:    isel 6, 4, 31, 20
+; AIX32-NEXT:    li 7, 5
+; AIX32-NEXT:    mr 4, 28
 ; AIX32-NEXT:    bl .__atomic_compare_exchange_8[PR]
 ; AIX32-NEXT:    nop
-; AIX32-NEXT:    lwz 9, 60(1)
-; AIX32-NEXT:    lwz 10, 56(1)
 ; AIX32-NEXT:    cmplwi 3, 0
+; AIX32-NEXT:    lwz 4, 60(1)
+; AIX32-NEXT:    lwz 7, 56(1)
 ; AIX32-NEXT:    beq 0, L..BB7_1
 ; AIX32-NEXT:  # %bb.2: # %atomicrmw.end
-; AIX32-NEXT:    cmplw 10, 30
-; AIX32-NEXT:    cmpw 1, 10, 30
+; AIX32-NEXT:    cmplw 7, 30
 ; AIX32-NEXT:    li 3, 55
-; AIX32-NEXT:    li 4, 66
+; AIX32-NEXT:    lwz 29, 68(1) # 4-byte Folded Reload
+; AIX32-NEXT:    lwz 28, 64(1) # 4-byte Folded Reload
+; AIX32-NEXT:    cmpw 1, 7, 30
+; AIX32-NEXT:    lwz 30, 72(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    crandc 20, 5, 2
-; AIX32-NEXT:    cmplw 1, 9, 31
+; AIX32-NEXT:    cmplw 1, 4, 31
+; AIX32-NEXT:    li 4, 66
 ; AIX32-NEXT:    lwz 31, 76(1) # 4-byte Folded Reload
-; AIX32-NEXT:    lwz 30, 72(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    crand 21, 2, 5
-; AIX32-NEXT:    lwz 29, 68(1) # 4-byte Folded Reload
-; AIX32-NEXT:    lwz 28, 64(1) # 4-byte Folded Reload
 ; AIX32-NEXT:    cror 20, 21, 20
 ; AIX32-NEXT:    isel 4, 4, 3, 20
 ; AIX32-NEXT:    li 3, 0
 ; AIX32-NEXT:    addi 1, 1, 80
 ; AIX32-NEXT:    lwz 0, 8(1)
 ; AIX32-NEXT:    mtlr 0
 ; AIX32-NEXT:    blr
 entry:

 ; CHECK-NEXT:    li 3, 55
 ; CHECK-NEXT:    li 4, 66
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:    isel 3, 4, 3, 5
 ; CHECK-NEXT:    blr
 ;
 ; AIX32-LABEL: atommax2:
 ; AIX32:       # %bb.0: # %entry
+; AIX32-NEXT:    rlwinm 6, 3, 3, 27, 27
 ; AIX32-NEXT:    li 7, 0
-; AIX32-NEXT:    rlwinm 5, 3, 3, 27, 27
-; AIX32-NEXT:    extsh 6, 4
 ; AIX32-NEXT:    sync
-; AIX32-NEXT:    xori 5, 5, 16
-; AIX32-NEXT:    ori 7, 7, 65535
-; AIX32-NEXT:    slw 8, 6, 5
-; AIX32-NEXT:    slw 7, 7, 5
+; AIX32-NEXT:    extsh 5, 4
 ; AIX32-NEXT:    rlwinm 3, 3, 0, 0, 29
+; AIX32-NEXT:    xori 6, 6, 16
+; AIX32-NEXT:    ori 7, 7, 65535
+; AIX32-NEXT:    slw 8, 5, 6
+; AIX32-NEXT:    slw 7, 7, 6
 ; AIX32-NEXT:    and 8, 8, 7
 ; AIX32-NEXT:  L..BB9_1: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 9, 0, 3
 ; AIX32-NEXT:    and 10, 9, 7
-; AIX32-NEXT:    srw 10, 10, 5
+; AIX32-NEXT:    srw 10, 10, 6
 ; AIX32-NEXT:    extsh 10, 10
-; AIX32-NEXT:    cmpw 10, 6
+; AIX32-NEXT:    cmpw 10, 5
 ; AIX32-NEXT:    bgt 0, L..BB9_3
 ; AIX32-NEXT:  # %bb.2: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    andc 10, 9, 7
 ; AIX32-NEXT:    or 10, 8, 10
 ; AIX32-NEXT:    stwcx. 10, 0, 3
 ; AIX32-NEXT:    bne 0, L..BB9_1
 ; AIX32-NEXT:  L..BB9_3: # %entry
-; AIX32-NEXT:    srw 3, 9, 5
+; AIX32-NEXT:    srw 3, 9, 6
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    clrlwi 3, 3, 16
 ; AIX32-NEXT:    extsh 3, 3
 ; AIX32-NEXT:    cmpw 3, 4
 ; AIX32-NEXT:    li 3, 55
 ; AIX32-NEXT:    li 4, 66
 ; AIX32-NEXT:    iselgt 3, 4, 3
 ; AIX32-NEXT:    blr

 ; CHECK-NEXT:    isel 3, 4, 3, 5
 ; CHECK-NEXT:    blr
 ;
 ; AIX32-LABEL: atommax1:
 ; AIX32:       # %bb.0: # %entry
 ; AIX32-NEXT:    rlwinm 5, 3, 3, 27, 28
 ; AIX32-NEXT:    li 7, 255
 ; AIX32-NEXT:    sync
-; AIX32-NEXT:    xori 5, 5, 24
 ; AIX32-NEXT:    rlwinm 3, 3, 0, 0, 29
+; AIX32-NEXT:    xori 5, 5, 24
 ; AIX32-NEXT:    slw 6, 4, 5
 ; AIX32-NEXT:    slw 7, 7, 5
 ; AIX32-NEXT:    and 8, 6, 7
 ; AIX32-NEXT:  L..BB10_1: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 9, 0, 3
 ; AIX32-NEXT:    and 10, 9, 7
 ; AIX32-NEXT:    cmplw 10, 6

llvm/test/CodeGen/PowerPC/atomics-i128-ldst.ll

 ;
 ; PWR7-LABEL: stq_unordered:
 ; PWR7:       # %bb.0: # %entry
 ; PWR7-NEXT:    mflr r0
 ; PWR7-NEXT:    stdu r1, -112(r1)
 ; PWR7-NEXT:    std r0, 128(r1)
 ; PWR7-NEXT:    .cfi_def_cfa_offset 112
 ; PWR7-NEXT:    .cfi_offset lr, 16
-; PWR7-NEXT:    mr r6, r4
+; PWR7-NEXT:    mr r7, r4
+; PWR7-NEXT:    li r6, 0
 ; PWR7-NEXT:    mr r4, r3
 ; PWR7-NEXT:    mr r3, r5
-; PWR7-NEXT:    mr r5, r6
-; PWR7-NEXT:    li r6, 0
+; PWR7-NEXT:    mr r5, r7
 ; PWR7-NEXT:    bl __atomic_store_16
 ; PWR7-NEXT:    nop
 ; PWR7-NEXT:    addi r1, r1, 112
 ; PWR7-NEXT:    ld r0, 16(r1)
 ; PWR7-NEXT:    mtlr r0
 ; PWR7-NEXT:    blr
 ;
 ; LE-PWR8-LABEL: stq_unordered:

 ;
 ; PWR7-LABEL: stq_big_offset_unordered:
 ; PWR7:       # %bb.0: # %entry
 ; PWR7-NEXT:    mflr r0
 ; PWR7-NEXT:    stdu r1, -112(r1)
 ; PWR7-NEXT:    std r0, 128(r1)
 ; PWR7-NEXT:    .cfi_def_cfa_offset 112
 ; PWR7-NEXT:    .cfi_offset lr, 16
-; PWR7-NEXT:    mr r6, r4
+; PWR7-NEXT:    mr r7, r4
 ; PWR7-NEXT:    mr r4, r3
 ; PWR7-NEXT:    addis r3, r5, 32
-; PWR7-NEXT:    mr r5, r6
 ; PWR7-NEXT:    li r6, 0
+; PWR7-NEXT:    mr r5, r7
 ; PWR7-NEXT:    bl __atomic_store_16
 ; PWR7-NEXT:    nop
 ; PWR7-NEXT:    addi r1, r1, 112
 ; PWR7-NEXT:    ld r0, 16(r1)
 ; PWR7-NEXT:    mtlr r0
 ; PWR7-NEXT:    blr
 ;
 ; LE-PWR8-LABEL: stq_big_offset_unordered:

 ;
 ; PWR7-LABEL: stq_monotonic:
 ; PWR7:       # %bb.0: # %entry
 ; PWR7-NEXT:    mflr r0
 ; PWR7-NEXT:    stdu r1, -112(r1)
 ; PWR7-NEXT:    std r0, 128(r1)
 ; PWR7-NEXT:    .cfi_def_cfa_offset 112
 ; PWR7-NEXT:    .cfi_offset lr, 16
-; PWR7-NEXT:    mr r6, r4
+; PWR7-NEXT:    mr r7, r4
+; PWR7-NEXT:    li r6, 0
 ; PWR7-NEXT:    mr r4, r3
 ; PWR7-NEXT:    mr r3, r5
-; PWR7-NEXT:    mr r5, r6
-; PWR7-NEXT:    li r6, 0
+; PWR7-NEXT:    mr r5, r7
 ; PWR7-NEXT:    bl __atomic_store_16
 ; PWR7-NEXT:    nop
 ; PWR7-NEXT:    addi r1, r1, 112
 ; PWR7-NEXT:    ld r0, 16(r1)
 ; PWR7-NEXT:    mtlr r0
 ; PWR7-NEXT:    blr
 ;
 ; LE-PWR8-LABEL: stq_monotonic:

 ;
 ; PWR7-LABEL: stq_release:
 ; PWR7:       # %bb.0: # %entry
 ; PWR7-NEXT:    mflr r0
 ; PWR7-NEXT:    stdu r1, -112(r1)
 ; PWR7-NEXT:    std r0, 128(r1)
 ; PWR7-NEXT:    .cfi_def_cfa_offset 112
 ; PWR7-NEXT:    .cfi_offset lr, 16
-; PWR7-NEXT:    mr r6, r4
+; PWR7-NEXT:    mr r7, r4
+; PWR7-NEXT:    li r6, 3
 ; PWR7-NEXT:    mr r4, r3
 ; PWR7-NEXT:    mr r3, r5
-; PWR7-NEXT:    mr r5, r6
-; PWR7-NEXT:    li r6, 3
+; PWR7-NEXT:    mr r5, r7
 ; PWR7-NEXT:    bl __atomic_store_16
 ; PWR7-NEXT:    nop
 ; PWR7-NEXT:    addi r1, r1, 112
 ; PWR7-NEXT:    ld r0, 16(r1)
 ; PWR7-NEXT:    mtlr r0
 ; PWR7-NEXT:    blr
 ;
 ; LE-PWR8-LABEL: stq_release:

 ;
 ; PWR7-LABEL: stq_seqcst:
 ; PWR7:       # %bb.0: # %entry
 ; PWR7-NEXT:    mflr r0
 ; PWR7-NEXT:    stdu r1, -112(r1)
 ; PWR7-NEXT:    std r0, 128(r1)
 ; PWR7-NEXT:    .cfi_def_cfa_offset 112
 ; PWR7-NEXT:    .cfi_offset lr, 16
-; PWR7-NEXT:    mr r6, r4
+; PWR7-NEXT:    mr r7, r4
+; PWR7-NEXT:    li r6, 5
 ; PWR7-NEXT:    mr r4, r3
 ; PWR7-NEXT:    mr r3, r5
-; PWR7-NEXT:    mr r5, r6
-; PWR7-NEXT:    li r6, 5
+; PWR7-NEXT:    mr r5, r7
 ; PWR7-NEXT:    bl __atomic_store_16
 ; PWR7-NEXT:    nop
 ; PWR7-NEXT:    addi r1, r1, 112
 ; PWR7-NEXT:    ld r0, 16(r1)
 ; PWR7-NEXT:    mtlr r0
 ; PWR7-NEXT:    blr
 ;
 ; LE-PWR8-LABEL: stq_seqcst:

llvm/test/CodeGen/PowerPC/atomics-i128.ll

 ;
 ; PWR7-LABEL: cas_weak_acquire_acquire:
 ; PWR7:       # %bb.0: # %entry
 ; PWR7-NEXT:    mflr r0
 ; PWR7-NEXT:    stdu r1, -128(r1)
 ; PWR7-NEXT:    std r0, 144(r1)
 ; PWR7-NEXT:    .cfi_def_cfa_offset 128
 ; PWR7-NEXT:    .cfi_offset lr, 16
-; PWR7-NEXT:    std r5, 120(r1)
+; PWR7-NEXT:    mr r9, r7
 ; PWR7-NEXT:    std r4, 112(r1)
 ; PWR7-NEXT:    addi r4, r1, 112
-; PWR7-NEXT:    mr r5, r6
-; PWR7-NEXT:    mr r6, r7
 ; PWR7-NEXT:    li r7, 2
 ; PWR7-NEXT:    li r8, 2
+; PWR7-NEXT:    std r5, 120(r1)
+; PWR7-NEXT:    mr r5, r6
+; PWR7-NEXT:    mr r6, r9
 ; PWR7-NEXT:    bl __atomic_compare_exchange_16
 ; PWR7-NEXT:    nop
 ; PWR7-NEXT:    ld r4, 120(r1)
 ; PWR7-NEXT:    ld r3, 112(r1)
 ; PWR7-NEXT:    addi r1, r1, 128
 ; PWR7-NEXT:    ld r0, 16(r1)
 ; PWR7-NEXT:    mtlr r0
 ; PWR7-NEXT:    blr

 ;
 ; PWR7-LABEL: cas_weak_release_monotonic:
 ; PWR7:       # %bb.0: # %entry
 ; PWR7-NEXT:    mflr r0
 ; PWR7-NEXT:    stdu r1, -128(r1)
 ; PWR7-NEXT:    std r0, 144(r1)
 ; PWR7-NEXT:    .cfi_def_cfa_offset 128
 ; PWR7-NEXT:    .cfi_offset lr, 16
-; PWR7-NEXT:    std r5, 120(r1)
+; PWR7-NEXT:    mr r9, r7
 ; PWR7-NEXT:    std r4, 112(r1)
 ; PWR7-NEXT:    addi r4, r1, 112
-; PWR7-NEXT:    mr r5, r6
-; PWR7-NEXT:    mr r6, r7
 ; PWR7-NEXT:    li r7, 3
 ; PWR7-NEXT:    li r8, 0
+; PWR7-NEXT:    std r5, 120(r1)
+; PWR7-NEXT:    mr r5, r6
+; PWR7-NEXT:    mr r6, r9
 ; PWR7-NEXT:    bl __atomic_compare_exchange_16
 ; PWR7-NEXT:    nop
 ; PWR7-NEXT:    ld r4, 120(r1)
 ; PWR7-NEXT:    ld r3, 112(r1)
 ; PWR7-NEXT:    addi r1, r1, 128
 ; PWR7-NEXT:    ld r0, 16(r1)
 ; PWR7-NEXT:    mtlr r0
 ; PWR7-NEXT:    blr

 ;
 ; PWR7-LABEL: cas_sc_sc:
 ; PWR7:       # %bb.0: # %entry
 ; PWR7-NEXT:    mflr r0
 ; PWR7-NEXT:    stdu r1, -128(r1)
 ; PWR7-NEXT:    std r0, 144(r1)
 ; PWR7-NEXT:    .cfi_def_cfa_offset 128
 ; PWR7-NEXT:    .cfi_offset lr, 16
-; PWR7-NEXT:    std r5, 120(r1)
+; PWR7-NEXT:    mr r9, r7
 ; PWR7-NEXT:    std r4, 112(r1)
 ; PWR7-NEXT:    addi r4, r1, 112
-; PWR7-NEXT:    mr r5, r6
-; PWR7-NEXT:    mr r6, r7
 ; PWR7-NEXT:    li r7, 5
 ; PWR7-NEXT:    li r8, 5
+; PWR7-NEXT:    std r5, 120(r1)
+; PWR7-NEXT:    mr r5, r6
+; PWR7-NEXT:    mr r6, r9
 ; PWR7-NEXT:    bl __atomic_compare_exchange_16
 ; PWR7-NEXT:    nop
 ; PWR7-NEXT:    ld r4, 120(r1)
 ; PWR7-NEXT:    ld r3, 112(r1)
 ; PWR7-NEXT:    addi r1, r1, 128
 ; PWR7-NEXT:    ld r0, 16(r1)
 ; PWR7-NEXT:    mtlr r0
 ; PWR7-NEXT:    blr

 ;
 ; PWR7-LABEL: cas_acqrel_acquire:
 ; PWR7:       # %bb.0: # %entry
 ; PWR7-NEXT:    mflr r0
 ; PWR7-NEXT:    stdu r1, -128(r1)
 ; PWR7-NEXT:    std r0, 144(r1)
 ; PWR7-NEXT:    .cfi_def_cfa_offset 128
 ; PWR7-NEXT:    .cfi_offset lr, 16
-; PWR7-NEXT:    std r5, 120(r1)
+; PWR7-NEXT:    mr r9, r7
 ; PWR7-NEXT:    std r4, 112(r1)
 ; PWR7-NEXT:    addi r4, r1, 112
-; PWR7-NEXT:    mr r5, r6
-; PWR7-NEXT:    mr r6, r7
 ; PWR7-NEXT:    li r7, 4
 ; PWR7-NEXT:    li r8, 2
+; PWR7-NEXT:    std r5, 120(r1)
+; PWR7-NEXT:    mr r5, r6
+; PWR7-NEXT:    mr r6, r9
 ; PWR7-NEXT:    bl __atomic_compare_exchange_16
 ; PWR7-NEXT:    nop
 ; PWR7-NEXT:    ld r4, 120(r1)
 ; PWR7-NEXT:    ld r3, 112(r1)
 ; PWR7-NEXT:    addi r1, r1, 128
 ; PWR7-NEXT:    ld r0, 16(r1)
 ; PWR7-NEXT:    mtlr r0
 ; PWR7-NEXT:    blr

 ;
 ; PWR7-LABEL: cas_acqrel_acquire_check_succ:
 ; PWR7:       # %bb.0: # %entry
 ; PWR7-NEXT:    mflr r0
 ; PWR7-NEXT:    stdu r1, -128(r1)
 ; PWR7-NEXT:    std r0, 144(r1)
 ; PWR7-NEXT:    .cfi_def_cfa_offset 128
 ; PWR7-NEXT:    .cfi_offset lr, 16
-; PWR7-NEXT:    std r5, 120(r1)
+; PWR7-NEXT:    mr r9, r7
 ; PWR7-NEXT:    std r4, 112(r1)
 ; PWR7-NEXT:    addi r4, r1, 112
-; PWR7-NEXT:    mr r5, r6
-; PWR7-NEXT:    mr r6, r7
 ; PWR7-NEXT:    li r7, 4
 ; PWR7-NEXT:    li r8, 2
+; PWR7-NEXT:    std r5, 120(r1)
+; PWR7-NEXT:    mr r5, r6
+; PWR7-NEXT:    mr r6, r9
 ; PWR7-NEXT:    bl __atomic_compare_exchange_16
 ; PWR7-NEXT:    nop
 ; PWR7-NEXT:    addi r1, r1, 128
 ; PWR7-NEXT:    ld r0, 16(r1)
 ; PWR7-NEXT:    mtlr r0
 ; PWR7-NEXT:    blr
 ;
 ; LE-PWR8-LABEL: cas_acqrel_acquire_check_succ:

llvm/test/CodeGen/PowerPC/bswap-load-store.ll

   ret i16 %tmp6
 }
 
 ; TODO: combine the bswap feeding a store on subtargets
 ; that do not have an STDBRX.
 define void @STDBRX(i64 %i, ptr %ptr, i64 %off) {
 ; PWR7_32-LABEL: STDBRX:
 ; PWR7_32:       # %bb.0:
-; PWR7_32-NEXT:    li r6, 4
-; PWR7_32-NEXT:    add r7, r5, r8
+; PWR7_32-NEXT:    add r6, r5, r8
 ; PWR7_32-NEXT:    stwbrx r4, r5, r8
-; PWR7_32-NEXT:    stwbrx r3, r7, r6
+; PWR7_32-NEXT:    li r4, 4
+; PWR7_32-NEXT:    stwbrx r3, r6, r4
 ; PWR7_32-NEXT:    blr
 ;
 ; X64-LABEL: STDBRX:
 ; X64:       # %bb.0:
 ; X64-NEXT:    rotldi r6, r3, 16
 ; X64-NEXT:    rotldi r7, r3, 8
 ; X64-NEXT:    rldimi r7, r6, 8, 48
 ; X64-NEXT:    rotldi r6, r3, 24

   %tmp13 = tail call i64 @llvm.bswap.i64( i64 %i )
   store i64 %tmp13, ptr %tmp1
   ret void
 }
 
 define i64 @LDBRX(ptr %ptr, i64 %off) {
 ; PWR7_32-LABEL: LDBRX:
 ; PWR7_32:       # %bb.0:
-; PWR7_32-NEXT:    li r5, 4
-; PWR7_32-NEXT:    add r7, r3, r6
+; PWR7_32-NEXT:    add r5, r3, r6
 ; PWR7_32-NEXT:    lwbrx r4, r3, r6
-; PWR7_32-NEXT:    lwbrx r3, r7, r5
+; PWR7_32-NEXT:    li r3, 4
+; PWR7_32-NEXT:    lwbrx r3, r5, r3
 ; PWR7_32-NEXT:    blr
 ;
 ; X64-LABEL: LDBRX:
 ; X64:       # %bb.0:
 ; X64-NEXT:    li r6, 4
 ; X64-NEXT:    lwbrx r5, r3, r4
 ; X64-NEXT:    add r3, r3, r4
 ; X64-NEXT:    lwbrx r3, r3, r6

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-move-tofrom-regs.ll

 ; CHECK-LABEL: test_mfmsr:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfmsr 3
 ; CHECK-NEXT:    clrldi 3, 3, 32
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-32BIT-LABEL: test_mfmsr:
 ; CHECK-32BIT:       # %bb.0: # %entry
-; CHECK-32BIT-NEXT:    mfmsr 4
 ; CHECK-32BIT-NEXT:    li 3, 0
+; CHECK-32BIT-NEXT:    mfmsr 4
 ; CHECK-32BIT-NEXT:    blr
 entry:
   %0 = tail call i32 @llvm.ppc.mfmsr()
   %conv = zext i32 %0 to i64
   ret i64 %conv
 }
 
 define dso_local void @test_mtmsr() {
-; CHECK-LABEL: test_mtmsr:
-; CHECK:    mtmsr 3
-; CHECK-NEXT:    blr
-;
 ; CHECK-32BIT-LABEL: test_mtmsr:
 ; CHECK-32BIT:       # %bb.0: # %entry
 ; CHECK-32BIT-NEXT:    lwz 3, L..C0(2) # @ula
 ; CHECK-32BIT-NEXT:    lwz 3, 4(3)
 ; CHECK-32BIT-NEXT:    mtmsr 3, 0
 ; CHECK-32BIT-NEXT:    blr
 entry:
   %0 = load i64, ptr @ula, align 8
   %conv = trunc i64 %0 to i32
   call void @llvm.ppc.mtmsr(i32 %conv)
   ret void
 }

llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll

 ; CHECK-NOVSX-NEXT:    addi r3, r1, -16
 ; CHECK-NOVSX-NEXT:    lvx v4, 0, r3
 ; CHECK-NOVSX-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-NOVSX-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: testmrglb3:
 ; CHECK-P7:       # %bb.0: # %entry
 ; CHECK-P7-NEXT:    ld r3, 0(r3)
-; CHECK-P7-NEXT:    addi r4, r1, -16
 ; CHECK-P7-NEXT:    xxlxor v4, v4, v4
 ; CHECK-P7-NEXT:    std r3, -16(r1)
+; CHECK-P7-NEXT:    addi r3, r1, -16
+; CHECK-P7-NEXT:    lxvd2x vs0, 0, r3
 ; CHECK-P7-NEXT:    addis r3, r2, .LCPI12_0@toc@ha
 ; CHECK-P7-NEXT:    addi r3, r3, .LCPI12_0@toc@l
-; CHECK-P7-NEXT:    lxvd2x vs0, 0, r4
-; CHECK-P7-NEXT:    lxvd2x vs1, 0, r3
 ; CHECK-P7-NEXT:    xxswapd v2, vs0
-; CHECK-P7-NEXT:    xxswapd v3, vs1
+; CHECK-P7-NEXT:    lxvd2x vs0, 0, r3
+; CHECK-P7-NEXT:    xxswapd v3, vs0
 ; CHECK-P7-NEXT:    vperm v2, v2, v4, v3
 ; CHECK-P7-NEXT:    blr
 ;
 ; P8-AIX-64-LABEL: testmrglb3:
 ; P8-AIX-64:       # %bb.0: # %entry
 ; P8-AIX-64-NEXT:    ld r4, L..C0(r2) # %const.0
 ; P8-AIX-64-NEXT:    lxsdx v2, 0, r3
 ; P8-AIX-64-NEXT:    xxlxor v4, v4, v4

 ; CHECK-NOVSX-NEXT:    addi r4, r4, .LCPI14_0@toc@l
 ; CHECK-NOVSX-NEXT:    lvx v3, 0, r3
 ; CHECK-NOVSX-NEXT:    lvx v2, 0, r4
 ; CHECK-NOVSX-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-NOVSX-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: no_crash_bitcast:
 ; CHECK-P7:       # %bb.0: # %entry
-; CHECK-P7-NEXT:    addis r4, r2, .LCPI14_0@toc@ha
 ; CHECK-P7-NEXT:    stw r3, -16(r1)
+; CHECK-P7-NEXT:    addis r3, r2, .LCPI14_0@toc@ha
+; CHECK-P7-NEXT:    addi r3, r3, .LCPI14_0@toc@l
+; CHECK-P7-NEXT:    lxvd2x vs0, 0, r3
 ; CHECK-P7-NEXT:    addi r3, r1, -16
-; CHECK-P7-NEXT:    addi r4, r4, .LCPI14_0@toc@l
-; CHECK-P7-NEXT:    lxvd2x vs1, 0, r3
-; CHECK-P7-NEXT:    lxvd2x vs0, 0, r4
-; CHECK-P7-NEXT:    xxswapd v3, vs1
 ; CHECK-P7-NEXT:    xxswapd v2, vs0
+; CHECK-P7-NEXT:    lxvd2x vs0, 0, r3
+; CHECK-P7-NEXT:    xxswapd v3, vs0
 ; CHECK-P7-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P7-NEXT:    blr
 ;
 ; P8-AIX-64-LABEL: no_crash_bitcast:
 ; P8-AIX-64:       # %bb.0: # %entry
 ; P8-AIX-64-NEXT:    mtfprwz f0, r3
 ; P8-AIX-64-NEXT:    xxmrghw v2, vs0, vs0
 ; P8-AIX-64-NEXT:    blr

 ; CHECK-NOVSX-NEXT:    addi r3, r4, .LCPI15_1@toc@l
 ; CHECK-NOVSX-NEXT:    lvx v4, 0, r3
 ; CHECK-NOVSX-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-NOVSX-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: replace_undefs_in_splat:
 ; CHECK-P7:       # %bb.0: # %entry
 ; CHECK-P7-NEXT:    addis r3, r2, .LCPI15_0@toc@ha
-; CHECK-P7-NEXT:    addis r4, r2, .LCPI15_1@toc@ha
 ; CHECK-P7-NEXT:    addi r3, r3, .LCPI15_0@toc@l
 ; CHECK-P7-NEXT:    lxvd2x vs0, 0, r3
-; CHECK-P7-NEXT:    addi r3, r4, .LCPI15_1@toc@l
-; CHECK-P7-NEXT:    lxvd2x vs1, 0, r3
+; CHECK-P7-NEXT:    addis r3, r2, .LCPI15_1@toc@ha
+; CHECK-P7-NEXT:    addi r3, r3, .LCPI15_1@toc@l
 ; CHECK-P7-NEXT:    xxswapd v3, vs0
-; CHECK-P7-NEXT:    xxswapd v4, vs1
+; CHECK-P7-NEXT:    lxvd2x vs0, 0, r3
+; CHECK-P7-NEXT:    xxswapd v4, vs0
 ; CHECK-P7-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P7-NEXT:    blr
 ;
 ; P8-AIX-64-LABEL: replace_undefs_in_splat:
 ; P8-AIX-64:       # %bb.0: # %entry
 ; P8-AIX-64-NEXT:    ld r3, L..C1(r2) # %const.0
 ; P8-AIX-64-NEXT:    ld r4, L..C2(r2) # %const.1
 ; P8-AIX-64-NEXT:    lxvw4x v3, 0, r3

 ; CHECK-NOVSX-NEXT:    std r3, -16(r1)
 ; CHECK-NOVSX-NEXT:    lvx v2, 0, r4
 ; CHECK-NOVSX-NEXT:    vspltw v2, v2, 2
 ; CHECK-NOVSX-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: testSplat4Low:
 ; CHECK-P7:       # %bb.0: # %entry
 ; CHECK-P7-NEXT:    ld r3, 0(r3)
-; CHECK-P7-NEXT:    addi r4, r1, -16
 ; CHECK-P7-NEXT:    std r3, -16(r1)
-; CHECK-P7-NEXT:    lxvd2x vs0, 0, r4
+; CHECK-P7-NEXT:    addi r3, r1, -16
+; CHECK-P7-NEXT:    lxvd2x vs0, 0, r3
 ; CHECK-P7-NEXT:    xxswapd v2, vs0
 ; CHECK-P7-NEXT:    xxspltw v2, v2, 2
 ; CHECK-P7-NEXT:    blr
 ;
 ; P8-AIX-64-LABEL: testSplat4Low:
 ; P8-AIX-64:       # %bb.0: # %entry
 ; P8-AIX-64-NEXT:    lfdx f0, 0, r3
 ; P8-AIX-64-NEXT:    xxspltw v2, vs0, 1

 ; CHECK-NOVSX-NEXT:    std r3, -16(r1)
 ; CHECK-NOVSX-NEXT:    lvx v2, 0, r4
 ; CHECK-NOVSX-NEXT:    vspltw v2, v2, 3
 ; CHECK-NOVSX-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: testSplat4hi:
 ; CHECK-P7:       # %bb.0: # %entry
 ; CHECK-P7-NEXT:    ld r3, 0(r3)
-; CHECK-P7-NEXT:    addi r4, r1, -16
 ; CHECK-P7-NEXT:    std r3, -16(r1)
-; CHECK-P7-NEXT:    lxvd2x vs0, 0, r4
+; CHECK-P7-NEXT:    addi r3, r1, -16
+; CHECK-P7-NEXT:    lxvd2x vs0, 0, r3
 ; CHECK-P7-NEXT:    xxswapd v2, vs0
 ; CHECK-P7-NEXT:    xxspltw v2, v2, 3
 ; CHECK-P7-NEXT:    blr
 ;
 ; P8-AIX-64-LABEL: testSplat4hi:
 ; P8-AIX-64:       # %bb.0: # %entry
 ; P8-AIX-64-NEXT:    lfdx f0, 0, r3
 ; P8-AIX-64-NEXT:    xxspltw v2, vs0, 0

llvm/test/CodeGen/PowerPC/crbits.ll

 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 -ppc-gpr-icmps=none < %s | \
 ; RUN:     FileCheck %s --check-prefix=CHECK-P10
 
 ; Function Attrs: nounwind readnone
 define zeroext i1 @test1(float %v1, float %v2) #0 {
 ; CHECK-LABEL: test1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlxor 0, 0, 0
 ; CHECK-NEXT:    fcmpu 0, 1, 2
+; CHECK-NEXT:    xxlxor 0, 0, 0
 ; CHECK-NEXT:    li 3, 1
-; CHECK-NEXT:    fcmpu 5, 2, 2
-; CHECK-NEXT:    fcmpu 1, 2, 0
+; CHECK-NEXT:    fcmpu 1, 2, 2
 ; CHECK-NEXT:    crnor 20, 3, 0
-; CHECK-NEXT:    crnor 21, 23, 5
+; CHECK-NEXT:    fcmpu 0, 2, 0
+; CHECK-NEXT:    crnor 21, 7, 1
 ; CHECK-NEXT:    crnand 20, 20, 21
 ; CHECK-NEXT:    isel 3, 0, 3, 20
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: test1:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
-; CHECK-NO-ISEL-NEXT:    xxlxor 0, 0, 0
 ; CHECK-NO-ISEL-NEXT:    fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT:    xxlxor 0, 0, 0
 ; CHECK-NO-ISEL-NEXT:    li 3, 1
-; CHECK-NO-ISEL-NEXT:    fcmpu 5, 2, 2
-; CHECK-NO-ISEL-NEXT:    fcmpu 1, 2, 0
+; CHECK-NO-ISEL-NEXT:    fcmpu 1, 2, 2
 ; CHECK-NO-ISEL-NEXT:    crnor 20, 3, 0
-; CHECK-NO-ISEL-NEXT:    crnor 21, 23, 5
+; CHECK-NO-ISEL-NEXT:    fcmpu 0, 2, 0
+; CHECK-NO-ISEL-NEXT:    crnor 21, 7, 1
 ; CHECK-NO-ISEL-NEXT:    crnand 20, 20, 21
 ; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB0_1
 ; CHECK-NO-ISEL-NEXT:    blr
 ; CHECK-NO-ISEL-NEXT:  .LBB0_1: # %entry
 ; CHECK-NO-ISEL-NEXT:    li 3, 0
 ; CHECK-NO-ISEL-NEXT:    blr
 ;
 ; CHECK-P10-LABEL: test1:

 
 
 }
 
 ; Function Attrs: nounwind readnone
 define zeroext i1 @test2(float %v1, float %v2) #0 {
 ; CHECK-LABEL: test2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlxor 0, 0, 0
 ; CHECK-NEXT:    fcmpu 0, 1, 2
+; CHECK-NEXT:    xxlxor 0, 0, 0
 ; CHECK-NEXT:    li 3, 1
-; CHECK-NEXT:    fcmpu 5, 2, 2
-; CHECK-NEXT:    fcmpu 1, 2, 0
+; CHECK-NEXT:    fcmpu 1, 2, 2
 ; CHECK-NEXT:    crnor 20, 3, 0
-; CHECK-NEXT:    crnor 21, 23, 5
+; CHECK-NEXT:    fcmpu 0, 2, 0
+; CHECK-NEXT:    crnor 21, 7, 1
 ; CHECK-NEXT:    creqv 20, 20, 21
 ; CHECK-NEXT:    isel 3, 0, 3, 20
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: test2:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
-; CHECK-NO-ISEL-NEXT:    xxlxor 0, 0, 0
 ; CHECK-NO-ISEL-NEXT:    fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT:    xxlxor 0, 0, 0
 ; CHECK-NO-ISEL-NEXT:    li 3, 1
-; CHECK-NO-ISEL-NEXT:    fcmpu 5, 2, 2
-; CHECK-NO-ISEL-NEXT:    fcmpu 1, 2, 0
+; CHECK-NO-ISEL-NEXT:    fcmpu 1, 2, 2
 ; CHECK-NO-ISEL-NEXT:    crnor 20, 3, 0
-; CHECK-NO-ISEL-NEXT:    crnor 21, 23, 5
+; CHECK-NO-ISEL-NEXT:    fcmpu 0, 2, 0
+; CHECK-NO-ISEL-NEXT:    crnor 21, 7, 1
 ; CHECK-NO-ISEL-NEXT:    creqv 20, 20, 21
 ; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB1_1
 ; CHECK-NO-ISEL-NEXT:    blr
 ; CHECK-NO-ISEL-NEXT:  .LBB1_1: # %entry
 ; CHECK-NO-ISEL-NEXT:    li 3, 0
 ; CHECK-NO-ISEL-NEXT:    blr
 ;
 ; CHECK-P10-LABEL: test2:

 
 
 }
 
 ; Function Attrs: nounwind readnone
 define zeroext i1 @test3(float %v1, float %v2, i32 signext %x) #0 {
 ; CHECK-LABEL: test3:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fcmpu 0, 1, 2
 ; CHECK-NEXT:    xxlxor 0, 0, 0
-; CHECK-NEXT:    fcmpu 0, 2, 2
 ; CHECK-NEXT:    li 3, 1
-; CHECK-NEXT:    fcmpu 5, 1, 2
-; CHECK-NEXT:    fcmpu 1, 2, 0
-; CHECK-NEXT:    crnor 20, 23, 20
-; CHECK-NEXT:    crnor 21, 3, 5
+; CHECK-NEXT:    fcmpu 1, 2, 2
+; CHECK-NEXT:    crnor 20, 3, 0
+; CHECK-NEXT:    fcmpu 0, 2, 0
+; CHECK-NEXT:    crnor 21, 7, 1
 ; CHECK-NEXT:    cmpwi 5, -2
 ; CHECK-NEXT:    crandc 21, 21, 2
 ; CHECK-NEXT:    creqv 20, 20, 21
 ; CHECK-NEXT:    isel 3, 0, 3, 20
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: test3:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT:    fcmpu 0, 1, 2
 ; CHECK-NO-ISEL-NEXT:    xxlxor 0, 0, 0
-; CHECK-NO-ISEL-NEXT:    fcmpu 0, 2, 2
 ; CHECK-NO-ISEL-NEXT:    li 3, 1
-; CHECK-NO-ISEL-NEXT:    fcmpu 5, 1, 2
-; CHECK-NO-ISEL-NEXT:    fcmpu 1, 2, 0
-; CHECK-NO-ISEL-NEXT:    crnor 20, 23, 20
-; CHECK-NO-ISEL-NEXT:    crnor 21, 3, 5
+; CHECK-NO-ISEL-NEXT:    fcmpu 1, 2, 2
+; CHECK-NO-ISEL-NEXT:    crnor 20, 3, 0
+; CHECK-NO-ISEL-NEXT:    fcmpu 0, 2, 0
+; CHECK-NO-ISEL-NEXT:    crnor 21, 7, 1
 ; CHECK-NO-ISEL-NEXT:    cmpwi 5, -2
 ; CHECK-NO-ISEL-NEXT:    crandc 21, 21, 2
 ; CHECK-NO-ISEL-NEXT:    creqv 20, 20, 21
 ; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB2_1
 ; CHECK-NO-ISEL-NEXT:    blr
 ; CHECK-NO-ISEL-NEXT:  .LBB2_1: # %entry
 ; CHECK-NO-ISEL-NEXT:    li 3, 0
 ; CHECK-NO-ISEL-NEXT:    blr
entry:
   ret i1 %or9
 
 }
 
 ; Function Attrs: nounwind readnone
 define zeroext i1 @test5(i1 zeroext %v1, i1 zeroext %v2, i32 signext %v3) #0 {
 ; CHECK-LABEL: test5:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    li 6, -2
 ; CHECK-NEXT:    and 3, 3, 4
-; CHECK-NEXT:    xor 5, 5, 6
+; CHECK-NEXT:    li 4, -2
+; CHECK-NEXT:    xor 4, 5, 4
 ; CHECK-NEXT:    clrldi 3, 3, 63
-; CHECK-NEXT:    cntlzw 5, 5
-; CHECK-NEXT:    srwi 4, 5, 5
+; CHECK-NEXT:    cntlzw 4, 4
+; CHECK-NEXT:    srwi 4, 4, 5
 ; CHECK-NEXT:    xori 4, 4, 1
 ; CHECK-NEXT:    or 3, 3, 4
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: test5:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
-; CHECK-NO-ISEL-NEXT:    li 6, -2
 ; CHECK-NO-ISEL-NEXT:    and 3, 3, 4
-; CHECK-NO-ISEL-NEXT:    xor 5, 5, 6
+; CHECK-NO-ISEL-NEXT:    li 4, -2
+; CHECK-NO-ISEL-NEXT:    xor 4, 5, 4
 ; CHECK-NO-ISEL-NEXT:    clrldi 3, 3, 63
-; CHECK-NO-ISEL-NEXT:    cntlzw 5, 5
-; CHECK-NO-ISEL-NEXT:    srwi 4, 5, 5
+; CHECK-NO-ISEL-NEXT:    cntlzw 4, 4
+; CHECK-NO-ISEL-NEXT:    srwi 4, 4, 5
 ; CHECK-NO-ISEL-NEXT:    xori 4, 4, 1
 ; CHECK-NO-ISEL-NEXT:    or 3, 3, 4
 ; CHECK-NO-ISEL-NEXT:    blr
 ;
 ; CHECK-P10-LABEL: test5:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    and r3, r3, r4
 ; CHECK-P10-NEXT:    cmpwi cr1, r5, -2

 }
 
 ; Function Attrs: nounwind readnone
 define zeroext i1 @test6(i1 zeroext %v1, i1 zeroext %v2, i32 signext %v3) #0 {
 ; CHECK-LABEL: test6:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li 6, -2
 ; CHECK-NEXT:    clrldi 4, 4, 63
-; CHECK-NEXT:    xor 5, 5, 6
 ; CHECK-NEXT:    clrldi 3, 3, 63
+; CHECK-NEXT:    xor 5, 5, 6
 ; CHECK-NEXT:    cntlzw 5, 5
 ; CHECK-NEXT:    srwi 5, 5, 5
 ; CHECK-NEXT:    xori 5, 5, 1
 ; CHECK-NEXT:    or 4, 5, 4
 ; CHECK-NEXT:    and 3, 4, 3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: test6:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    li 6, -2
 ; CHECK-NO-ISEL-NEXT:    clrldi 4, 4, 63
-; CHECK-NO-ISEL-NEXT:    xor 5, 5, 6
 ; CHECK-NO-ISEL-NEXT:    clrldi 3, 3, 63
+; CHECK-NO-ISEL-NEXT:    xor 5, 5, 6
 ; CHECK-NO-ISEL-NEXT:    cntlzw 5, 5
 ; CHECK-NO-ISEL-NEXT:    srwi 5, 5, 5
 ; CHECK-NO-ISEL-NEXT:    xori 5, 5, 1
 ; CHECK-NO-ISEL-NEXT:    or 4, 5, 4
 ; CHECK-NO-ISEL-NEXT:    and 3, 4, 3
 ; CHECK-NO-ISEL-NEXT:    blr
 ;
 ; CHECK-P10-LABEL: test6:
entry:
   %cond = select i1 %v2, i32 %i1, i32 %i2
   ret i32 %cond
 
 }
 
 define signext i32 @exttest7(i32 signext %a) #0 {
 ; CHECK-LABEL: exttest7:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    li 4, 8
 ; CHECK-NEXT:    cmplwi 3, 5
-; CHECK-NEXT:    li 3, 7
-; CHECK-NEXT:    iseleq 3, 3, 4
+; CHECK-NEXT:    li 3, 8
+; CHECK-NEXT:    li 4, 7
+; CHECK-NEXT:    iseleq 3, 4, 3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: exttest7:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
-; CHECK-NO-ISEL-NEXT:    li 4, 8
 ; CHECK-NO-ISEL-NEXT:    cmplwi 3, 5
-; CHECK-NO-ISEL-NEXT:    li 3, 7
-; CHECK-NO-ISEL-NEXT:    bclr 12, 2, 0
-; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT:    ori 3, 4, 0
+; CHECK-NO-ISEL-NEXT:    li 3, 8
+; CHECK-NO-ISEL-NEXT:    li 4, 7
+; CHECK-NO-ISEL-NEXT:    bc 12, 2, .LBB7_1
+; CHECK-NO-ISEL-NEXT:    blr
+; CHECK-NO-ISEL-NEXT:  .LBB7_1: # %entry
+; CHECK-NO-ISEL-NEXT:    addi 3, 4, 0
 ; CHECK-NO-ISEL-NEXT:    blr
 ;
 ; CHECK-P10-LABEL: exttest7:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    cmplwi r3, 5
 ; CHECK-P10-NEXT:    li r3, 8
 ; CHECK-P10-NEXT:    li r4, 7
 ; CHECK-P10-NEXT:    iseleq r3, r4, r3

llvm/test/CodeGen/PowerPC/expand-foldable-isel.ll

 ; CHECK-GEN-ISEL-TRUE-NEXT:    .cfi_def_cfa_offset 64
 ; CHECK-GEN-ISEL-TRUE-NEXT:    .cfi_offset lr, 16
 ; CHECK-GEN-ISEL-TRUE-NEXT:    .cfi_offset r29, -24
 ; CHECK-GEN-ISEL-TRUE-NEXT:    .cfi_offset r30, -16
 ; CHECK-GEN-ISEL-TRUE-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; CHECK-GEN-ISEL-TRUE-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-GEN-ISEL-TRUE-NEXT:    stdu r1, -64(r1)
 ; CHECK-GEN-ISEL-TRUE-NEXT:    mr r30, r3
+; CHECK-GEN-ISEL-TRUE-NEXT:    std r0, 80(r1)
 ; CHECK-GEN-ISEL-TRUE-NEXT:    # implicit-def: $x3
 ; CHECK-GEN-ISEL-TRUE-NEXT:    # implicit-def: $r29
-; CHECK-GEN-ISEL-TRUE-NEXT:    std r0, 80(r1)
 ; CHECK-GEN-ISEL-TRUE-NEXT:    b .LBB0_2
 ; CHECK-GEN-ISEL-TRUE-NEXT:    .p2align 4
 ; CHECK-GEN-ISEL-TRUE-NEXT:  .LBB0_1: # %cond.false21.i156
 ; CHECK-GEN-ISEL-TRUE-NEXT:    #
 ; CHECK-GEN-ISEL-TRUE-NEXT:    addi r4, r29, 1
 ; CHECK-GEN-ISEL-TRUE-NEXT:    srawi r4, r4, 1
 ; CHECK-GEN-ISEL-TRUE-NEXT:    addze r29, r4
 ; CHECK-GEN-ISEL-TRUE-NEXT:  .LBB0_2: # %while.cond11

 ; CHECK-NEXT:    .cfi_def_cfa_offset 64
 ; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    .cfi_offset r29, -24
 ; CHECK-NEXT:    .cfi_offset r30, -16
 ; CHECK-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    stdu r1, -64(r1)
 ; CHECK-NEXT:    mr r30, r3
+; CHECK-NEXT:    std r0, 80(r1)
 ; CHECK-NEXT:    # implicit-def: $x3
 ; CHECK-NEXT:    # implicit-def: $r29
-; CHECK-NEXT:    std r0, 80(r1)
 ; CHECK-NEXT:    b .LBB0_2
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB0_1: # %cond.false21.i156
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    addi r4, r29, 1
 ; CHECK-NEXT:    srawi r4, r4, 1
 ; CHECK-NEXT:    addze r29, r4
 ; CHECK-NEXT:  .LBB0_2: # %while.cond11

llvm/test/CodeGen/PowerPC/fma-mutate.ll

 ; CHECK-LABEL: foo3_fmf:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xstsqrtdp 0, 1
 ; CHECK-NEXT:    bc 12, 2, .LBB0_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    vspltisw 2, -3
 ; CHECK-NEXT:    xsrsqrtedp 0, 1
 ; CHECK-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
-; CHECK-NEXT:    lfs 4, .LCPI0_0@toc@l(3)
-; CHECK-NEXT:    xvcvsxwdp 2, 34
-; CHECK-NEXT:    xsmuldp 3, 1, 0
-; CHECK-NEXT:    fmr 5, 2
-; CHECK-NEXT:    xsmaddadp 5, 3, 0
+; CHECK-NEXT:    xvcvsxwdp 3, 34
+; CHECK-NEXT:    xsmuldp 2, 1, 0
+; CHECK-NEXT:    fmr 4, 3
+; CHECK-NEXT:    xsmaddadp 4, 2, 0
+; CHECK-NEXT:    lfs 2, .LCPI0_0@toc@l(3)
+; CHECK-NEXT:    xsmuldp 0, 0, 2
 ; CHECK-NEXT:    xsmuldp 0, 0, 4
-; CHECK-NEXT:    xsmuldp 0, 0, 5
 ; CHECK-NEXT:    xsmuldp 1, 1, 0
-; CHECK-NEXT:    xsmaddadp 2, 1, 0
-; CHECK-NEXT:    xsmuldp 0, 1, 4
-; CHECK-NEXT:    xsmuldp 1, 0, 2
+; CHECK-NEXT:    xsmaddadp 3, 1, 0
+; CHECK-NEXT:    xsmuldp 0, 1, 2
+; CHECK-NEXT:    xsmuldp 1, 0, 3
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB0_2:
 ; CHECK-NEXT:    xssqrtdp 1, 1
 ; CHECK-NEXT:    blr
   %r = call contract reassoc afn ninf double @llvm.sqrt.f64(double %a)
   ret double %r
 }
 

llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll

 ; PPC64-P8-NEXT:    mffprd 5, 1
 ; PPC64-P8-NEXT:    rldic 6, 3, 63, 0
 ; PPC64-P8-NEXT:    xor 4, 4, 6
 ; PPC64-P8-NEXT:    xor 3, 5, 6
 ; PPC64-P8-NEXT:    blr
 ;
 ; PPC64-LABEL: test_neg:
 ; PPC64:       # %bb.0: # %entry
-; PPC64-NEXT:    stfd 2, -8(1)
-; PPC64-NEXT:    stfd 1, -16(1)
 ; PPC64-NEXT:    li 3, 1
+; PPC64-NEXT:    stfd 2, -8(1)
 ; PPC64-NEXT:    ld 4, -8(1)
+; PPC64-NEXT:    stfd 1, -16(1)
 ; PPC64-NEXT:    ld 5, -16(1)
 ; PPC64-NEXT:    rldic 6, 3, 63, 0
 ; PPC64-NEXT:    xor 3, 5, 6
 ; PPC64-NEXT:    xor 4, 4, 6
 ; PPC64-NEXT:    blr
 ;
 ; PPC32-LABEL: test_neg:
 ; PPC32:       # %bb.0: # %entry

 ; PPC64-P8-NEXT:    rldic 4, 5, 52, 0
 ; PPC64-P8-NEXT:    or 3, 6, 3
 ; PPC64-P8-NEXT:    xor 4, 6, 4
 ; PPC64-P8-NEXT:    blr
 ;
 ; PPC64-LABEL: test_copysign_const:
 ; PPC64:       # %bb.0: # %entry
 ; PPC64-NEXT:    stfd 1, -8(1)
-; PPC64-NEXT:    li 4, 16399
 ; PPC64-NEXT:    li 5, 3019
 ; PPC64-NEXT:    ld 3, -8(1)
-; PPC64-NEXT:    rldicr 6, 3, 0, 0
-; PPC64-NEXT:    rldic 3, 4, 48, 1
-; PPC64-NEXT:    rldic 4, 5, 52, 0
-; PPC64-NEXT:    or 3, 6, 3
-; PPC64-NEXT:    xor 4, 6, 4
+; PPC64-NEXT:    rldic 5, 5, 52, 0
+; PPC64-NEXT:    rldicr 4, 3, 0, 0
+; PPC64-NEXT:    li 3, 16399
+; PPC64-NEXT:    rldic 3, 3, 48, 1
+; PPC64-NEXT:    or 3, 4, 3
+; PPC64-NEXT:    xor 4, 4, 5
 ; PPC64-NEXT:    blr
 ;
 ; PPC32-LABEL: test_copysign_const:
 ; PPC32:       # %bb.0: # %entry
 ; PPC32-NEXT:    stwu 1, -32(1)
 ; PPC32-NEXT:    stfd 1, 24(1)
 ; PPC32-NEXT:    li 6, 0
 ; PPC32-NEXT:    lwz 3, 24(1)

llvm/test/CodeGen/PowerPC/fpscr-intrinsics.ll

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mtfprwz 0, 3
 ; CHECK-NEXT:    xscvuxddp 0, 0
 ; CHECK-NEXT:    mtfsf 7, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-AIX64-LABEL: callmtfsf:
 ; CHECK-AIX64:       # %bb.0: # %entry
-; CHECK-AIX64-NEXT:    addi 4, 1, -4
 ; CHECK-AIX64-NEXT:    stw 3, -4(1)
-; CHECK-AIX64-NEXT:    lfiwzx 0, 0, 4
+; CHECK-AIX64-NEXT:    addi 3, 1, -4
+; CHECK-AIX64-NEXT:    lfiwzx 0, 0, 3
 ; CHECK-AIX64-NEXT:    xscvuxddp 0, 0
 ; CHECK-AIX64-NEXT:    mtfsf 7, 0
 ; CHECK-AIX64-NEXT:    blr
 ;
 ; CHECK-AIX32-LABEL: callmtfsf:
 ; CHECK-AIX32:       # %bb.0: # %entry
 ; CHECK-AIX32-NEXT:    addi 4, 1, -4
 ; CHECK-AIX32-NEXT:    stw 3, -4(1)

llvm/test/CodeGen/PowerPC/load-and-splat.ll

 ; P8-AIX32-NEXT:    lxvw4x v3, 0, r4
 ; P8-AIX32-NEXT:    lxvw4x v4, 0, r5
 ; P8-AIX32-NEXT:    vperm v2, v4, v3, v2
 ; P8-AIX32-NEXT:    stxvw4x v2, 0, r3
 ; P8-AIX32-NEXT:    blr
 ;
 ; P7-AIX32-LABEL: test4:
 ; P7-AIX32:       # %bb.0: # %entry
-; P7-AIX32-NEXT:    lwz r5, L..C0(r2) # %const.0
-; P7-AIX32-NEXT:    lwz r6, 24(r4)
+; P7-AIX32-NEXT:    lwz r5, 24(r4)
 ; P7-AIX32-NEXT:    lwz r4, 28(r4)
 ; P7-AIX32-NEXT:    stw r4, -16(r1)
-; P7-AIX32-NEXT:    stw r6, -32(r1)
-; P7-AIX32-NEXT:    lxvw4x v2, 0, r5
+; P7-AIX32-NEXT:    lwz r4, L..C0(r2) # %const.0
+; P7-AIX32-NEXT:    stw r5, -32(r1)
+; P7-AIX32-NEXT:    lxvw4x v2, 0, r4
 ; P7-AIX32-NEXT:    addi r4, r1, -16
-; P7-AIX32-NEXT:    addi r5, r1, -32
 ; P7-AIX32-NEXT:    lxvw4x v3, 0, r4
-; P7-AIX32-NEXT:    lxvw4x v4, 0, r5
+; P7-AIX32-NEXT:    addi r4, r1, -32
+; P7-AIX32-NEXT:    lxvw4x v4, 0, r4
 ; P7-AIX32-NEXT:    vperm v2, v4, v3, v2
 ; P7-AIX32-NEXT:    stxvw4x v2, 0, r3
 ; P7-AIX32-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds i64, ptr %a, i64 3
   %0 = load i64, ptr %arrayidx, align 8
   %splat.splatinsert.i = insertelement <2 x i64> undef, i64 %0, i32 0
   %splat.splat.i = shufflevector <2 x i64> %splat.splatinsert.i, <2 x i64> undef, <2 x i32> zeroinitializer

 ; P8-AIX32-NEXT:    lxvw4x v4, 0, r5
 ; P8-AIX32-NEXT:    vperm v2, v4, v3, v2
 ; P8-AIX32-NEXT:    stxvw4x v2, 0, r3
 ; P8-AIX32-NEXT:    blr
 ;
 ; P7-AIX32-LABEL: test5:
 ; P7-AIX32:       # %bb.0: # %entry
 ; P7-AIX32-NEXT:    lwz r4, 0(r4)
-; P7-AIX32-NEXT:    lwz r5, L..C1(r2) # %const.0
-; P7-AIX32-NEXT:    srawi r6, r4, 31
+; P7-AIX32-NEXT:    srawi r5, r4, 31
 ; P7-AIX32-NEXT:    stw r4, -16(r1)
+; P7-AIX32-NEXT:    lwz r4, L..C1(r2) # %const.0
+; P7-AIX32-NEXT:    stw r5, -32(r1)
+; P7-AIX32-NEXT:    lxvw4x v2, 0, r4
 ; P7-AIX32-NEXT:    addi r4, r1, -16
-; P7-AIX32-NEXT:    stw r6, -32(r1)
-; P7-AIX32-NEXT:    lxvw4x v2, 0, r5
-; P7-AIX32-NEXT:    addi r5, r1, -32
 ; P7-AIX32-NEXT:    lxvw4x v3, 0, r4
-; P7-AIX32-NEXT:    lxvw4x v4, 0, r5
+; P7-AIX32-NEXT:    addi r4, r1, -32
+; P7-AIX32-NEXT:    lxvw4x v4, 0, r4
 ; P7-AIX32-NEXT:    vperm v2, v4, v3, v2
 ; P7-AIX32-NEXT:    stxvw4x v2, 0, r3
 ; P7-AIX32-NEXT:    blr
 entry:
   %0 = load i32, ptr %in, align 4
   %conv = sext i32 %0 to i64
   %splat.splatinsert.i = insertelement <2 x i64> poison, i64 %conv, i32 0
   %splat.splat.i = shufflevector <2 x i64> %splat.splatinsert.i, <2 x i64> poison, <2 x i32> zeroinitializer

 ; P8-AIX32-NEXT:    lxvw4x v3, 0, r4
 ; P8-AIX32-NEXT:    lxvw4x v4, 0, r5
 ; P8-AIX32-NEXT:    vperm v2, v3, v4, v2
 ; P8-AIX32-NEXT:    stxvw4x v2, 0, r3
 ; P8-AIX32-NEXT:    blr
 ;
 ; P7-AIX32-LABEL: test6:
 ; P7-AIX32:       # %bb.0: # %entry
-; P7-AIX32-NEXT:    lwz r5, L..C2(r2) # %const.0
 ; P7-AIX32-NEXT:    lwz r4, 0(r4)
-; P7-AIX32-NEXT:    li r6, 0
-; P7-AIX32-NEXT:    stw r6, -32(r1)
+; P7-AIX32-NEXT:    li r5, 0
+; P7-AIX32-NEXT:    stw r5, -32(r1)
 ; P7-AIX32-NEXT:    stw r4, -16(r1)
+; P7-AIX32-NEXT:    lwz r4, L..C2(r2) # %const.0
+; P7-AIX32-NEXT:    lxvw4x v2, 0, r4
 ; P7-AIX32-NEXT:    addi r4, r1, -32
-; P7-AIX32-NEXT:    lxvw4x v2, 0, r5
-; P7-AIX32-NEXT:    addi r5, r1, -16
 ; P7-AIX32-NEXT:    lxvw4x v3, 0, r4
-; P7-AIX32-NEXT:    lxvw4x v4, 0, r5
+; P7-AIX32-NEXT:    addi r4, r1, -16
+; P7-AIX32-NEXT:    lxvw4x v4, 0, r4
 ; P7-AIX32-NEXT:    vperm v2, v3, v4, v2
 ; P7-AIX32-NEXT:    stxvw4x v2, 0, r3
 ; P7-AIX32-NEXT:    blr
 entry:
   %0 = load i32, ptr %in, align 4
   %conv = zext i32 %0 to i64
   %splat.splatinsert.i = insertelement <2 x i64> poison, i64 %conv, i32 0
   %splat.splat.i = shufflevector <2 x i64> %splat.splatinsert.i, <2 x i64> poison, <2 x i32> zeroinitializer

 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    lfdx f0, 0, r3
 ; P8-NEXT:    xxspltw v2, vs0, 0
 ; P8-NEXT:    blr
 ;
 ; P7-LABEL: adjusted_lxvwsx:
 ; P7:       # %bb.0: # %entry
 ; P7-NEXT:    ld r3, 0(r3)
-; P7-NEXT:    addi r4, r1, -16
 ; P7-NEXT:    std r3, -16(r1)
-; P7-NEXT:    lxvw4x vs0, 0, r4
+; P7-NEXT:    addi r3, r1, -16
+; P7-NEXT:    lxvw4x vs0, 0, r3
 ; P7-NEXT:    xxspltw v2, vs0, 1
 ; P7-NEXT:    blr
 ;
 ; P9-AIX32-LABEL: adjusted_lxvwsx:
 ; P9-AIX32:       # %bb.0: # %entry
 ; P9-AIX32-NEXT:    addi r3, r3, 4
 ; P9-AIX32-NEXT:    lxvwsx v2, 0, r3
 ; P9-AIX32-NEXT:    blr

 ; P8-AIX32-NEXT:    lxvw4x vs0, 0, r3
 ; P8-AIX32-NEXT:    lxvw4x vs1, 0, r4
 ; P8-AIX32-NEXT:    xxmrghw vs0, vs1, vs0
 ; P8-AIX32-NEXT:    xxmrghd v2, vs0, vs0
 ; P8-AIX32-NEXT:    blr
 ;
 ; P7-AIX32-LABEL: unadjusted_lxvdsx:
 ; P7-AIX32:       # %bb.0: # %entry
-; P7-AIX32-NEXT:    lwz r5, 4(r3)
-; P7-AIX32-NEXT:    addi r4, r1, -16
-; P7-AIX32-NEXT:    stw r5, -16(r1)
+; P7-AIX32-NEXT:    lwz r4, 4(r3)
+; P7-AIX32-NEXT:    stw r4, -16(r1)
 ; P7-AIX32-NEXT:    lwz r3, 0(r3)
 ; P7-AIX32-NEXT:    stw r3, -32(r1)
+; P7-AIX32-NEXT:    addi r3, r1, -16
+; P7-AIX32-NEXT:    lxvw4x vs0, 0, r3
 ; P7-AIX32-NEXT:    addi r3, r1, -32
-; P7-AIX32-NEXT:    lxvw4x vs0, 0, r4
 ; P7-AIX32-NEXT:    lxvw4x vs1, 0, r3
 ; P7-AIX32-NEXT:    xxmrghw vs0, vs1, vs0
 ; P7-AIX32-NEXT:    xxmrghd v2, vs0, vs0
 ; P7-AIX32-NEXT:    blr
   entry:
     %0 = load <8 x i8>, ptr %s, align 8
     %1 = shufflevector <8 x i8> %0, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
     ret <16 x i8> %1

 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    lhz r3, 6(r3)
 ; P8-NEXT:    mtvsrwz v2, r3
 ; P8-NEXT:    vsplth v2, v2, 3
 ; P8-NEXT:    blr
 ;
 ; P7-LABEL: test_unaligned_v8i16:
 ; P7:       # %bb.0: # %entry
-; P7-NEXT:    li r4, 1
 ; P7-NEXT:    addi r3, r3, 6
+; P7-NEXT:    li r4, 1
 ; P7-NEXT:    lvx v2, 0, r3
 ; P7-NEXT:    lvx v3, r4, r3
 ; P7-NEXT:    lvsl v4, 0, r3
 ; P7-NEXT:    vperm v2, v2, v3, v4
 ; P7-NEXT:    vsplth v2, v2, 0
 ; P7-NEXT:    blr
 ;
 ; P9-AIX32-LABEL: test_unaligned_v8i16:
 ; P9-AIX32:       # %bb.0: # %entry
 ; P9-AIX32-NEXT:    addi r3, r3, 6
 ; P9-AIX32-NEXT:    lxsihzx v2, 0, r3
 ; P9-AIX32-NEXT:    vsplth v2, v2, 3
 ; P9-AIX32-NEXT:    blr
 ;
 ; P8-AIX32-LABEL: test_unaligned_v8i16:
 ; P8-AIX32:       # %bb.0: # %entry
 ; P8-AIX32-NEXT:    lhz r3, 6(r3)
 ; P8-AIX32-NEXT:    mtvsrwz v2, r3
 ; P8-AIX32-NEXT:    vsplth v2, v2, 3
 ; P8-AIX32-NEXT:    blr
 ;
 ; P7-AIX32-LABEL: test_unaligned_v8i16:
 ; P7-AIX32:       # %bb.0: # %entry
-; P7-AIX32-NEXT:    li r4, 1
 ; P7-AIX32-NEXT:    addi r3, r3, 6
+; P7-AIX32-NEXT:    li r4, 1
 ; P7-AIX32-NEXT:    lvx v2, 0, r3
 ; P7-AIX32-NEXT:    lvx v3, r4, r3
 ; P7-AIX32-NEXT:    lvsl v4, 0, r3
 ; P7-AIX32-NEXT:    vperm v2, v2, v3, v4
 ; P7-AIX32-NEXT:    vsplth v2, v2, 0
 ; P7-AIX32-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i16, ptr %Ptr, i64 3

 ; P8-NEXT:    stfd f1, 0(r5)
 ; P8-NEXT:    blr
 ;
 ; P7-LABEL: test_v2f64_multiple_use:
 ; P7:       # %bb.0: # %entry
 ; P7-NEXT:    lfs f0, 0(r3)
 ; P7-NEXT:    lfd f1, 0(r4)
 ; P7-NEXT:    xsadddp f1, f1, f0
-; P7-NEXT:    xxspltd v2, vs0, 0
 ; P7-NEXT:    stfd f1, 0(r4)
 ; P7-NEXT:    lfd f1, 0(r5)
-; P7-NEXT:    xsadddp f1, f1, f0
-; P7-NEXT:    stfd f1, 0(r5)
+; P7-NEXT:    xxspltd v2, vs0, 0
+; P7-NEXT:    xsadddp f0, f1, f0
+; P7-NEXT:    stfd f0, 0(r5)
 ; P7-NEXT:    blr
 ;
 ; P9-AIX32-LABEL: test_v2f64_multiple_use:
 ; P9-AIX32:       # %bb.0: # %entry
 ; P9-AIX32-NEXT:    lfs f0, 0(r3)
 ; P9-AIX32-NEXT:    xxmrghd v2, vs0, vs0
 ; P9-AIX32-NEXT:    lfd f1, 0(r4)
 ; P9-AIX32-NEXT:    xsadddp f1, f1, f0

 ; P8-AIX32-NEXT:    stfd f1, 0(r5)
 ; P8-AIX32-NEXT:    blr
 ;
 ; P7-AIX32-LABEL: test_v2f64_multiple_use:
 ; P7-AIX32:       # %bb.0: # %entry
 ; P7-AIX32-NEXT:    lfs f0, 0(r3)
 ; P7-AIX32-NEXT:    lfd f1, 0(r4)
 ; P7-AIX32-NEXT:    xsadddp f1, f1, f0
-; P7-AIX32-NEXT:    xxmrghd v2, vs0, vs0
 ; P7-AIX32-NEXT:    stfd f1, 0(r4)
 ; P7-AIX32-NEXT:    lfd f1, 0(r5)
-; P7-AIX32-NEXT:    xsadddp f1, f1, f0
-; P7-AIX32-NEXT:    stfd f1, 0(r5)
+; P7-AIX32-NEXT:    xxmrghd v2, vs0, vs0
+; P7-AIX32-NEXT:    xsadddp f0, f1, f0
+; P7-AIX32-NEXT:    stfd f0, 0(r5)
 ; P7-AIX32-NEXT:    blr
 entry:
   %0 = load float, ptr %a, align 4
   %conv = fpext float %0 to double
   %1 = load double, ptr %b, align 8
   %add = fadd double %1, %conv
   store double %add, ptr %b, align 8
   %2 = load double, ptr %c, align 8

llvm/test/CodeGen/PowerPC/ppc-partword-atomic.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mcpu=pwr7 %s -o - | FileCheck %s --check-prefix=PWR7
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mcpu=pwr9 %s -o - | FileCheck %s --check-prefix=PWR9
 
 @value8 = dso_local global { i8 } zeroinitializer, align 1
 @value16 = dso_local global { i16 } zeroinitializer, align 2
 @global_int = dso_local local_unnamed_addr global i32 0, align 4
 
 define dso_local zeroext i32 @testI8(i8 zeroext %val) local_unnamed_addr #0 {
 ; PWR7-LABEL: testI8:
 ; PWR7:       # %bb.0: # %entry
 ; PWR7-NEXT:    addis 4, 2, value8@toc@ha
-; PWR7-NEXT:    li 6, 255
 ; PWR7-NEXT:    sync
 ; PWR7-NEXT:    addi 5, 4, value8@toc@l
 ; PWR7-NEXT:    rlwinm 4, 5, 3, 27, 28
 ; PWR7-NEXT:    rldicr 5, 5, 0, 61
 ; PWR7-NEXT:    xori 4, 4, 24
-; PWR7-NEXT:    slw 7, 3, 4
-; PWR7-NEXT:    slw 3, 6, 4
-; PWR7-NEXT:    and 6, 7, 3
+; PWR7-NEXT:    slw 6, 3, 4
+; PWR7-NEXT:    li 3, 255
+; PWR7-NEXT:    slw 3, 3, 4
+; PWR7-NEXT:    and 6, 6, 3
 ; PWR7-NEXT:  .LBB0_1: # %entry
 ; PWR7-NEXT:    #
 ; PWR7-NEXT:    lwarx 7, 0, 5
 ; PWR7-NEXT:    andc 8, 7, 3
 ; PWR7-NEXT:    or 8, 6, 8
 ; PWR7-NEXT:    stwcx. 8, 0, 5
 ; PWR7-NEXT:    bne 0, .LBB0_1
 ; PWR7-NEXT:  # %bb.2: # %entry
 ; PWR7-NEXT:    srw 3, 7, 4
-; PWR7-NEXT:    addis 5, 2, global_int@toc@ha
+; PWR7-NEXT:    addis 4, 2, global_int@toc@ha
 ; PWR7-NEXT:    lwsync
-; PWR7-NEXT:    clrlwi 4, 3, 24
+; PWR7-NEXT:    clrlwi 3, 3, 24
+; PWR7-NEXT:    stw 3, global_int@toc@l(4)
 ; PWR7-NEXT:    li 3, 55
-; PWR7-NEXT:    stw 4, global_int@toc@l(5)
 ; PWR7-NEXT:    blr
 ;
 ; PWR9-LABEL: testI8:
 ; PWR9:       # %bb.0: # %entry
 ; PWR9-NEXT:    addis 4, 2, value8@toc@ha
 ; PWR9-NEXT:    sync
 ; PWR9-NEXT:    addi 5, 4, value8@toc@l
 ; PWR9-NEXT:  .LBB0_1: # %entry
entry:
   store i32 %conv, ptr @global_int, align 4
   ret i32 55
 }
 
 define dso_local zeroext i32 @testI16(i16 zeroext %val) local_unnamed_addr #0 {
 ; PWR7-LABEL: testI16:
 ; PWR7:       # %bb.0: # %entry
 ; PWR7-NEXT:    addis 4, 2, value16@toc@ha
-; PWR7-NEXT:    li 6, 0
 ; PWR7-NEXT:    sync
 ; PWR7-NEXT:    addi 5, 4, value16@toc@l
-; PWR7-NEXT:    ori 6, 6, 65535
 ; PWR7-NEXT:    rlwinm 4, 5, 3, 27, 27
 ; PWR7-NEXT:    rldicr 5, 5, 0, 61
 ; PWR7-NEXT:    xori 4, 4, 16
-; PWR7-NEXT:    slw 7, 3, 4
-; PWR7-NEXT:    slw 3, 6, 4
-; PWR7-NEXT:    and 6, 7, 3
+; PWR7-NEXT:    slw 6, 3, 4
+; PWR7-NEXT:    li 3, 0
+; PWR7-NEXT:    ori 3, 3, 65535
+; PWR7-NEXT:    slw 3, 3, 4
+; PWR7-NEXT:    and 6, 6, 3
 ; PWR7-NEXT:  .LBB1_1: # %entry
 ; PWR7-NEXT:    #
 ; PWR7-NEXT:    lwarx 7, 0, 5
 ; PWR7-NEXT:    andc 8, 7, 3
 ; PWR7-NEXT:    or 8, 6, 8
 ; PWR7-NEXT:    stwcx. 8, 0, 5
 ; PWR7-NEXT:    bne 0, .LBB1_1
 ; PWR7-NEXT:  # %bb.2: # %entry
 ; PWR7-NEXT:    srw 3, 7, 4
-; PWR7-NEXT:    addis 5, 2, global_int@toc@ha
+; PWR7-NEXT:    addis 4, 2, global_int@toc@ha
 ; PWR7-NEXT:    lwsync
-; PWR7-NEXT:    clrlwi 4, 3, 16
+; PWR7-NEXT:    clrlwi 3, 3, 16
+; PWR7-NEXT:    stw 3, global_int@toc@l(4)
 ; PWR7-NEXT:    li 3, 55
-; PWR7-NEXT:    stw 4, global_int@toc@l(5)
 ; PWR7-NEXT:    blr
 ;
 ; PWR9-LABEL: testI16:
 ; PWR9:       # %bb.0: # %entry
 ; PWR9-NEXT:    addis 4, 2, value16@toc@ha
 ; PWR9-NEXT:    sync
 ; PWR9-NEXT:    addi 5, 4, value16@toc@l
 ; PWR9-NEXT:  .LBB1_1: # %entry

llvm/test/CodeGen/PowerPC/ppc32-selectcc-i64.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc -mcpu=pwr7 < %s | FileCheck %s
 
 ; This piece of IR is expanded from memcmp.
 define i1 @cmp(i8* %a, i8* %b) {
 ; CHECK-LABEL: cmp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz 5, 4(3)
 ; CHECK-NEXT:    lwz 7, 0(3)
-; CHECK-NEXT:    lwz 6, 4(4)
 ; CHECK-NEXT:    lwz 8, 0(4)
+; CHECK-NEXT:    lwz 6, 4(4)
 ; CHECK-NEXT:    xor 9, 7, 8
 ; CHECK-NEXT:    xor 10, 5, 6
 ; CHECK-NEXT:    or. 9, 10, 9
 ; CHECK-NEXT:    bne 0, .LBB0_2
 ; CHECK-NEXT:  # %bb.1: # %loadbb1
 ; CHECK-NEXT:    lbz 3, 8(3)
 ; CHECK-NEXT:    lbz 4, 8(4)
 ; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    srwi 3, 3, 31
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB0_2: # %res_block
 ; CHECK-NEXT:    cmplw 7, 8
-; CHECK-NEXT:    cmplw 1, 5, 6
 ; CHECK-NEXT:    li 3, 1
 ; CHECK-NEXT:    li 4, -1
+; CHECK-NEXT:    cmplw 1, 5, 6
 ; CHECK-NEXT:    crandc 20, 0, 2
 ; CHECK-NEXT:    crand 21, 2, 4
 ; CHECK-NEXT:    cror 20, 21, 20
 ; CHECK-NEXT:    isel 3, 4, 3, 20
 ; CHECK-NEXT:    srwi 3, 3, 31
 ; CHECK-NEXT:    blr
 entry:
   br label %loadbb

llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll

 ; CHECK-PWR8-NEXT:    vsubudm v2, v2, v3
 ; CHECK-PWR8-NEXT:    vsubudm v3, v4, v2
 ; CHECK-PWR8-NEXT:    vmaxsd v2, v2, v3
 ; CHECK-PWR8-NEXT:    blr
 ;
 ; CHECK-PWR7-LABEL: sub_absv_64:
 ; CHECK-PWR7:       # %bb.0: # %entry
 ; CHECK-PWR7-NEXT:    addi r3, r1, -48
-; CHECK-PWR7-NEXT:    addi r4, r1, -32
 ; CHECK-PWR7-NEXT:    stxvd2x v2, 0, r3
-; CHECK-PWR7-NEXT:    stxvd2x v3, 0, r4
-; CHECK-PWR7-NEXT:    ld r3, -40(r1)
-; CHECK-PWR7-NEXT:    ld r4, -24(r1)
-; CHECK-PWR7-NEXT:    ld r5, -48(r1)
-; CHECK-PWR7-NEXT:    ld r6, -32(r1)
+; CHECK-PWR7-NEXT:    addi r3, r1, -32
+; CHECK-PWR7-NEXT:    stxvd2x v3, 0, r3
+; CHECK-PWR7-NEXT:    ld r3, -48(r1)
+; CHECK-PWR7-NEXT:    ld r4, -32(r1)
+; CHECK-PWR7-NEXT:    ld r5, -24(r1)
 ; CHECK-PWR7-NEXT:    sub r3, r3, r4
-; CHECK-PWR7-NEXT:    sub r4, r5, r6
-; CHECK-PWR7-NEXT:    sradi r5, r3, 63
-; CHECK-PWR7-NEXT:    sradi r6, r4, 63
-; CHECK-PWR7-NEXT:    xor r3, r3, r5
-; CHECK-PWR7-NEXT:    xor r4, r4, r6
-; CHECK-PWR7-NEXT:    sub r3, r3, r5
-; CHECK-PWR7-NEXT:    sub r4, r4, r6
-; CHECK-PWR7-NEXT:    std r3, -8(r1)
+; CHECK-PWR7-NEXT:    ld r4, -40(r1)
+; CHECK-PWR7-NEXT:    sub r4, r4, r5
+; CHECK-PWR7-NEXT:    sradi r5, r4, 63
+; CHECK-PWR7-NEXT:    xor r4, r4, r5
+; CHECK-PWR7-NEXT:    sub r4, r4, r5
+; CHECK-PWR7-NEXT:    std r4, -8(r1)
+; CHECK-PWR7-NEXT:    sradi r4, r3, 63
+; CHECK-PWR7-NEXT:    xor r3, r3, r4
+; CHECK-PWR7-NEXT:    sub r3, r3, r4
+; CHECK-PWR7-NEXT:    std r3, -16(r1)
 ; CHECK-PWR7-NEXT:    addi r3, r1, -16
-; CHECK-PWR7-NEXT:    std r4, -16(r1)
 ; CHECK-PWR7-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-PWR7-NEXT:    blr
 entry:
   %0 = sub nsw <2 x i64> %a, %b
   %1 = icmp sgt <2 x i64> %0, <i64 -1, i64 -1>
   %2 = sub <2 x i64> zeroinitializer, %0
   %3 = select <2 x i1> %1, <2 x i64> %0, <2 x i64> %2
   ret <2 x i64> %3
 }
 
 ; The select pattern can only be detected for v4i32.
 define <4 x i32> @sub_absv_32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr {
 ; CHECK-PWR9-LABEL: sub_absv_32:
 ; CHECK-PWR9:       # %bb.0: # %entry
 ; CHECK-PWR9-NEXT:    xvnegsp v3, v3
 ; CHECK-PWR9-NEXT:    xvnegsp v2, v2
 ; CHECK-PWR9-NEXT:    vabsduw v2, v2, v3
 ; CHECK-PWR9-NEXT:    blr
 ;
-; CHECK-PWR78-LABEL: sub_absv_32:
-; CHECK-PWR78:       # %bb.0: # %entry
-; CHECK-PWR78-NEXT:    xxlxor v4, v4, v4
-; CHECK-PWR78-NEXT:    vsubuwm v2, v2, v3
-; CHECK-PWR78-NEXT:    vsubuwm v3, v4, v2
-; CHECK-PWR78-NEXT:    vmaxsw v2, v2, v3
-; CHECK-PWR78-NEXT:    blr
+; CHECK-PWR8-LABEL: sub_absv_32:
+; CHECK-PWR8:       # %bb.0: # %entry
+; CHECK-PWR8-NEXT:    xxlxor v4, v4, v4
+; CHECK-PWR8-NEXT:    vsubuwm v2, v2, v3
+; CHECK-PWR8-NEXT:    vsubuwm v3, v4, v2
+; CHECK-PWR8-NEXT:    vmaxsw v2, v2, v3
+; CHECK-PWR8-NEXT:    blr
+;
+; CHECK-PWR7-LABEL: sub_absv_32:
+; CHECK-PWR7:       # %bb.0: # %entry
+; CHECK-PWR7-NEXT:    vsubuwm v2, v2, v3
+; CHECK-PWR7-NEXT:    xxlxor v3, v3, v3
+; CHECK-PWR7-NEXT:    vsubuwm v3, v3, v2
+; CHECK-PWR7-NEXT:    vmaxsw v2, v2, v3
+; CHECK-PWR7-NEXT:    blr
 entry:
   %0 = sub nsw <4 x i32> %a, %b
   %1 = icmp sgt <4 x i32> %0, <i32 -1, i32 -1, i32 -1, i32 -1>
   %2 = sub <4 x i32> zeroinitializer, %0
   %3 = select <4 x i1> %1, <4 x i32> %0, <4 x i32> %2
   ret <4 x i32> %3
 }
 
 define <8 x i16> @sub_absv_16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr {
 ; CHECK-PWR9-LABEL: sub_absv_16:
 ; CHECK-PWR9:       # %bb.0: # %entry
 ; CHECK-PWR9-NEXT:    vsubuhm v2, v2, v3
 ; CHECK-PWR9-NEXT:    xxlxor v3, v3, v3
 ; CHECK-PWR9-NEXT:    vsubuhm v3, v3, v2
 ; CHECK-PWR9-NEXT:    vmaxsh v2, v2, v3
 ; CHECK-PWR9-NEXT:    blr
 ;
-; CHECK-PWR78-LABEL: sub_absv_16:
-; CHECK-PWR78:       # %bb.0: # %entry
-; CHECK-PWR78-NEXT:    xxlxor v4, v4, v4
-; CHECK-PWR78-NEXT:    vsubuhm v2, v2, v3
-; CHECK-PWR78-NEXT:    vsubuhm v3, v4, v2
-; CHECK-PWR78-NEXT:    vmaxsh v2, v2, v3
-; CHECK-PWR78-NEXT:    blr
+; CHECK-PWR8-LABEL: sub_absv_16:
+; CHECK-PWR8:       # %bb.0: # %entry
+; CHECK-PWR8-NEXT:    xxlxor v4, v4, v4
+; CHECK-PWR8-NEXT:    vsubuhm v2, v2, v3
+; CHECK-PWR8-NEXT:    vsubuhm v3, v4, v2
+; CHECK-PWR8-NEXT:    vmaxsh v2, v2, v3
+; CHECK-PWR8-NEXT:    blr
+;
+; CHECK-PWR7-LABEL: sub_absv_16:
+; CHECK-PWR7:       # %bb.0: # %entry
+; CHECK-PWR7-NEXT:    vsubuhm v2, v2, v3
+; CHECK-PWR7-NEXT:    xxlxor v3, v3, v3
+; CHECK-PWR7-NEXT:    vsubuhm v3, v3, v2
+; CHECK-PWR7-NEXT:    vmaxsh v2, v2, v3
+; CHECK-PWR7-NEXT:    blr
 entry:
   %0 = sub nsw <8 x i16> %a, %b
   %1 = icmp sgt <8 x i16> %0, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
   %2 = sub <8 x i16> zeroinitializer, %0
   %3 = select <8 x i1> %1, <8 x i16> %0, <8 x i16> %2
   ret <8 x i16> %3
 }
 
 define <16 x i8> @sub_absv_8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr {
 ; CHECK-PWR9-LABEL: sub_absv_8:
 ; CHECK-PWR9:       # %bb.0: # %entry
 ; CHECK-PWR9-NEXT:    vsububm v2, v2, v3
 ; CHECK-PWR9-NEXT:    xxlxor v3, v3, v3
 ; CHECK-PWR9-NEXT:    vsububm v3, v3, v2
 ; CHECK-PWR9-NEXT:    vmaxsb v2, v2, v3
 ; CHECK-PWR9-NEXT:    blr
 ;
-; CHECK-PWR78-LABEL: sub_absv_8:
-; CHECK-PWR78:       # %bb.0: # %entry
-; CHECK-PWR78-NEXT:    xxlxor v4, v4, v4
-; CHECK-PWR78-NEXT:    vsububm v2, v2, v3
-; CHECK-PWR78-NEXT:    vsububm v3, v4, v2
-; CHECK-PWR78-NEXT:    vmaxsb v2, v2, v3
-; CHECK-PWR78-NEXT:    blr
+; CHECK-PWR8-LABEL: sub_absv_8:
+; CHECK-PWR8:       # %bb.0: # %entry
+; CHECK-PWR8-NEXT:    xxlxor v4, v4, v4
+; CHECK-PWR8-NEXT:    vsububm v2, v2, v3
+; CHECK-PWR8-NEXT:    vsububm v3, v4, v2
+; CHECK-PWR8-NEXT:    vmaxsb v2, v2, v3
+; CHECK-PWR8-NEXT:    blr
+;
+; CHECK-PWR7-LABEL: sub_absv_8:
+; CHECK-PWR7:       # %bb.0: # %entry
+; CHECK-PWR7-NEXT:    vsububm v2, v2, v3
+; CHECK-PWR7-NEXT:    xxlxor v3, v3, v3
+; CHECK-PWR7-NEXT:    vsububm v3, v3, v2
+; CHECK-PWR7-NEXT:    vmaxsb v2, v2, v3
+; CHECK-PWR7-NEXT:    blr
 entry:
   %0 = sub nsw <16 x i8> %a, %b
   %1 = icmp sgt <16 x i8> %0, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
   %2 = sub <16 x i8> zeroinitializer, %0
   %3 = select <16 x i1> %1, <16 x i8> %0, <16 x i8> %2
   ret <16 x i8> %3
 }
 

 ; CHECK-PWR8-NEXT:    vsubuwm v4, v4, v2
 ; CHECK-PWR8-NEXT:    vmaxsw v3, v5, v3
 ; CHECK-PWR8-NEXT:    vmaxsw v2, v2, v4
 ; CHECK-PWR8-NEXT:    vpkuwum v2, v2, v3
 ; CHECK-PWR8-NEXT:    blr
 ;
 ; CHECK-PWR7-LABEL: sub_absv_16_ext:
 ; CHECK-PWR7:       # %bb.0: # %entry
+; CHECK-PWR7-NEXT:    vspltisw v4, 8
 ; CHECK-PWR7-NEXT:    vmrglh v5, v2, v2
 ; CHECK-PWR7-NEXT:    vmrghh v2, v2, v2
 ; CHECK-PWR7-NEXT:    vmrglh v0, v3, v3
 ; CHECK-PWR7-NEXT:    vmrghh v3, v3, v3
-; CHECK-PWR7-NEXT:    vspltisw v4, 8
 ; CHECK-PWR7-NEXT:    vadduwm v4, v4, v4
 ; CHECK-PWR7-NEXT:    vslw v5, v5, v4
 ; CHECK-PWR7-NEXT:    vslw v2, v2, v4
 ; CHECK-PWR7-NEXT:    vslw v0, v0, v4
 ; CHECK-PWR7-NEXT:    vslw v3, v3, v4
 ; CHECK-PWR7-NEXT:    vsraw v5, v5, v4
 ; CHECK-PWR7-NEXT:    vsraw v2, v2, v4
 ; CHECK-PWR7-NEXT:    vsraw v0, v0, v4
 ; CHECK-PWR7-NEXT:    vsraw v3, v3, v4
 ; CHECK-PWR7-NEXT:    xxlxor v4, v4, v4
-; CHECK-PWR7-NEXT:    vsubuwm v5, v5, v0
 ; CHECK-PWR7-NEXT:    vsubuwm v2, v2, v3
-; CHECK-PWR7-NEXT:    vsubuwm v3, v4, v5
+; CHECK-PWR7-NEXT:    vsubuwm v3, v5, v0
+; CHECK-PWR7-NEXT:    vsubuwm v5, v4, v3
 ; CHECK-PWR7-NEXT:    vsubuwm v4, v4, v2
-; CHECK-PWR7-NEXT:    vmaxsw v3, v5, v3
+; CHECK-PWR7-NEXT:    vmaxsw v3, v3, v5
 ; CHECK-PWR7-NEXT:    vmaxsw v2, v2, v4
 ; CHECK-PWR7-NEXT:    vpkuwum v2, v2, v3
 ; CHECK-PWR7-NEXT:    blr
 entry:
   %0 = sext <8 x i16> %a to <8 x i32>
   %1 = sext <8 x i16> %b to <8 x i32>
   %2 = sub nsw <8 x i32> %0, %1
   %3 = icmp sgt <8 x i32> %2, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>

 ; CHECK-PWR8-NEXT:    vmrglh v5, v1, v8
 ; CHECK-PWR8-NEXT:    xxmrglw vs0, v3, v2
 ; CHECK-PWR8-NEXT:    xxmrglw vs1, v5, v4
 ; CHECK-PWR8-NEXT:    xxmrgld v2, vs0, vs1
 ; CHECK-PWR8-NEXT:    blr
 ;
 ; CHECK-PWR7-LABEL: sub_absv_8_ext:
 ; CHECK-PWR7:       # %bb.0: # %entry
-; CHECK-PWR7-NEXT:    stdu r1, -416(r1)
-; CHECK-PWR7-NEXT:    .cfi_def_cfa_offset 416
-; CHECK-PWR7-NEXT:    .cfi_offset r23, -72
+; CHECK-PWR7-NEXT:    stdu r1, -400(r1)
+; CHECK-PWR7-NEXT:    .cfi_def_cfa_offset 400
 ; CHECK-PWR7-NEXT:    .cfi_offset r24, -64
 ; CHECK-PWR7-NEXT:    .cfi_offset r25, -56
 ; CHECK-PWR7-NEXT:    .cfi_offset r26, -48
 ; CHECK-PWR7-NEXT:    .cfi_offset r27, -40
 ; CHECK-PWR7-NEXT:    .cfi_offset r28, -32
 ; CHECK-PWR7-NEXT:    .cfi_offset r29, -24
 ; CHECK-PWR7-NEXT:    .cfi_offset r30, -16
 ; CHECK-PWR7-NEXT:    addi r3, r1, 304
-; CHECK-PWR7-NEXT:    std r23, 344(r1) # 8-byte Folded Spill
 ; CHECK-PWR7-NEXT:    addi r4, r1, 320
-; CHECK-PWR7-NEXT:    std r24, 352(r1) # 8-byte Folded Spill
-; CHECK-PWR7-NEXT:    std r25, 360(r1) # 8-byte Folded Spill
-; CHECK-PWR7-NEXT:    std r26, 368(r1) # 8-byte Folded Spill
-; CHECK-PWR7-NEXT:    std r27, 376(r1) # 8-byte Folded Spill
-; CHECK-PWR7-NEXT:    std r28, 384(r1) # 8-byte Folded Spill
-; CHECK-PWR7-NEXT:    std r29, 392(r1) # 8-byte Folded Spill
-; CHECK-PWR7-NEXT:    std r30, 400(r1) # 8-byte Folded Spill
+; CHECK-PWR7-NEXT:    std r24, 336(r1) # 8-byte Folded Spill
+; CHECK-PWR7-NEXT:    std r25, 344(r1) # 8-byte Folded Spill
+; CHECK-PWR7-NEXT:    std r26, 352(r1) # 8-byte Folded Spill
+; CHECK-PWR7-NEXT:    std r27, 360(r1) # 8-byte Folded Spill
+; CHECK-PWR7-NEXT:    std r28, 368(r1) # 8-byte Folded Spill
+; CHECK-PWR7-NEXT:    std r29, 376(r1) # 8-byte Folded Spill
+; CHECK-PWR7-NEXT:    std r30, 384(r1) # 8-byte Folded Spill
 ; CHECK-PWR7-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-PWR7-NEXT:    lbz r3, 304(r1)
 ; CHECK-PWR7-NEXT:    stxvw4x v3, 0, r4
+; CHECK-PWR7-NEXT:    lbz r4, 320(r1)
+; CHECK-PWR7-NEXT:    lbz r5, 305(r1)
+; CHECK-PWR7-NEXT:    lbz r6, 321(r1)
 ; CHECK-PWR7-NEXT:    lbz r9, 307(r1)
 ; CHECK-PWR7-NEXT:    lbz r10, 323(r1)
 ; CHECK-PWR7-NEXT:    lbz r11, 308(r1)
 ; CHECK-PWR7-NEXT:    lbz r12, 324(r1)
 ; CHECK-PWR7-NEXT:    lbz r0, 309(r1)
+; CHECK-PWR7-NEXT:    sub r3, r3, r4
+; CHECK-PWR7-NEXT:    lbz r4, 313(r1)
+; CHECK-PWR7-NEXT:    sub r5, r5, r6
+; CHECK-PWR7-NEXT:    lbz r6, 329(r1)
 ; CHECK-PWR7-NEXT:    lbz r30, 325(r1)
-; CHECK-PWR7-NEXT:    sub r9, r9, r10
+; CHECK-PWR7-NEXT:    lbz r27, 311(r1)
+; CHECK-PWR7-NEXT:    lbz r26, 327(r1)
 ; CHECK-PWR7-NEXT:    lbz r29, 310(r1)
 ; CHECK-PWR7-NEXT:    lbz r28, 326(r1)
+; CHECK-PWR7-NEXT:    lbz r7, 306(r1)
+; CHECK-PWR7-NEXT:    lbz r8, 322(r1)
+; CHECK-PWR7-NEXT:    sub r9, r9, r10
 ; CHECK-PWR7-NEXT:    sub r11, r11, r12
-; CHECK-PWR7-NEXT:    lbz r27, 311(r1)
-; CHECK-PWR7-NEXT:    lbz r26, 327(r1)
-; CHECK-PWR7-NEXT:    sub r0, r0, r30
+; CHECK-PWR7-NEXT:    sub r12, r0, r30
+; CHECK-PWR7-NEXT:    sub r30, r27, r26
 ; CHECK-PWR7-NEXT:    lbz r25, 312(r1)
 ; CHECK-PWR7-NEXT:    lbz r24, 328(r1)
-; CHECK-PWR7-NEXT:    sub r29, r29, r28
-; CHECK-PWR7-NEXT:    lbz r10, 315(r1)
-; CHECK-PWR7-NEXT:    lbz r12, 331(r1)
-; CHECK-PWR7-NEXT:    sub r27, r27, r26
-; CHECK-PWR7-NEXT:    lbz r30, 316(r1)
-; CHECK-PWR7-NEXT:    lbz r28, 332(r1)
-; CHECK-PWR7-NEXT:    sub r25, r25, r24
-; CHECK-PWR7-NEXT:    lbz r4, 320(r1)
-; CHECK-PWR7-NEXT:    lbz r5, 305(r1)
-; CHECK-PWR7-NEXT:    sub r10, r10, r12
-; CHECK-PWR7-NEXT:    lbz r6, 321(r1)
-; CHECK-PWR7-NEXT:    lbz r26, 317(r1)
-; CHECK-PWR7-NEXT:    sub r30, r30, r28
-; CHECK-PWR7-NEXT:    lbz r24, 333(r1)
-; CHECK-PWR7-NEXT:    lbz r12, 319(r1)
-; CHECK-PWR7-NEXT:    sub r3, r3, r4
-; CHECK-PWR7-NEXT:    lbz r28, 335(r1)
-; CHECK-PWR7-NEXT:    lbz r7, 306(r1)
-; CHECK-PWR7-NEXT:    sub r5, r5, r6
-; CHECK-PWR7-NEXT:    lbz r8, 322(r1)
-; CHECK-PWR7-NEXT:    sub r26, r26, r24
-; CHECK-PWR7-NEXT:    srawi r24, r5, 31
-; CHECK-PWR7-NEXT:    lbz r23, 313(r1)
-; CHECK-PWR7-NEXT:    sub r12, r12, r28
-; CHECK-PWR7-NEXT:    srawi r28, r3, 31
-; CHECK-PWR7-NEXT:    xor r5, r5, r24
-; CHECK-PWR7-NEXT:    lbz r4, 329(r1)
+; CHECK-PWR7-NEXT:    sub r0, r29, r28
+; CHECK-PWR7-NEXT:    sub r4, r4, r6
+; CHECK-PWR7-NEXT:    srawi r6, r3, 31
+; CHECK-PWR7-NEXT:    srawi r28, r5, 31
 ; CHECK-PWR7-NEXT:    sub r7, r7, r8
-; CHECK-PWR7-NEXT:    xor r3, r3, r28
-; CHECK-PWR7-NEXT:    lbz r6, 314(r1)
-; CHECK-PWR7-NEXT:    lbz r8, 330(r1)
-; CHECK-PWR7-NEXT:    sub r3, r3, r28
-; CHECK-PWR7-NEXT:    srawi r28, r7, 31
-; CHECK-PWR7-NEXT:    sub r5, r5, r24
-; CHECK-PWR7-NEXT:    srawi r24, r9, 31
-; CHECK-PWR7-NEXT:    xor r7, r7, r28
-; CHECK-PWR7-NEXT:    xor r9, r9, r24
-; CHECK-PWR7-NEXT:    sub r7, r7, r28
-; CHECK-PWR7-NEXT:    srawi r28, r11, 31
-; CHECK-PWR7-NEXT:    sub r9, r9, r24
-; CHECK-PWR7-NEXT:    srawi r24, r0, 31
-; CHECK-PWR7-NEXT:    xor r11, r11, r28
-; CHECK-PWR7-NEXT:    xor r0, r0, r24
-; CHECK-PWR7-NEXT:    sub r11, r11, r28
+; CHECK-PWR7-NEXT:    srawi r26, r9, 31
+; CHECK-PWR7-NEXT:    lbz r8, 314(r1)
+; CHECK-PWR7-NEXT:    lbz r10, 330(r1)
+; CHECK-PWR7-NEXT:    xor r5, r5, r28
+; CHECK-PWR7-NEXT:    xor r3, r3, r6
+; CHECK-PWR7-NEXT:    xor r9, r9, r26
+; CHECK-PWR7-NEXT:    sub r29, r25, r24
+; CHECK-PWR7-NEXT:    sub r8, r8, r10
+; CHECK-PWR7-NEXT:    srawi r10, r0, 31
+; CHECK-PWR7-NEXT:    sub r5, r5, r28
 ; CHECK-PWR7-NEXT:    srawi r28, r29, 31
-; CHECK-PWR7-NEXT:    sub r0, r0, r24
-; CHECK-PWR7-NEXT:    srawi r24, r27, 31
-; CHECK-PWR7-NEXT:    sub r4, r23, r4
+; CHECK-PWR7-NEXT:    sub r9, r9, r26
+; CHECK-PWR7-NEXT:    sub r3, r3, r6
+; CHECK-PWR7-NEXT:    srawi r6, r30, 31
+; CHECK-PWR7-NEXT:    lbz r26, 315(r1)
+; CHECK-PWR7-NEXT:    xor r0, r0, r10
 ; CHECK-PWR7-NEXT:    xor r29, r29, r28
-; CHECK-PWR7-NEXT:    lbz r23, 318(r1)
-; CHECK-PWR7-NEXT:    xor r27, r27, r24
-; CHECK-PWR7-NEXT:    sub r29, r29, r28
-; CHECK-PWR7-NEXT:    srawi r28, r25, 31
-; CHECK-PWR7-NEXT:    sub r27, r27, r24
-; CHECK-PWR7-NEXT:    srawi r24, r4, 31
-; CHECK-PWR7-NEXT:    sub r6, r6, r8
-; CHECK-PWR7-NEXT:    xor r25, r25, r28
-; CHECK-PWR7-NEXT:    lbz r8, 334(r1)
-; CHECK-PWR7-NEXT:    xor r4, r4, r24
-; CHECK-PWR7-NEXT:    sub r28, r25, r28
-; CHECK-PWR7-NEXT:    srawi r25, r6, 31
-; CHECK-PWR7-NEXT:    sub r4, r4, r24
-; CHECK-PWR7-NEXT:    srawi r24, r10, 31
-; CHECK-PWR7-NEXT:    xor r6, r6, r25
-; CHECK-PWR7-NEXT:    xor r10, r10, r24
-; CHECK-PWR7-NEXT:    sub r6, r6, r25
-; CHECK-PWR7-NEXT:    srawi r25, r30, 31
-; CHECK-PWR7-NEXT:    sub r10, r10, r24
-; CHECK-PWR7-NEXT:    srawi r24, r26, 31
-; CHECK-PWR7-NEXT:    sub r8, r23, r8
-; CHECK-PWR7-NEXT:    xor r30, r30, r25
-; CHECK-PWR7-NEXT:    ld r23, 344(r1) # 8-byte Folded Reload
-; CHECK-PWR7-NEXT:    xor r26, r26, r24
-; CHECK-PWR7-NEXT:    sub r30, r30, r25
-; CHECK-PWR7-NEXT:    srawi r25, r12, 31
-; CHECK-PWR7-NEXT:    sub r26, r26, r24
-; CHECK-PWR7-NEXT:    srawi r24, r8, 31
-; CHECK-PWR7-NEXT:    xor r12, r12, r25
-; CHECK-PWR7-NEXT:    xor r8, r8, r24
-; CHECK-PWR7-NEXT:    sub r12, r12, r25
-; CHECK-PWR7-NEXT:    addi r25, r1, 272
-; CHECK-PWR7-NEXT:    sub r8, r8, r24
-; CHECK-PWR7-NEXT:    stb r12, 288(r1)
-; CHECK-PWR7-NEXT:    addi r12, r1, 288
-; CHECK-PWR7-NEXT:    stb r8, 272(r1)
-; CHECK-PWR7-NEXT:    stb r26, 256(r1)
-; CHECK-PWR7-NEXT:    stb r30, 240(r1)
-; CHECK-PWR7-NEXT:    stb r10, 224(r1)
-; CHECK-PWR7-NEXT:    stb r6, 208(r1)
+; CHECK-PWR7-NEXT:    sub r10, r0, r10
+; CHECK-PWR7-NEXT:    srawi r27, r7, 31
+; CHECK-PWR7-NEXT:    sub r0, r29, r28
+; CHECK-PWR7-NEXT:    xor r30, r30, r6
+; CHECK-PWR7-NEXT:    srawi r25, r11, 31
+; CHECK-PWR7-NEXT:    lbz r28, 332(r1)
+; CHECK-PWR7-NEXT:    sub r6, r30, r6
+; CHECK-PWR7-NEXT:    lbz r30, 331(r1)
+; CHECK-PWR7-NEXT:    xor r7, r7, r27
+; CHECK-PWR7-NEXT:    xor r11, r11, r25
+; CHECK-PWR7-NEXT:    sub r7, r7, r27
+; CHECK-PWR7-NEXT:    srawi r27, r4, 31
+; CHECK-PWR7-NEXT:    sub r11, r11, r25
+; CHECK-PWR7-NEXT:    srawi r25, r8, 31
+; CHECK-PWR7-NEXT:    sub r30, r26, r30
+; CHECK-PWR7-NEXT:    xor r4, r4, r27
+; CHECK-PWR7-NEXT:    xor r8, r8, r25
+; CHECK-PWR7-NEXT:    sub r4, r4, r27
+; CHECK-PWR7-NEXT:    sub r8, r8, r25
+; CHECK-PWR7-NEXT:    lbz r27, 317(r1)
+; CHECK-PWR7-NEXT:    lbz r26, 333(r1)
+; CHECK-PWR7-NEXT:    lbz r25, 334(r1)
+; CHECK-PWR7-NEXT:    srawi r24, r12, 31
+; CHECK-PWR7-NEXT:    sub r27, r27, r26
+; CHECK-PWR7-NEXT:    srawi r29, r30, 31
+; CHECK-PWR7-NEXT:    xor r30, r30, r29
+; CHECK-PWR7-NEXT:    xor r12, r12, r24
+; CHECK-PWR7-NEXT:    sub r12, r12, r24
+; CHECK-PWR7-NEXT:    stb r3, 48(r1)
+; CHECK-PWR7-NEXT:    addi r3, r1, 288
+; CHECK-PWR7-NEXT:    stb r8, 208(r1)
 ; CHECK-PWR7-NEXT:    stb r4, 192(r1)
-; CHECK-PWR7-NEXT:    stb r28, 176(r1)
-; CHECK-PWR7-NEXT:    stb r27, 160(r1)
-; CHECK-PWR7-NEXT:    stb r29, 144(r1)
-; CHECK-PWR7-NEXT:    stb r0, 128(r1)
+; CHECK-PWR7-NEXT:    stb r0, 176(r1)
+; CHECK-PWR7-NEXT:    stb r6, 160(r1)
+; CHECK-PWR7-NEXT:    srawi r26, r27, 31
+; CHECK-PWR7-NEXT:    stb r10, 144(r1)
+; CHECK-PWR7-NEXT:    ld r24, 336(r1) # 8-byte Folded Reload
+; CHECK-PWR7-NEXT:    sub r30, r30, r29
+; CHECK-PWR7-NEXT:    lbz r29, 316(r1)
+; CHECK-PWR7-NEXT:    stb r12, 128(r1)
+; CHECK-PWR7-NEXT:    sub r29, r29, r28
+; CHECK-PWR7-NEXT:    xor r27, r27, r26
+; CHECK-PWR7-NEXT:    sub r27, r27, r26
+; CHECK-PWR7-NEXT:    lbz r26, 319(r1)
+; CHECK-PWR7-NEXT:    srawi r28, r29, 31
+; CHECK-PWR7-NEXT:    stb r27, 256(r1)
+; CHECK-PWR7-NEXT:    stb r30, 224(r1)
 ; CHECK-PWR7-NEXT:    stb r11, 112(r1)
 ; CHECK-PWR7-NEXT:    stb r9, 96(r1)
 ; CHECK-PWR7-NEXT:    stb r7, 80(r1)
 ; CHECK-PWR7-NEXT:    stb r5, 64(r1)
-; CHECK-PWR7-NEXT:    stb r3, 48(r1)
-; CHECK-PWR7-NEXT:    addi r8, r1, 256
-; CHECK-PWR7-NEXT:    addi r26, r1, 240
-; CHECK-PWR7-NEXT:    lxvw4x v2, 0, r12
-; CHECK-PWR7-NEXT:    lxvw4x v3, 0, r25
-; CHECK-PWR7-NEXT:    addi r10, r1, 224
-; CHECK-PWR7-NEXT:    addi r30, r1, 208
+; CHECK-PWR7-NEXT:    ld r30, 384(r1) # 8-byte Folded Reload
+; CHECK-PWR7-NEXT:    ld r27, 360(r1) # 8-byte Folded Reload
+; CHECK-PWR7-NEXT:    xor r29, r29, r28
+; CHECK-PWR7-NEXT:    sub r29, r29, r28
+; CHECK-PWR7-NEXT:    lbz r28, 318(r1)
+; CHECK-PWR7-NEXT:    stb r29, 240(r1)
+; CHECK-PWR7-NEXT:    ld r29, 376(r1) # 8-byte Folded Reload
+; CHECK-PWR7-NEXT:    sub r28, r28, r25
+; CHECK-PWR7-NEXT:    srawi r25, r28, 31
+; CHECK-PWR7-NEXT:    xor r28, r28, r25
+; CHECK-PWR7-NEXT:    sub r28, r28, r25
+; CHECK-PWR7-NEXT:    lbz r25, 335(r1)
+; CHECK-PWR7-NEXT:    stb r28, 272(r1)
+; CHECK-PWR7-NEXT:    ld r28, 368(r1) # 8-byte Folded Reload
+; CHECK-PWR7-NEXT:    sub r26, r26, r25
+; CHECK-PWR7-NEXT:    srawi r25, r26, 31
+; CHECK-PWR7-NEXT:    xor r26, r26, r25
+; CHECK-PWR7-NEXT:    sub r26, r26, r25
+; CHECK-PWR7-NEXT:    ld r25, 344(r1) # 8-byte Folded Reload
+; CHECK-PWR7-NEXT:    stb r26, 288(r1)
+; CHECK-PWR7-NEXT:    ld r26, 352(r1) # 8-byte Folded Reload
+; CHECK-PWR7-NEXT:    lxvw4x v2, 0, r3
+; CHECK-PWR7-NEXT:    addi r3, r1, 272
+; CHECK-PWR7-NEXT:    lxvw4x v3, 0, r3
+; CHECK-PWR7-NEXT:    addi r3, r1, 256
+; CHECK-PWR7-NEXT:    vmrghb v2, v3, v2
+; CHECK-PWR7-NEXT:    lxvw4x v3, 0, r3
+; CHECK-PWR7-NEXT:    addi r3, r1, 240
+; CHECK-PWR7-NEXT:    lxvw4x v4, 0, r3
+; CHECK-PWR7-NEXT:    addi r3, r1, 224
+; CHECK-PWR7-NEXT:    vmrghb v3, v4, v3
+; CHECK-PWR7-NEXT:    vmrghh v2, v3, v2
+; CHECK-PWR7-NEXT:    lxvw4x v4, 0, r3
+; CHECK-PWR7-NEXT:    addi r3, r1, 208
+; CHECK-PWR7-NEXT:    lxvw4x v5, 0, r3
 ; CHECK-PWR7-NEXT:    addi r3, r1, 192
-; CHECK-PWR7-NEXT:    addi r4, r1, 176
-; CHECK-PWR7-NEXT:    addi r5, r1, 160
-; CHECK-PWR7-NEXT:    addi r6, r1, 144
-; CHECK-PWR7-NEXT:    lxvw4x v4, 0, r8
-; CHECK-PWR7-NEXT:    lxvw4x v5, 0, r26
-; CHECK-PWR7-NEXT:    addi r7, r1, 128
-; CHECK-PWR7-NEXT:    addi r8, r1, 112
-; CHECK-PWR7-NEXT:    lxvw4x v0, 0, r10
-; CHECK-PWR7-NEXT:    lxvw4x v1, 0, r30
+; CHECK-PWR7-NEXT:    vmrghb v3, v5, v4
+; CHECK-PWR7-NEXT:    lxvw4x v4, 0, r3
+; CHECK-PWR7-NEXT:    addi r3, r1, 176
+; CHECK-PWR7-NEXT:    lxvw4x v5, 0, r3
+; CHECK-PWR7-NEXT:    addi r3, r1, 160
+; CHECK-PWR7-NEXT:    vmrghb v4, v5, v4
+; CHECK-PWR7-NEXT:    vmrghh v3, v4, v3
+; CHECK-PWR7-NEXT:    xxmrghw vs0, v3, v2
+; CHECK-PWR7-NEXT:    lxvw4x v2, 0, r3
+; CHECK-PWR7-NEXT:    addi r3, r1, 144
+; CHECK-PWR7-NEXT:    lxvw4x v3, 0, r3
+; CHECK-PWR7-NEXT:    addi r3, r1, 128
 ; CHECK-PWR7-NEXT:    vmrghb v2, v3, v2
-; CHECK-PWR7-NEXT:    addi r9, r1, 96
-; CHECK-PWR7-NEXT:    lxvw4x v6, 0, r3
-; CHECK-PWR7-NEXT:    lxvw4x v7, 0, r4
+; CHECK-PWR7-NEXT:    lxvw4x v3, 0, r3
+; CHECK-PWR7-NEXT:    addi r3, r1, 112
+; CHECK-PWR7-NEXT:    lxvw4x v4, 0, r3
+; CHECK-PWR7-NEXT:    addi r3, r1, 96
+; CHECK-PWR7-NEXT:    vmrghb v3, v4, v3
+; CHECK-PWR7-NEXT:    vmrghh v2, v3, v2
+; CHECK-PWR7-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-PWR7-NEXT:    addi r3, r1, 80
-; CHECK-PWR7-NEXT:    addi r4, r1, 64
-; CHECK-PWR7-NEXT:    lxvw4x v3, 0, r5
-; CHECK-PWR7-NEXT:    lxvw4x v8, 0, r6
-; CHECK-PWR7-NEXT:    addi r5, r1, 48
+; CHECK-PWR7-NEXT:    lxvw4x v4, 0, r3
+; CHECK-PWR7-NEXT:    addi r3, r1, 64
+; CHECK-PWR7-NEXT:    vmrghb v3, v4, v3
+; CHECK-PWR7-NEXT:    lxvw4x v4, 0, r3
+; CHECK-PWR7-NEXT:    addi r3, r1, 48
+; CHECK-PWR7-NEXT:    lxvw4x v5, 0, r3
 ; CHECK-PWR7-NEXT:    vmrghb v4, v5, v4
-; CHECK-PWR7-NEXT:    lxvw4x v5, 0, r7
-; CHECK-PWR7-NEXT:    lxvw4x v9, 0, r8
-; CHECK-PWR7-NEXT:    vmrghb v0, v1, v0
-; CHECK-PWR7-NEXT:    lxvw4x v1, 0, r9
-; CHECK-PWR7-NEXT:    lxvw4x v10, 0, r3
-; CHECK-PWR7-NEXT:    vmrghb v6, v7, v6
-; CHECK-PWR7-NEXT:    lxvw4x v7, 0, r4
-; CHECK-PWR7-NEXT:    vmrghb v3, v8, v3
-; CHECK-PWR7-NEXT:    lxvw4x v8, 0, r5
-; CHECK-PWR7-NEXT:    vmrghb v5, v9, v5
-; CHECK-PWR7-NEXT:    ld r30, 400(r1) # 8-byte Folded Reload
-; CHECK-PWR7-NEXT:    ld r29, 392(r1) # 8-byte Folded Reload
-; CHECK-PWR7-NEXT:    vmrghb v1, v10, v1
-; CHECK-PWR7-NEXT:    ld r28, 384(r1) # 8-byte Folded Reload
-; CHECK-PWR7-NEXT:    ld r27, 376(r1) # 8-byte Folded Reload
-; CHECK-PWR7-NEXT:    vmrghb v7, v8, v7
-; CHECK-PWR7-NEXT:    ld r26, 368(r1) # 8-byte Folded Reload
-; CHECK-PWR7-NEXT:    ld r25, 360(r1) # 8-byte Folded Reload
-; CHECK-PWR7-NEXT:    vmrghh v2, v4, v2
-; CHECK-PWR7-NEXT:    ld r24, 352(r1) # 8-byte Folded Reload
-; CHECK-PWR7-NEXT:    vmrghh v4, v6, v0
-; CHECK-PWR7-NEXT:    vmrghh v3, v5, v3
-; CHECK-PWR7-NEXT:    vmrghh v5, v7, v1
-; CHECK-PWR7-NEXT:    xxmrghw vs0, v4, v2
-; CHECK-PWR7-NEXT:    xxmrghw vs1, v5, v3
+; CHECK-PWR7-NEXT:    vmrghh v3, v4, v3
+; CHECK-PWR7-NEXT:    xxmrghw vs1, v3, v2
 ; CHECK-PWR7-NEXT:    xxmrghd v2, vs1, vs0
-; CHECK-PWR7-NEXT:    addi r1, r1, 416
+; CHECK-PWR7-NEXT:    addi r1, r1, 400
 ; CHECK-PWR7-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %a, i32 0
   %conv = zext i8 %vecext to i32
   %vecext1 = extractelement <16 x i8> %b, i32 0
   %conv2 = zext i8 %vecext1 to i32
   %sub = sub nsw i32 %conv, %conv2
   %ispos = icmp sgt i32 %sub, -1

 define <4 x i32> @sub_absv_vec_32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr {
 ; CHECK-PWR9-LABEL: sub_absv_vec_32:
 ; CHECK-PWR9:       # %bb.0: # %entry
 ; CHECK-PWR9-NEXT:    xvnegsp v3, v3
 ; CHECK-PWR9-NEXT:    xvnegsp v2, v2
 ; CHECK-PWR9-NEXT:    vabsduw v2, v2, v3
 ; CHECK-PWR9-NEXT:    blr
 ;
-; CHECK-PWR78-LABEL: sub_absv_vec_32:
-; CHECK-PWR78:       # %bb.0: # %entry
-; CHECK-PWR78-NEXT:    xxlxor v4, v4, v4
-; CHECK-PWR78-NEXT:    vsubuwm v2, v2, v3
-; CHECK-PWR78-NEXT:    vsubuwm v3, v4, v2
-; CHECK-PWR78-NEXT:    vmaxsw v2, v2, v3
-; CHECK-PWR78-NEXT:    blr
+; CHECK-PWR8-LABEL: sub_absv_vec_32:
+; CHECK-PWR8:       # %bb.0: # %entry
+; CHECK-PWR8-NEXT:    xxlxor v4, v4, v4
+; CHECK-PWR8-NEXT:    vsubuwm v2, v2, v3
+; CHECK-PWR8-NEXT:    vsubuwm v3, v4, v2
+; CHECK-PWR8-NEXT:    vmaxsw v2, v2, v3
+; CHECK-PWR8-NEXT:    blr
+;
+; CHECK-PWR7-LABEL: sub_absv_vec_32:
+; CHECK-PWR7:       # %bb.0: # %entry
+; CHECK-PWR7-NEXT:    vsubuwm v2, v2, v3
+; CHECK-PWR7-NEXT:    xxlxor v3, v3, v3
+; CHECK-PWR7-NEXT:    vsubuwm v3, v3, v2
+; CHECK-PWR7-NEXT:    vmaxsw v2, v2, v3
+; CHECK-PWR7-NEXT:    blr
 entry:
   %sub = sub nsw <4 x i32> %a, %b
   %sub.i = sub <4 x i32> zeroinitializer, %sub
   %0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %sub, <4 x i32> %sub.i)
   ret <4 x i32> %0
 }
 
 define <8 x i16> @sub_absv_vec_16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr {
 ; CHECK-PWR9-LABEL: sub_absv_vec_16:
 ; CHECK-PWR9:       # %bb.0: # %entry
 ; CHECK-PWR9-NEXT:    vsubuhm v2, v2, v3
 ; CHECK-PWR9-NEXT:    xxlxor v3, v3, v3
 ; CHECK-PWR9-NEXT:    vsubuhm v3, v3, v2
 ; CHECK-PWR9-NEXT:    vmaxsh v2, v2, v3
 ; CHECK-PWR9-NEXT:    blr
 ;
-; CHECK-PWR78-LABEL: sub_absv_vec_16:
-; CHECK-PWR78:       # %bb.0: # %entry
-; CHECK-PWR78-NEXT:    xxlxor v4, v4, v4
-; CHECK-PWR78-NEXT:    vsubuhm v2, v2, v3
-; CHECK-PWR78-NEXT:    vsubuhm v3, v4, v2
-; CHECK-PWR78-NEXT:    vmaxsh v2, v2, v3
-; CHECK-PWR78-NEXT:    blr
+; CHECK-PWR8-LABEL: sub_absv_vec_16:
+; CHECK-PWR8:       # %bb.0: # %entry
+; CHECK-PWR8-NEXT:    xxlxor v4, v4, v4
+; CHECK-PWR8-NEXT:    vsubuhm v2, v2, v3
+; CHECK-PWR8-NEXT:    vsubuhm v3, v4, v2
+; CHECK-PWR8-NEXT:    vmaxsh v2, v2, v3
+; CHECK-PWR8-NEXT:    blr
+;
+; CHECK-PWR7-LABEL: sub_absv_vec_16:
+; CHECK-PWR7:       # %bb.0: # %entry
+; CHECK-PWR7-NEXT:    vsubuhm v2, v2, v3
+; CHECK-PWR7-NEXT:    xxlxor v3, v3, v3
+; CHECK-PWR7-NEXT:    vsubuhm v3, v3, v2
+; CHECK-PWR7-NEXT:    vmaxsh v2, v2, v3
+; CHECK-PWR7-NEXT:    blr
 entry:
   %sub = sub nsw <8 x i16> %a, %b
   %sub.i = sub <8 x i16> zeroinitializer, %sub
   %0 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %sub, <8 x i16> %sub.i)
   ret <8 x i16> %0
 }
 
 define <16 x i8> @sub_absv_vec_8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr {
 ; CHECK-PWR9-LABEL: sub_absv_vec_8:
 ; CHECK-PWR9:       # %bb.0: # %entry
 ; CHECK-PWR9-NEXT:    vsububm v2, v2, v3
 ; CHECK-PWR9-NEXT:    xxlxor v3, v3, v3
 ; CHECK-PWR9-NEXT:    vsububm v3, v3, v2
 ; CHECK-PWR9-NEXT:    vmaxsb v2, v2, v3
 ; CHECK-PWR9-NEXT:    blr
 ;
-; CHECK-PWR78-LABEL: sub_absv_vec_8:
-; CHECK-PWR78:       # %bb.0: # %entry
-; CHECK-PWR78-NEXT:    xxlxor v4, v4, v4
-; CHECK-PWR78-NEXT:    vsububm v2, v2, v3
-; CHECK-PWR78-NEXT:    vsububm v3, v4, v2
-; CHECK-PWR78-NEXT:    vmaxsb v2, v2, v3
-; CHECK-PWR78-NEXT:    blr
+; CHECK-PWR8-LABEL: sub_absv_vec_8:
+; CHECK-PWR8:       # %bb.0: # %entry
+; CHECK-PWR8-NEXT:    xxlxor v4, v4, v4
+; CHECK-PWR8-NEXT:    vsububm v2, v2, v3
+; CHECK-PWR8-NEXT:    vsububm v3, v4, v2
+; CHECK-PWR8-NEXT:    vmaxsb v2, v2, v3
+; CHECK-PWR8-NEXT:    blr
+;
+; CHECK-PWR7-LABEL: sub_absv_vec_8:
+; CHECK-PWR7:       # %bb.0: # %entry
+; CHECK-PWR7-NEXT:    vsububm v2, v2, v3
+; CHECK-PWR7-NEXT:    xxlxor v3, v3, v3
+; CHECK-PWR7-NEXT:    vsububm v3, v3, v2
+; CHECK-PWR7-NEXT:    vmaxsb v2, v2, v3
+; CHECK-PWR7-NEXT:    blr
 entry:
   %sub = sub nsw <16 x i8> %a, %b
   %sub.i = sub <16 x i8> zeroinitializer, %sub
   %0 = tail call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %sub, <16 x i8> %sub.i)
   ret <16 x i8> %0
 }
 
 define <4 x i32> @zext_sub_absd32(<4 x i16>, <4 x i16>) local_unnamed_addr {

 ; CHECK-PWR8-NEXT:    vsubuwm v2, v2, v3
 ; CHECK-PWR8-NEXT:    xxlxor v3, v3, v3
 ; CHECK-PWR8-NEXT:    vsubuwm v3, v3, v2
 ; CHECK-PWR8-NEXT:    vmaxsw v2, v2, v3
 ; CHECK-PWR8-NEXT:    blr
 ;
 ; CHECK-PWR7-LABEL: sext_sub_absd32:
 ; CHECK-PWR7:       # %bb.0:
+; CHECK-PWR7-NEXT:    vspltisw v4, 8
 ; CHECK-PWR7-NEXT:    vmrghh v2, v2, v2
 ; CHECK-PWR7-NEXT:    vmrghh v3, v3, v3
-; CHECK-PWR7-NEXT:    vspltisw v4, 8
 ; CHECK-PWR7-NEXT:    vadduwm v4, v4, v4
 ; CHECK-PWR7-NEXT:    vslw v2, v2, v4
 ; CHECK-PWR7-NEXT:    vslw v3, v3, v4
 ; CHECK-PWR7-NEXT:    vsraw v2, v2, v4
 ; CHECK-PWR7-NEXT:    vsraw v3, v3, v4
 ; CHECK-PWR7-NEXT:    vsubuwm v2, v2, v3
 ; CHECK-PWR7-NEXT:    xxlxor v3, v3, v3
 ; CHECK-PWR7-NEXT:    vsubuwm v3, v3, v2

 ; CHECK-PWR8-NEXT:    vsubuhm v2, v2, v3
 ; CHECK-PWR8-NEXT:    xxlxor v3, v3, v3
 ; CHECK-PWR8-NEXT:    vsubuhm v3, v3, v2
 ; CHECK-PWR8-NEXT:    vmaxsh v2, v2, v3
 ; CHECK-PWR8-NEXT:    blr
 ;
 ; CHECK-PWR7-LABEL: sext_sub_absd16:
 ; CHECK-PWR7:       # %bb.0:
+; CHECK-PWR7-NEXT:    vspltish v4, 8
 ; CHECK-PWR7-NEXT:    vmrghb v2, v2, v2
 ; CHECK-PWR7-NEXT:    vmrghb v3, v3, v3
-; CHECK-PWR7-NEXT:    vspltish v4, 8
 ; CHECK-PWR7-NEXT:    vslh v2, v2, v4
 ; CHECK-PWR7-NEXT:    vslh v3, v3, v4
 ; CHECK-PWR7-NEXT:    vsrah v2, v2, v4
 ; CHECK-PWR7-NEXT:    vsrah v3, v3, v4
 ; CHECK-PWR7-NEXT:    vsubuhm v2, v2, v3
 ; CHECK-PWR7-NEXT:    xxlxor v3, v3, v3
 ; CHECK-PWR7-NEXT:    vsubuhm v3, v3, v2
 ; CHECK-PWR7-NEXT:    vmaxsh v2, v2, v3

 ; CHECK-PWR8-NEXT:    vsubudm v5, v2, v3
 ; CHECK-PWR8-NEXT:    vsubudm v2, v3, v2
 ; CHECK-PWR8-NEXT:    xxsel v2, v2, v5, v4
 ; CHECK-PWR8-NEXT:    blr
 ;
 ; CHECK-PWR7-LABEL: absd_int64_ugt:
 ; CHECK-PWR7:       # %bb.0:
 ; CHECK-PWR7-NEXT:    addi r3, r1, -64
-; CHECK-PWR7-NEXT:    addi r4, r1, -80
 ; CHECK-PWR7-NEXT:    li r5, 0
 ; CHECK-PWR7-NEXT:    li r6, -1
 ; CHECK-PWR7-NEXT:    stxvd2x v3, 0, r3
-; CHECK-PWR7-NEXT:    stxvd2x v2, 0, r4
+; CHECK-PWR7-NEXT:    addi r3, r1, -80
+; CHECK-PWR7-NEXT:    stxvd2x v2, 0, r3
 ; CHECK-PWR7-NEXT:    ld r3, -56(r1)
 ; CHECK-PWR7-NEXT:    ld r4, -72(r1)
 ; CHECK-PWR7-NEXT:    ld r8, -80(r1)
 ; CHECK-PWR7-NEXT:    cmpld r4, r3
-; CHECK-PWR7-NEXT:    sub r9, r4, r3
 ; CHECK-PWR7-NEXT:    iselgt r7, r6, r5
-; CHECK-PWR7-NEXT:    sub r3, r3, r4
 ; CHECK-PWR7-NEXT:    std r7, -8(r1)
 ; CHECK-PWR7-NEXT:    ld r7, -64(r1)
 ; CHECK-PWR7-NEXT:    cmpld r8, r7
-; CHECK-PWR7-NEXT:    iselgt r4, r6, r5
+; CHECK-PWR7-NEXT:    iselgt r5, r6, r5
+; CHECK-PWR7-NEXT:    std r5, -16(r1)
 ; CHECK-PWR7-NEXT:    addi r5, r1, -16
-; CHECK-PWR7-NEXT:    std r4, -16(r1)
-; CHECK-PWR7-NEXT:    sub r4, r8, r7
 ; CHECK-PWR7-NEXT:    lxvd2x v2, 0, r5
-; CHECK-PWR7-NEXT:    std r9, -40(r1)
+; CHECK-PWR7-NEXT:    sub r5, r4, r3
+; CHECK-PWR7-NEXT:    sub r3, r3, r4
+; CHECK-PWR7-NEXT:    std r5, -40(r1)
+; CHECK-PWR7-NEXT:    sub r5, r8, r7
+; CHECK-PWR7-NEXT:    std r5, -48(r1)
 ; CHECK-PWR7-NEXT:    addi r5, r1, -48
-; CHECK-PWR7-NEXT:    std r4, -48(r1)
-; CHECK-PWR7-NEXT:    sub r4, r7, r8
 ; CHECK-PWR7-NEXT:    lxvd2x v3, 0, r5
 ; CHECK-PWR7-NEXT:    std r3, -24(r1)
+; CHECK-PWR7-NEXT:    sub r3, r7, r8
+; CHECK-PWR7-NEXT:    std r3, -32(r1)
 ; CHECK-PWR7-NEXT:    addi r3, r1, -32
-; CHECK-PWR7-NEXT:    std r4, -32(r1)
 ; CHECK-PWR7-NEXT:    lxvd2x v4, 0, r3
 ; CHECK-PWR7-NEXT:    xxsel v2, v4, v3, v2
 ; CHECK-PWR7-NEXT:    blr
   %3 = icmp ugt <2 x i64> %0, %1
   %4 = sub <2 x i64> %0, %1
   %5 = sub <2 x i64> %1, %0
   %6 = select <2 x i1> %3, <2 x i64> %4, <2 x i64> %5
   ret <2 x i64> %6
 }
 
 declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>)
 
 declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>)
 
 declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>)
 

llvm/test/CodeGen/PowerPC/ppcf128-endian.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -mattr=-vsx < %s | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-n32:64"
 target triple = "powerpc64le-unknown-linux-gnu"
 
 @g = common global ppc_fp128 0xM00000000000000000000000000000000, align 16
 
 define void @callee(ppc_fp128 %x) {
 ; CHECK-LABEL: callee:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LC0@toc@ha
 ; CHECK-NEXT:    stfd 2, -8(1)
-; CHECK-NEXT:    stfd 1, -16(1)
 ; CHECK-NEXT:    ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:    stfd 1, -16(1)
 ; CHECK-NEXT:    stfd 2, 8(3)
 ; CHECK-NEXT:    stfd 1, 0(3)
 ; CHECK-NEXT:    blr
 entry:
   %x.addr = alloca ppc_fp128, align 16
   store ppc_fp128 %x, ptr %x.addr, align 16
   %0 = load ppc_fp128, ptr %x.addr, align 16
   store ppc_fp128 %0, ptr @g, align 16

 ; CHECK-LABEL: caller_const:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr 0
 ; CHECK-NEXT:    stdu 1, -32(1)
 ; CHECK-NEXT:    std 0, 48(1)
 ; CHECK-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
-; CHECK-NEXT:    addis 4, 2, .LCPI2_1@toc@ha
 ; CHECK-NEXT:    lfs 1, .LCPI2_0@toc@l(3)
-; CHECK-NEXT:    lfs 2, .LCPI2_1@toc@l(4)
+; CHECK-NEXT:    addis 3, 2, .LCPI2_1@toc@ha
+; CHECK-NEXT:    lfs 2, .LCPI2_1@toc@l(3)
 ; CHECK-NEXT:    bl test
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    addi 1, 1, 32
 ; CHECK-NEXT:    ld 0, 16(1)
 ; CHECK-NEXT:    mtlr 0
 ; CHECK-NEXT:    blr
 entry:
   call void @test(ppc_fp128 0xM3FF00000000000000000000000000000)

 
 define ppc_fp128 @convert_to2(i128 %x) {
 ; CHECK-LABEL: convert_to2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rotldi 5, 3, 1
 ; CHECK-NEXT:    sldi 3, 3, 1
 ; CHECK-NEXT:    rldimi 5, 4, 1, 0
 ; CHECK-NEXT:    std 3, -16(1)
-; CHECK-NEXT:    std 5, -8(1)
 ; CHECK-NEXT:    lfd 1, -16(1)
+; CHECK-NEXT:    std 5, -8(1)
 ; CHECK-NEXT:    lfd 2, -8(1)
 ; CHECK-NEXT:    blr
 entry:
   %shl = shl i128 %x, 1
   %0 = bitcast i128 %shl to ppc_fp128
   ret ppc_fp128 %0
 }
 

 
 declare void @llvm.va_start(ptr)
 
 define double @vararg(i32 %a, ...) {
 ; CHECK-LABEL: vararg:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi 3, 1, 55
 ; CHECK-NEXT:    std 4, 40(1)
-; CHECK-NEXT:    rldicr 3, 3, 0, 59
 ; CHECK-NEXT:    std 5, 48(1)
-; CHECK-NEXT:    ori 4, 3, 8
 ; CHECK-NEXT:    std 6, 56(1)
+; CHECK-NEXT:    rldicr 3, 3, 0, 59
 ; CHECK-NEXT:    std 7, 64(1)
 ; CHECK-NEXT:    std 8, 72(1)
 ; CHECK-NEXT:    std 9, 80(1)
+; CHECK-NEXT:    ori 4, 3, 8
 ; CHECK-NEXT:    std 10, 88(1)
 ; CHECK-NEXT:    std 4, -8(1)
 ; CHECK-NEXT:    lfd 1, 0(3)
 ; CHECK-NEXT:    addi 3, 3, 16
 ; CHECK-NEXT:    std 3, -8(1)
 ; CHECK-NEXT:    blr
 entry:
   %va = alloca ptr, align 8
   call void @llvm.va_start(ptr %va)
   %arg = va_arg ptr %va, ppc_fp128
   %conv = fptrunc ppc_fp128 %arg to double
   ret double %conv
 }
 

llvm/test/CodeGen/PowerPC/pr61882.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -mtriple=powerpc \
 ; RUN:   -mcpu=pwr7 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -mtriple=powerpc \
 ; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=PWR8
 
 define void @foo(ptr %a, i32 %x) {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    rlwinm r5, r3, 3, 27, 28
-; CHECK-NEXT:    li r6, 255
 ; CHECK-NEXT:    extsb r4, r4
+; CHECK-NEXT:    li r6, 255
 ; CHECK-NEXT:    sync
-; CHECK-NEXT:    xori r5, r5, 24
 ; CHECK-NEXT:    rlwinm r3, r3, 0, 0, 29
+; CHECK-NEXT:    xori r5, r5, 24
 ; CHECK-NEXT:    slw r7, r4, r5
 ; CHECK-NEXT:    slw r6, r6, r5
 ; CHECK-NEXT:    and r7, r7, r6
 ; CHECK-NEXT:  .LBB0_1:
 ; CHECK-NEXT:    lwarx r8, 0, r3
 ; CHECK-NEXT:    and r9, r8, r6
 ; CHECK-NEXT:    srw r9, r9, r5
 ; CHECK-NEXT:    extsb r9, r9

llvm/test/CodeGen/PowerPC/recipest.ll

 declare <4 x float> @llvm.sqrt.v4f32(<4 x float>)
 declare <2 x double> @llvm.sqrt.v2f64(<2 x double>)
 
 define double @foo_fmf(double %a, double %b) nounwind {
 ; CHECK-P7-LABEL: foo_fmf:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    frsqrte 0, 2
 ; CHECK-P7-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
-; CHECK-P7-NEXT:    addis 4, 2, .LCPI0_1@toc@ha
-; CHECK-P7-NEXT:    lfs 4, .LCPI0_0@toc@l(3)
-; CHECK-P7-NEXT:    lfs 5, .LCPI0_1@toc@l(4)
-; CHECK-P7-NEXT:    fmul 3, 2, 0
-; CHECK-P7-NEXT:    fmadd 3, 3, 0, 4
+; CHECK-P7-NEXT:    lfs 3, .LCPI0_0@toc@l(3)
+; CHECK-P7-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
+; CHECK-P7-NEXT:    lfs 5, .LCPI0_1@toc@l(3)
+; CHECK-P7-NEXT:    fmul 4, 2, 0
+; CHECK-P7-NEXT:    fmadd 4, 4, 0, 3
 ; CHECK-P7-NEXT:    fmul 0, 0, 5
-; CHECK-P7-NEXT:    fmul 0, 0, 3
+; CHECK-P7-NEXT:    fmul 0, 0, 4
 ; CHECK-P7-NEXT:    fmul 2, 2, 0
-; CHECK-P7-NEXT:    fmadd 2, 2, 0, 4
+; CHECK-P7-NEXT:    fmadd 2, 2, 0, 3
 ; CHECK-P7-NEXT:    fmul 0, 0, 5
 ; CHECK-P7-NEXT:    fmul 0, 0, 2
 ; CHECK-P7-NEXT:    fmul 1, 1, 0
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: foo_fmf:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    vspltisw 2, -3
; CHECK-P9-NEXT:    blr
   ret double %r
 }
 
 define double @foof_fmf(double %a, float %b) nounwind {
 ; CHECK-P7-LABEL: foof_fmf:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    frsqrtes 0, 2
 ; CHECK-P7-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
-; CHECK-P7-NEXT:    addis 4, 2, .LCPI3_1@toc@ha
 ; CHECK-P7-NEXT:    lfs 3, .LCPI3_0@toc@l(3)
-; CHECK-P7-NEXT:    lfs 4, .LCPI3_1@toc@l(4)
+; CHECK-P7-NEXT:    addis 3, 2, .LCPI3_1@toc@ha
 ; CHECK-P7-NEXT:    fmuls 2, 2, 0
 ; CHECK-P7-NEXT:    fmadds 2, 2, 0, 3
-; CHECK-P7-NEXT:    fmuls 0, 0, 4
+; CHECK-P7-NEXT:    lfs 3, .LCPI3_1@toc@l(3)
+; CHECK-P7-NEXT:    fmuls 0, 0, 3
 ; CHECK-P7-NEXT:    fmuls 0, 0, 2
 ; CHECK-P7-NEXT:    fmul 1, 1, 0
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: foof_fmf:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    xsrsqrtesp 0, 2
 ; CHECK-P8-NEXT:    vspltisw 2, -3
; CHECK-P9-NEXT:    blr
   ret double %r
 }
 
 define float @food_fmf(float %a, double %b) nounwind {
 ; CHECK-P7-LABEL: food_fmf:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    frsqrte 0, 2
 ; CHECK-P7-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
-; CHECK-P7-NEXT:    addis 4, 2, .LCPI5_1@toc@ha
 ; CHECK-P7-NEXT:    lfs 4, .LCPI5_0@toc@l(3)
-; CHECK-P7-NEXT:    lfs 5, .LCPI5_1@toc@l(4)
+; CHECK-P7-NEXT:    addis 3, 2, .LCPI5_1@toc@ha
+; CHECK-P7-NEXT:    lfs 5, .LCPI5_1@toc@l(3)
 ; CHECK-P7-NEXT:    fmul 3, 2, 0
 ; CHECK-P7-NEXT:    fmadd 3, 3, 0, 4
 ; CHECK-P7-NEXT:    fmul 0, 0, 5
 ; CHECK-P7-NEXT:    fmul 0, 0, 3
 ; CHECK-P7-NEXT:    fmul 2, 2, 0
 ; CHECK-P7-NEXT:    fmadd 2, 2, 0, 4
 ; CHECK-P7-NEXT:    fmul 0, 0, 5
 ; CHECK-P7-NEXT:    fmul 0, 0, 2
; CHECK-P9-NEXT:    blr
   ret float %r
 }
 
 define float @goo_fmf(float %a, float %b) nounwind {
 ; CHECK-P7-LABEL: goo_fmf:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    frsqrtes 0, 2
 ; CHECK-P7-NEXT:    addis 3, 2, .LCPI7_0@toc@ha
-; CHECK-P7-NEXT:    addis 4, 2, .LCPI7_1@toc@ha
 ; CHECK-P7-NEXT:    lfs 3, .LCPI7_0@toc@l(3)
-; CHECK-P7-NEXT:    lfs 4, .LCPI7_1@toc@l(4)
+; CHECK-P7-NEXT:    addis 3, 2, .LCPI7_1@toc@ha
 ; CHECK-P7-NEXT:    fmuls 2, 2, 0
 ; CHECK-P7-NEXT:    fmadds 2, 2, 0, 3
-; CHECK-P7-NEXT:    fmuls 0, 0, 4
+; CHECK-P7-NEXT:    lfs 3, .LCPI7_1@toc@l(3)
+; CHECK-P7-NEXT:    fmuls 0, 0, 3
 ; CHECK-P7-NEXT:    fmuls 0, 0, 2
 ; CHECK-P7-NEXT:    fmuls 1, 1, 0
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: goo_fmf:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    xsrsqrtesp 0, 2
 ; CHECK-P8-NEXT:    vspltisw 2, -3
; CHECK-P9-NEXT:    blr
   ret float %r
 }
 
 define float @rsqrt_fmul_fmf(float %a, float %b, float %c) {
 ; CHECK-P7-LABEL: rsqrt_fmul_fmf:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    frsqrtes 0, 1
 ; CHECK-P7-NEXT:    addis 3, 2, .LCPI10_0@toc@ha
-; CHECK-P7-NEXT:    addis 4, 2, .LCPI10_1@toc@ha
 ; CHECK-P7-NEXT:    lfs 4, .LCPI10_0@toc@l(3)
-; CHECK-P7-NEXT:    lfs 5, .LCPI10_1@toc@l(4)
+; CHECK-P7-NEXT:    addis 3, 2, .LCPI10_1@toc@ha
+; CHECK-P7-NEXT:    lfs 5, .LCPI10_1@toc@l(3)
 ; CHECK-P7-NEXT:    fmuls 1, 1, 0
 ; CHECK-P7-NEXT:    fmadds 1, 1, 0, 4
 ; CHECK-P7-NEXT:    fmuls 0, 0, 5
 ; CHECK-P7-NEXT:    fmuls 0, 0, 1
 ; CHECK-P7-NEXT:    fres 1, 2
 ; CHECK-P7-NEXT:    fmuls 4, 0, 1
 ; CHECK-P7-NEXT:    fnmsubs 0, 2, 4, 0
 ; CHECK-P7-NEXT:    fmadds 0, 1, 0, 4
; CHECK-P9-NEXT:    blr
   %z = fdiv float %c, %y
   ret float %z
 }
 
 define <4 x float> @hoo_fmf(<4 x float> %a, <4 x float> %b) nounwind {
 ; CHECK-P7-LABEL: hoo_fmf:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    vspltisw 4, -1
-; CHECK-P7-NEXT:    addis 3, 2, .LCPI12_0@toc@ha
 ; CHECK-P7-NEXT:    vrsqrtefp 5, 3
+; CHECK-P7-NEXT:    addis 3, 2, .LCPI12_0@toc@ha
+; CHECK-P7-NEXT:    vslw 4, 4, 4
 ; CHECK-P7-NEXT:    addi 3, 3, .LCPI12_0@toc@l
 ; CHECK-P7-NEXT:    lvx 0, 0, 3
 ; CHECK-P7-NEXT:    addis 3, 2, .LCPI12_1@toc@ha
 ; CHECK-P7-NEXT:    addi 3, 3, .LCPI12_1@toc@l
-; CHECK-P7-NEXT:    lvx 1, 0, 3
-; CHECK-P7-NEXT:    vslw 4, 4, 4
 ; CHECK-P7-NEXT:    vmaddfp 3, 3, 5, 4
 ; CHECK-P7-NEXT:    vmaddfp 3, 3, 5, 0
-; CHECK-P7-NEXT:    vmaddfp 5, 5, 1, 4
+; CHECK-P7-NEXT:    lvx 0, 0, 3
+; CHECK-P7-NEXT:    vmaddfp 5, 5, 0, 4
 ; CHECK-P7-NEXT:    vmaddfp 3, 5, 3, 4
 ; CHECK-P7-NEXT:    vmaddfp 2, 2, 3, 4
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: hoo_fmf:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    xvrsqrtesp 0, 35
 ; CHECK-P8-NEXT:    addis 3, 2, .LCPI12_0@toc@ha

 }
 
 define <4 x float> @hoo_safe(<4 x float> %a, <4 x float> %b) nounwind {
 ; CHECK-P7-LABEL: hoo_safe:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    addi 3, 1, -32
 ; CHECK-P7-NEXT:    stvx 3, 0, 3
 ; CHECK-P7-NEXT:    addi 3, 1, -48
-; CHECK-P7-NEXT:    lfs 0, -20(1)
-; CHECK-P7-NEXT:    lfs 3, -24(1)
-; CHECK-P7-NEXT:    lfs 1, -32(1)
-; CHECK-P7-NEXT:    lfs 2, -28(1)
+; CHECK-P7-NEXT:    lfs 3, -20(1)
+; CHECK-P7-NEXT:    lfs 0, -32(1)
+; CHECK-P7-NEXT:    lfs 1, -28(1)
+; CHECK-P7-NEXT:    lfs 2, -24(1)
 ; CHECK-P7-NEXT:    stvx 2, 0, 3
 ; CHECK-P7-NEXT:    addi 3, 1, -16
-; CHECK-P7-NEXT:    fsqrts 0, 0
 ; CHECK-P7-NEXT:    lfs 4, -36(1)
 ; CHECK-P7-NEXT:    fsqrts 3, 3
 ; CHECK-P7-NEXT:    fsqrts 2, 2
 ; CHECK-P7-NEXT:    fsqrts 1, 1
-; CHECK-P7-NEXT:    fdivs 0, 4, 0
-; CHECK-P7-NEXT:    stfs 0, -4(1)
-; CHECK-P7-NEXT:    lfs 0, -40(1)
-; CHECK-P7-NEXT:    fdivs 0, 0, 3
-; CHECK-P7-NEXT:    stfs 0, -8(1)
-; CHECK-P7-NEXT:    lfs 0, -44(1)
-; CHECK-P7-NEXT:    fdivs 0, 0, 2
-; CHECK-P7-NEXT:    stfs 0, -12(1)
-; CHECK-P7-NEXT:    lfs 0, -48(1)
-; CHECK-P7-NEXT:    fdivs 0, 0, 1
+; CHECK-P7-NEXT:    fsqrts 0, 0
+; CHECK-P7-NEXT:    fdivs 3, 4, 3
+; CHECK-P7-NEXT:    stfs 3, -4(1)
+; CHECK-P7-NEXT:    lfs 3, -40(1)
+; CHECK-P7-NEXT:    fdivs 2, 3, 2
+; CHECK-P7-NEXT:    stfs 2, -8(1)
+; CHECK-P7-NEXT:    lfs 2, -44(1)
+; CHECK-P7-NEXT:    fdivs 1, 2, 1
+; CHECK-P7-NEXT:    stfs 1, -12(1)
+; CHECK-P7-NEXT:    lfs 1, -48(1)
+; CHECK-P7-NEXT:    fdivs 0, 1, 0
 ; CHECK-P7-NEXT:    stfs 0, -16(1)
 ; CHECK-P7-NEXT:    lvx 2, 0, 3
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: hoo_safe:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    xvsqrtsp 0, 35
 ; CHECK-P8-NEXT:    xvdivsp 34, 34, 0
; CHECK-P9-NEXT:    blr
   %r = fdiv contract reassoc arcp nsz ninf <4 x float> %a, %b
   ret <4 x float> %r
 }
 
 define <4 x float> @hoo2_safe(<4 x float> %a, <4 x float> %b) nounwind {
 ; CHECK-P7-LABEL: hoo2_safe:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    addi 3, 1, -32
-; CHECK-P7-NEXT:    addi 4, 1, -48
 ; CHECK-P7-NEXT:    stvx 3, 0, 3
-; CHECK-P7-NEXT:    stvx 2, 0, 4
+; CHECK-P7-NEXT:    addi 3, 1, -48
+; CHECK-P7-NEXT:    stvx 2, 0, 3
+; CHECK-P7-NEXT:    addi 3, 1, -16
 ; CHECK-P7-NEXT:    lfs 0, -20(1)
 ; CHECK-P7-NEXT:    lfs 1, -36(1)
-; CHECK-P7-NEXT:    addi 3, 1, -16
 ; CHECK-P7-NEXT:    fdivs 0, 1, 0
 ; CHECK-P7-NEXT:    lfs 1, -40(1)
 ; CHECK-P7-NEXT:    stfs 0, -4(1)
 ; CHECK-P7-NEXT:    lfs 0, -24(1)
 ; CHECK-P7-NEXT:    fdivs 0, 1, 0
 ; CHECK-P7-NEXT:    lfs 1, -44(1)
 ; CHECK-P7-NEXT:    stfs 0, -8(1)
 ; CHECK-P7-NEXT:    lfs 0, -28(1)

 define double @foo3_fmf(double %a) nounwind {
 ; CHECK-P7-LABEL: foo3_fmf:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    ftsqrt 0, 1
 ; CHECK-P7-NEXT:    bc 12, 2, .LBB20_2
 ; CHECK-P7-NEXT:  # %bb.1:
 ; CHECK-P7-NEXT:    frsqrte 0, 1
 ; CHECK-P7-NEXT:    addis 3, 2, .LCPI20_0@toc@ha
-; CHECK-P7-NEXT:    addis 4, 2, .LCPI20_1@toc@ha
 ; CHECK-P7-NEXT:    lfs 3, .LCPI20_0@toc@l(3)
-; CHECK-P7-NEXT:    lfs 4, .LCPI20_1@toc@l(4)
+; CHECK-P7-NEXT:    addis 3, 2, .LCPI20_1@toc@ha
+; CHECK-P7-NEXT:    lfs 4, .LCPI20_1@toc@l(3)
 ; CHECK-P7-NEXT:    fmul 2, 1, 0
 ; CHECK-P7-NEXT:    fmadd 2, 2, 0, 3
 ; CHECK-P7-NEXT:    fmul 0, 0, 4
 ; CHECK-P7-NEXT:    fmul 0, 0, 2
 ; CHECK-P7-NEXT:    fmul 1, 1, 0
 ; CHECK-P7-NEXT:    fmadd 0, 1, 0, 3
 ; CHECK-P7-NEXT:    fmul 1, 1, 4
 ; CHECK-P7-NEXT:    fmul 1, 1, 0

 ; CHECK-P7-NEXT:    fabs 0, 1
 ; CHECK-P7-NEXT:    addis 3, 2, .LCPI21_2@toc@ha
 ; CHECK-P7-NEXT:    lfd 2, .LCPI21_2@toc@l(3)
 ; CHECK-P7-NEXT:    fcmpu 0, 0, 2
 ; CHECK-P7-NEXT:    blt 0, .LBB21_2
 ; CHECK-P7-NEXT:  # %bb.1:
 ; CHECK-P7-NEXT:    frsqrte 0, 1
 ; CHECK-P7-NEXT:    addis 3, 2, .LCPI21_0@toc@ha
-; CHECK-P7-NEXT:    addis 4, 2, .LCPI21_1@toc@ha
 ; CHECK-P7-NEXT:    lfs 3, .LCPI21_0@toc@l(3)
-; CHECK-P7-NEXT:    lfs 4, .LCPI21_1@toc@l(4)
+; CHECK-P7-NEXT:    addis 3, 2, .LCPI21_1@toc@ha
+; CHECK-P7-NEXT:    lfs 4, .LCPI21_1@toc@l(3)
 ; CHECK-P7-NEXT:    fmul 2, 1, 0
 ; CHECK-P7-NEXT:    fmadd 2, 2, 0, 3
 ; CHECK-P7-NEXT:    fmul 0, 0, 4
 ; CHECK-P7-NEXT:    fmul 0, 0, 2
 ; CHECK-P7-NEXT:    fmul 1, 1, 0
 ; CHECK-P7-NEXT:    fmadd 0, 1, 0, 3
 ; CHECK-P7-NEXT:    fmul 1, 1, 4
 ; CHECK-P7-NEXT:    fmul 1, 1, 0

 ; CHECK-P7-NEXT:    fabs 0, 1
 ; CHECK-P7-NEXT:    addis 3, 2, .LCPI23_2@toc@ha
 ; CHECK-P7-NEXT:    lfs 2, .LCPI23_2@toc@l(3)
 ; CHECK-P7-NEXT:    fcmpu 0, 0, 2
 ; CHECK-P7-NEXT:    blt 0, .LBB23_2
 ; CHECK-P7-NEXT:  # %bb.1:
 ; CHECK-P7-NEXT:    frsqrtes 0, 1
 ; CHECK-P7-NEXT:    addis 3, 2, .LCPI23_0@toc@ha
-; CHECK-P7-NEXT:    addis 4, 2, .LCPI23_1@toc@ha
 ; CHECK-P7-NEXT:    lfs 2, .LCPI23_0@toc@l(3)
-; CHECK-P7-NEXT:    lfs 3, .LCPI23_1@toc@l(4)
+; CHECK-P7-NEXT:    addis 3, 2, .LCPI23_1@toc@ha
+; CHECK-P7-NEXT:    lfs 3, .LCPI23_1@toc@l(3)
 ; CHECK-P7-NEXT:    fmuls 1, 1, 0
 ; CHECK-P7-NEXT:    fmadds 0, 1, 0, 2
 ; CHECK-P7-NEXT:    fmuls 1, 1, 3
 ; CHECK-P7-NEXT:    fmuls 1, 1, 0
 ; CHECK-P7-NEXT:    blr
 ; CHECK-P7-NEXT:  .LBB23_2:
 ; CHECK-P7-NEXT:    addis 3, 2, .LCPI23_3@toc@ha
 ; CHECK-P7-NEXT:    lfs 1, .LCPI23_3@toc@l(3)
; CHECK-P9-NEXT:    blr
   %r = call float @llvm.sqrt.f32(float %a)
   ret float %r
 }
 
 define <4 x float> @hoo3_fmf(<4 x float> %a) #1 {
 ; CHECK-P7-LABEL: hoo3_fmf:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    vspltisw 3, -1
-; CHECK-P7-NEXT:    addis 3, 2, .LCPI25_0@toc@ha
 ; CHECK-P7-NEXT:    vrsqrtefp 4, 2
+; CHECK-P7-NEXT:    addis 3, 2, .LCPI25_0@toc@ha
+; CHECK-P7-NEXT:    vslw 3, 3, 3
 ; CHECK-P7-NEXT:    addi 3, 3, .LCPI25_0@toc@l
 ; CHECK-P7-NEXT:    lvx 0, 0, 3
 ; CHECK-P7-NEXT:    addis 3, 2, .LCPI25_1@toc@ha
 ; CHECK-P7-NEXT:    addi 3, 3, .LCPI25_1@toc@l
 ; CHECK-P7-NEXT:    lvx 1, 0, 3
-; CHECK-P7-NEXT:    vslw 3, 3, 3
 ; CHECK-P7-NEXT:    vmaddfp 5, 2, 4, 3
 ; CHECK-P7-NEXT:    vmaddfp 4, 5, 4, 0
 ; CHECK-P7-NEXT:    vmaddfp 5, 5, 1, 3
-; CHECK-P7-NEXT:    vxor 0, 0, 0
 ; CHECK-P7-NEXT:    vmaddfp 3, 5, 4, 3
-; CHECK-P7-NEXT:    vcmpeqfp 2, 2, 0
-; CHECK-P7-NEXT:    vsel 2, 3, 0, 2
+; CHECK-P7-NEXT:    vxor 4, 4, 4
+; CHECK-P7-NEXT:    vcmpeqfp 2, 2, 4
+; CHECK-P7-NEXT:    vsel 2, 3, 4, 2
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: hoo3_fmf:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    xvtsqrtsp 0, 34
 ; CHECK-P8-NEXT:    bc 12, 2, .LBB25_2
 ; CHECK-P8-NEXT:  # %bb.1:
 ; CHECK-P8-NEXT:    xvrsqrtesp 0, 34

 ; CHECK-P9-NEXT:    blr
   %r = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a)
   ret <4 x float> %r
 }
 
 define <2 x double> @hoo4_fmf(<2 x double> %a) #1 {
 ; CHECK-P7-LABEL: hoo4_fmf:
 ; CHECK-P7:       # %bb.0:
-; CHECK-P7-NEXT:    ftsqrt 0, 1
 ; CHECK-P7-NEXT:    addis 3, 2, .LCPI27_0@toc@ha
-; CHECK-P7-NEXT:    addis 4, 2, .LCPI27_1@toc@ha
-; CHECK-P7-NEXT:    lfs 3, .LCPI27_0@toc@l(3)
-; CHECK-P7-NEXT:    lfs 0, .LCPI27_1@toc@l(4)
+; CHECK-P7-NEXT:    ftsqrt 0, 1
+; CHECK-P7-NEXT:    lfs 0, .LCPI27_0@toc@l(3)
+; CHECK-P7-NEXT:    addis 3, 2, .LCPI27_1@toc@ha
+; CHECK-P7-NEXT:    lfs 3, .LCPI27_1@toc@l(3)
 ; CHECK-P7-NEXT:    bc 12, 2, .LBB27_3
 ; CHECK-P7-NEXT:  # %bb.1:
 ; CHECK-P7-NEXT:    frsqrte 4, 1
 ; CHECK-P7-NEXT:    fmul 5, 1, 4
-; CHECK-P7-NEXT:    fmadd 5, 5, 4, 3
-; CHECK-P7-NEXT:    fmul 4, 4, 0
+; CHECK-P7-NEXT:    fmadd 5, 5, 4, 0
+; CHECK-P7-NEXT:    fmul 4, 4, 3
 ; CHECK-P7-NEXT:    fmul 4, 4, 5
 ; CHECK-P7-NEXT:    fmul 1, 1, 4
-; CHECK-P7-NEXT:    fmadd 4, 1, 4, 3
-; CHECK-P7-NEXT:    fmul 1, 1, 0
+; CHECK-P7-NEXT:    fmadd 4, 1, 4, 0
+; CHECK-P7-NEXT:    fmul 1, 1, 3
 ; CHECK-P7-NEXT:    fmul 1, 1, 4
 ; CHECK-P7-NEXT:    ftsqrt 0, 2
 ; CHECK-P7-NEXT:    bc 4, 2, .LBB27_4
 ; CHECK-P7-NEXT:  .LBB27_2:
 ; CHECK-P7-NEXT:    fsqrt 2, 2
 ; CHECK-P7-NEXT:    blr
 ; CHECK-P7-NEXT:  .LBB27_3:
 ; CHECK-P7-NEXT:    fsqrt 1, 1
 ; CHECK-P7-NEXT:    ftsqrt 0, 2
 ; CHECK-P7-NEXT:    bc 12, 2, .LBB27_2
 ; CHECK-P7-NEXT:  .LBB27_4:
 ; CHECK-P7-NEXT:    frsqrte 4, 2
 ; CHECK-P7-NEXT:    fmul 5, 2, 4
-; CHECK-P7-NEXT:    fmadd 5, 5, 4, 3
-; CHECK-P7-NEXT:    fmul 4, 4, 0
+; CHECK-P7-NEXT:    fmadd 5, 5, 4, 0
+; CHECK-P7-NEXT:    fmul 4, 4, 3
 ; CHECK-P7-NEXT:    fmul 4, 4, 5
 ; CHECK-P7-NEXT:    fmul 2, 2, 4
-; CHECK-P7-NEXT:    fmadd 3, 2, 4, 3
-; CHECK-P7-NEXT:    fmul 0, 2, 0
-; CHECK-P7-NEXT:    fmul 2, 0, 3
+; CHECK-P7-NEXT:    fmadd 0, 2, 4, 0
+; CHECK-P7-NEXT:    fmul 2, 2, 3
+; CHECK-P7-NEXT:    fmul 2, 2, 0
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: hoo4_fmf:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    xvtsqrtdp 0, 34
 ; CHECK-P8-NEXT:    bc 12, 2, .LBB27_2
 ; CHECK-P8-NEXT:  # %bb.1:
 ; CHECK-P8-NEXT:    xvrsqrtedp 0, 34

llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll

 
 }
 
 define float @testfloateq(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
 ; CHECK-LABEL: testfloateq:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    fcmpu 0, 3, 4
 ; CHECK-NEXT:    fcmpu 1, 1, 2
-; CHECK-NEXT:    fmr 1, 5
 ; CHECK-NEXT:    creqv 20, 6, 2
-; CHECK-NEXT:    bclr 12, 20, 0
+; CHECK-NEXT:    bc 12, 20, .LBB24_2
 ; CHECK-NEXT:  # %bb.1: # %entry
-; CHECK-NEXT:    fmr 1, 6
+; CHECK-NEXT:    fmr 5, 6
+; CHECK-NEXT:  .LBB24_2: # %entry
+; CHECK-NEXT:    fmr 1, 5
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: testfloateq:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    fcmpu 0, 3, 4
 ; CHECK-NO-ISEL-NEXT:    fcmpu 1, 1, 2
-; CHECK-NO-ISEL-NEXT:    fmr 1, 5
 ; CHECK-NO-ISEL-NEXT:    creqv 20, 6, 2
-; CHECK-NO-ISEL-NEXT:    bclr 12, 20, 0
+; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB24_2
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT:    fmr 1, 6
+; CHECK-NO-ISEL-NEXT:    fmr 5, 6
+; CHECK-NO-ISEL-NEXT:  .LBB24_2: # %entry
+; CHECK-NO-ISEL-NEXT:    fmr 1, 5
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, float %a1, float %a2
   ret float %cond
 

 
 }
 
 define float @testfloatne(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
 ; CHECK-LABEL: testfloatne:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    fcmpu 0, 3, 4
 ; CHECK-NEXT:    fcmpu 1, 1, 2
-; CHECK-NEXT:    fmr 1, 5
 ; CHECK-NEXT:    crxor 20, 6, 2
-; CHECK-NEXT:    bclr 12, 20, 0
+; CHECK-NEXT:    bc 12, 20, .LBB29_2
 ; CHECK-NEXT:  # %bb.1: # %entry
-; CHECK-NEXT:    fmr 1, 6
+; CHECK-NEXT:    fmr 5, 6
+; CHECK-NEXT:  .LBB29_2: # %entry
+; CHECK-NEXT:    fmr 1, 5
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: testfloatne:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    fcmpu 0, 3, 4
 ; CHECK-NO-ISEL-NEXT:    fcmpu 1, 1, 2
-; CHECK-NO-ISEL-NEXT:    fmr 1, 5
 ; CHECK-NO-ISEL-NEXT:    crxor 20, 6, 2
-; CHECK-NO-ISEL-NEXT:    bclr 12, 20, 0
+; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB29_2
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT:    fmr 1, 6
+; CHECK-NO-ISEL-NEXT:    fmr 5, 6
+; CHECK-NO-ISEL-NEXT:  .LBB29_2: # %entry
+; CHECK-NO-ISEL-NEXT:    fmr 1, 5
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, float %a1, float %a2
   ret float %cond
 

 
 }
 
 define double @testdoubleeq(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
 ; CHECK-LABEL: testdoubleeq:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    fcmpu 0, 3, 4
 ; CHECK-NEXT:    fcmpu 1, 1, 2
-; CHECK-NEXT:    fmr 1, 5
 ; CHECK-NEXT:    creqv 20, 6, 2
-; CHECK-NEXT:    bclr 12, 20, 0
+; CHECK-NEXT:    bc 12, 20, .LBB34_2
 ; CHECK-NEXT:  # %bb.1: # %entry
-; CHECK-NEXT:    fmr 1, 6
+; CHECK-NEXT:    fmr 5, 6
+; CHECK-NEXT:  .LBB34_2: # %entry
+; CHECK-NEXT:    fmr 1, 5
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: testdoubleeq:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    fcmpu 0, 3, 4
 ; CHECK-NO-ISEL-NEXT:    fcmpu 1, 1, 2
-; CHECK-NO-ISEL-NEXT:    fmr 1, 5
 ; CHECK-NO-ISEL-NEXT:    creqv 20, 6, 2
-; CHECK-NO-ISEL-NEXT:    bclr 12, 20, 0
+; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB34_2
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT:    fmr 1, 6
+; CHECK-NO-ISEL-NEXT:    fmr 5, 6
+; CHECK-NO-ISEL-NEXT:  .LBB34_2: # %entry
+; CHECK-NO-ISEL-NEXT:    fmr 1, 5
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %cmp1 = fcmp oeq double %c3, %c4
   %cmp3tmp = fcmp oeq double %c1, %c2
   %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, double %a1, double %a2
   ret double %cond
 

 
 }
 
 define double @testdoublene(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
 ; CHECK-LABEL: testdoublene:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    fcmpu 0, 3, 4
 ; CHECK-NEXT:    fcmpu 1, 1, 2
-; CHECK-NEXT:    fmr 1, 5
 ; CHECK-NEXT:    crxor 20, 6, 2
-; CHECK-NEXT:    bclr 12, 20, 0
+; CHECK-NEXT:    bc 12, 20, .LBB39_2
 ; CHECK-NEXT:  # %bb.1: # %entry
-; CHECK-NEXT:    fmr 1, 6
+; CHECK-NEXT:    fmr 5, 6
+; CHECK-NEXT:  .LBB39_2: # %entry
+; CHECK-NEXT:    fmr 1, 5
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: testdoublene:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    fcmpu 0, 3, 4
 ; CHECK-NO-ISEL-NEXT:    fcmpu 1, 1, 2
-; CHECK-NO-ISEL-NEXT:    fmr 1, 5
 ; CHECK-NO-ISEL-NEXT:    crxor 20, 6, 2
-; CHECK-NO-ISEL-NEXT:    bclr 12, 20, 0
+; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB39_2
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT:    fmr 1, 6
+; CHECK-NO-ISEL-NEXT:    fmr 5, 6
+; CHECK-NO-ISEL-NEXT:  .LBB39_2: # %entry
+; CHECK-NO-ISEL-NEXT:    fmr 1, 5
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %cmp1 = fcmp oeq double %c3, %c4
   %cmp3tmp = fcmp oeq double %c1, %c2
   %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, double %a1, double %a2
   ret double %cond
 

 
 }
 
 define ppc_fp128 @testppc_fp128eq(ppc_fp128 %c1, ppc_fp128 %c2, ppc_fp128 %c3, ppc_fp128 %c4, ppc_fp128 %a1, ppc_fp128 %a2) #0 {
 ; CHECK-LABEL: testppc_fp128eq:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    fcmpu 0, 6, 8
 ; CHECK-NEXT:    fcmpu 1, 5, 7
-; CHECK-NEXT:    fcmpu 5, 2, 4
-; CHECK-NEXT:    fcmpu 6, 1, 3
 ; CHECK-NEXT:    crand 20, 6, 2
-; CHECK-NEXT:    crand 21, 26, 22
+; CHECK-NEXT:    fcmpu 0, 2, 4
+; CHECK-NEXT:    fcmpu 1, 1, 3
+; CHECK-NEXT:    crand 21, 6, 2
 ; CHECK-NEXT:    crxor 20, 21, 20
 ; CHECK-NEXT:    bc 12, 20, .LBB50_2
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    fmr 11, 9
 ; CHECK-NEXT:  .LBB50_2: # %entry
 ; CHECK-NEXT:    bc 12, 20, .LBB50_4
 ; CHECK-NEXT:  # %bb.3: # %entry
 ; CHECK-NEXT:    fmr 12, 10
 ; CHECK-NEXT:  .LBB50_4: # %entry
 ; CHECK-NEXT:    fmr 1, 11
 ; CHECK-NEXT:    fmr 2, 12
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: testppc_fp128eq:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    fcmpu 0, 6, 8
 ; CHECK-NO-ISEL-NEXT:    fcmpu 1, 5, 7
-; CHECK-NO-ISEL-NEXT:    fcmpu 5, 2, 4
-; CHECK-NO-ISEL-NEXT:    fcmpu 6, 1, 3
 ; CHECK-NO-ISEL-NEXT:    crand 20, 6, 2
-; CHECK-NO-ISEL-NEXT:    crand 21, 26, 22
+; CHECK-NO-ISEL-NEXT:    fcmpu 0, 2, 4
+; CHECK-NO-ISEL-NEXT:    fcmpu 1, 1, 3
+; CHECK-NO-ISEL-NEXT:    crand 21, 6, 2
 ; CHECK-NO-ISEL-NEXT:    crxor 20, 21, 20
 ; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB50_2
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
 ; CHECK-NO-ISEL-NEXT:    fmr 11, 9
 ; CHECK-NO-ISEL-NEXT:  .LBB50_2: # %entry
 ; CHECK-NO-ISEL-NEXT:    bc 12, 20, .LBB50_4
 ; CHECK-NO-ISEL-NEXT:  # %bb.3: # %entry
 ; CHECK-NO-ISEL-NEXT:    fmr 12, 10

llvm/test/CodeGen/PowerPC/test-vector-insert.ll

 ; xscvdpsxws and xscvdpsxws is only available on Power7 and above
 ; Codgen is different for Power7, Power8, and Power9.
 
 define dso_local <4 x i32> @test(<4 x i32> %a, double %b) {
 ; CHECK-LE-P7-LABEL: test:
 ; CHECK-LE-P7:       # %bb.0: # %entry
 ; CHECK-LE-P7-NEXT:    xscvdpsxws f0, f1
 ; CHECK-LE-P7-NEXT:    addi r3, r1, -4
-; CHECK-LE-P7-NEXT:    addis r4, r2, .LCPI0_0@toc@ha
-; CHECK-LE-P7-NEXT:    addi r4, r4, .LCPI0_0@toc@l
 ; CHECK-LE-P7-NEXT:    stfiwx f0, 0, r3
-; CHECK-LE-P7-NEXT:    lxvd2x vs0, 0, r4
 ; CHECK-LE-P7-NEXT:    lwz r3, -4(r1)
 ; CHECK-LE-P7-NEXT:    stw r3, -32(r1)
+; CHECK-LE-P7-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
+; CHECK-LE-P7-NEXT:    addi r3, r3, .LCPI0_0@toc@l
+; CHECK-LE-P7-NEXT:    lxvd2x vs0, 0, r3
 ; CHECK-LE-P7-NEXT:    addi r3, r1, -32
 ; CHECK-LE-P7-NEXT:    xxswapd v3, vs0
-; CHECK-LE-P7-NEXT:    lxvd2x vs1, 0, r3
-; CHECK-LE-P7-NEXT:    xxswapd v4, vs1
+; CHECK-LE-P7-NEXT:    lxvd2x vs0, 0, r3
+; CHECK-LE-P7-NEXT:    xxswapd v4, vs0
 ; CHECK-LE-P7-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-LE-P7-NEXT:    blr
 ;
 ; CHECK-LE-P8-LABEL: test:
 ; CHECK-LE-P8:       # %bb.0: # %entry
 ; CHECK-LE-P8-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
 ; CHECK-LE-P8-NEXT:    xscvdpsxws v3, f1
 ; CHECK-LE-P8-NEXT:    addi r3, r3, .LCPI0_0@toc@l
 ; CHECK-LE-P8-NEXT:    lxvd2x vs0, 0, r3
 ; CHECK-LE-P8-NEXT:    xxswapd v4, vs0
 ; CHECK-LE-P8-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test:
 ; CHECK-LE-P9:       # %bb.0: # %entry
 ; CHECK-LE-P9-NEXT:    xscvdpsxws f0, f1
 ; CHECK-LE-P9-NEXT:    xxinsertw v2, vs0, 0
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P7-LABEL: test:
 ; CHECK-BE-P7:       # %bb.0: # %entry
 ; CHECK-BE-P7-NEXT:    xscvdpsxws f0, f1
 ; CHECK-BE-P7-NEXT:    addi r3, r1, -4
-; CHECK-BE-P7-NEXT:    addis r4, r2, .LCPI0_0@toc@ha
 ; CHECK-BE-P7-NEXT:    stfiwx f0, 0, r3
 ; CHECK-BE-P7-NEXT:    lwz r3, -4(r1)
 ; CHECK-BE-P7-NEXT:    stw r3, -32(r1)
-; CHECK-BE-P7-NEXT:    addi r3, r4, .LCPI0_0@toc@l
-; CHECK-BE-P7-NEXT:    addi r4, r1, -32
+; CHECK-BE-P7-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
+; CHECK-BE-P7-NEXT:    addi r3, r3, .LCPI0_0@toc@l
 ; CHECK-BE-P7-NEXT:    lxvw4x v3, 0, r3
-; CHECK-BE-P7-NEXT:    lxvw4x v4, 0, r4
+; CHECK-BE-P7-NEXT:    addi r3, r1, -32
+; CHECK-BE-P7-NEXT:    lxvw4x v4, 0, r3
 ; CHECK-BE-P7-NEXT:    vperm v2, v2, v4, v3
 ; CHECK-BE-P7-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    xscvdpsxws v3, f1
 ; CHECK-BE-P8-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
 ; CHECK-BE-P8-NEXT:    addi r3, r3, .LCPI0_0@toc@l
entry:
   ret <4 x i32> %vecins
 }
 
 define dso_local <4 x i32> @test2(<4 x i32> %a, float %b) {
 ; CHECK-LE-P7-LABEL: test2:
 ; CHECK-LE-P7:       # %bb.0: # %entry
 ; CHECK-LE-P7-NEXT:    xscvdpsxws f0, f1
 ; CHECK-LE-P7-NEXT:    addi r3, r1, -4
-; CHECK-LE-P7-NEXT:    addis r4, r2, .LCPI1_0@toc@ha
-; CHECK-LE-P7-NEXT:    addi r4, r4, .LCPI1_0@toc@l
 ; CHECK-LE-P7-NEXT:    stfiwx f0, 0, r3
-; CHECK-LE-P7-NEXT:    lxvd2x vs0, 0, r4
 ; CHECK-LE-P7-NEXT:    lwz r3, -4(r1)
 ; CHECK-LE-P7-NEXT:    stw r3, -32(r1)
+; CHECK-LE-P7-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
+; CHECK-LE-P7-NEXT:    addi r3, r3, .LCPI1_0@toc@l
+; CHECK-LE-P7-NEXT:    lxvd2x vs0, 0, r3
 ; CHECK-LE-P7-NEXT:    addi r3, r1, -32
 ; CHECK-LE-P7-NEXT:    xxswapd v3, vs0
-; CHECK-LE-P7-NEXT:    lxvd2x vs1, 0, r3
-; CHECK-LE-P7-NEXT:    xxswapd v4, vs1
+; CHECK-LE-P7-NEXT:    lxvd2x vs0, 0, r3
+; CHECK-LE-P7-NEXT:    xxswapd v4, vs0
 ; CHECK-LE-P7-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-LE-P7-NEXT:    blr
 ;
 ; CHECK-LE-P8-LABEL: test2:
 ; CHECK-LE-P8:       # %bb.0: # %entry
 ; CHECK-LE-P8-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
 ; CHECK-LE-P8-NEXT:    xscvdpsxws v3, f1
 ; CHECK-LE-P8-NEXT:    addi r3, r3, .LCPI1_0@toc@l
 ; CHECK-LE-P8-NEXT:    lxvd2x vs0, 0, r3
 ; CHECK-LE-P8-NEXT:    xxswapd v4, vs0
 ; CHECK-LE-P8-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test2:
 ; CHECK-LE-P9:       # %bb.0: # %entry
 ; CHECK-LE-P9-NEXT:    xscvdpsxws f0, f1
 ; CHECK-LE-P9-NEXT:    xxinsertw v2, vs0, 0
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P7-LABEL: test2:
 ; CHECK-BE-P7:       # %bb.0: # %entry
 ; CHECK-BE-P7-NEXT:    xscvdpsxws f0, f1
 ; CHECK-BE-P7-NEXT:    addi r3, r1, -4
-; CHECK-BE-P7-NEXT:    addis r4, r2, .LCPI1_0@toc@ha
 ; CHECK-BE-P7-NEXT:    stfiwx f0, 0, r3
 ; CHECK-BE-P7-NEXT:    lwz r3, -4(r1)
 ; CHECK-BE-P7-NEXT:    stw r3, -32(r1)
-; CHECK-BE-P7-NEXT:    addi r3, r4, .LCPI1_0@toc@l
-; CHECK-BE-P7-NEXT:    addi r4, r1, -32
+; CHECK-BE-P7-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
+; CHECK-BE-P7-NEXT:    addi r3, r3, .LCPI1_0@toc@l
 ; CHECK-BE-P7-NEXT:    lxvw4x v3, 0, r3
-; CHECK-BE-P7-NEXT:    lxvw4x v4, 0, r4
+; CHECK-BE-P7-NEXT:    addi r3, r1, -32
+; CHECK-BE-P7-NEXT:    lxvw4x v4, 0, r3
 ; CHECK-BE-P7-NEXT:    vperm v2, v2, v4, v3
 ; CHECK-BE-P7-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test2:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    xscvdpsxws v3, f1
 ; CHECK-BE-P8-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
 ; CHECK-BE-P8-NEXT:    addi r3, r3, .LCPI1_0@toc@l
entry:
   ret <4 x i32> %vecins
 }
 
 define dso_local <4 x i32> @test3(<4 x i32> %a, double %b) {
 ; CHECK-LE-P7-LABEL: test3:
 ; CHECK-LE-P7:       # %bb.0: # %entry
 ; CHECK-LE-P7-NEXT:    xscvdpuxws f0, f1
 ; CHECK-LE-P7-NEXT:    addi r3, r1, -4
-; CHECK-LE-P7-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
-; CHECK-LE-P7-NEXT:    addi r4, r4, .LCPI2_0@toc@l
 ; CHECK-LE-P7-NEXT:    stfiwx f0, 0, r3
-; CHECK-LE-P7-NEXT:    lxvd2x vs0, 0, r4
 ; CHECK-LE-P7-NEXT:    lwz r3, -4(r1)
 ; CHECK-LE-P7-NEXT:    stw r3, -32(r1)
+; CHECK-LE-P7-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
+; CHECK-LE-P7-NEXT:    addi r3, r3, .LCPI2_0@toc@l
+; CHECK-LE-P7-NEXT:    lxvd2x vs0, 0, r3
 ; CHECK-LE-P7-NEXT:    addi r3, r1, -32
 ; CHECK-LE-P7-NEXT:    xxswapd v3, vs0
-; CHECK-LE-P7-NEXT:    lxvd2x vs1, 0, r3
-; CHECK-LE-P7-NEXT:    xxswapd v4, vs1
+; CHECK-LE-P7-NEXT:    lxvd2x vs0, 0, r3
+; CHECK-LE-P7-NEXT:    xxswapd v4, vs0
 ; CHECK-LE-P7-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-LE-P7-NEXT:    blr
 ;
 ; CHECK-LE-P8-LABEL: test3:
 ; CHECK-LE-P8:       # %bb.0: # %entry
 ; CHECK-LE-P8-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; CHECK-LE-P8-NEXT:    xscvdpuxws v3, f1
 ; CHECK-LE-P8-NEXT:    addi r3, r3, .LCPI2_0@toc@l
 ; CHECK-LE-P8-NEXT:    lxvd2x vs0, 0, r3
 ; CHECK-LE-P8-NEXT:    xxswapd v4, vs0
 ; CHECK-LE-P8-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test3:
 ; CHECK-LE-P9:       # %bb.0: # %entry
 ; CHECK-LE-P9-NEXT:    xscvdpuxws f0, f1
 ; CHECK-LE-P9-NEXT:    xxinsertw v2, vs0, 0
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P7-LABEL: test3:
 ; CHECK-BE-P7:       # %bb.0: # %entry
 ; CHECK-BE-P7-NEXT:    xscvdpuxws f0, f1
 ; CHECK-BE-P7-NEXT:    addi r3, r1, -4
-; CHECK-BE-P7-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
 ; CHECK-BE-P7-NEXT:    stfiwx f0, 0, r3
 ; CHECK-BE-P7-NEXT:    lwz r3, -4(r1)
 ; CHECK-BE-P7-NEXT:    stw r3, -32(r1)
-; CHECK-BE-P7-NEXT:    addi r3, r4, .LCPI2_0@toc@l
-; CHECK-BE-P7-NEXT:    addi r4, r1, -32
+; CHECK-BE-P7-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
+; CHECK-BE-P7-NEXT:    addi r3, r3, .LCPI2_0@toc@l
 ; CHECK-BE-P7-NEXT:    lxvw4x v3, 0, r3
-; CHECK-BE-P7-NEXT:    lxvw4x v4, 0, r4
+; CHECK-BE-P7-NEXT:    addi r3, r1, -32
+; CHECK-BE-P7-NEXT:    lxvw4x v4, 0, r3
 ; CHECK-BE-P7-NEXT:    vperm v2, v2, v4, v3
 ; CHECK-BE-P7-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test3:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    xscvdpuxws v3, f1
 ; CHECK-BE-P8-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; CHECK-BE-P8-NEXT:    addi r3, r3, .LCPI2_0@toc@l
entry:
   ret <4 x i32> %vecins
 }
 
 define dso_local <4 x i32> @test4(<4 x i32> %a, float %b) {
 ; CHECK-LE-P7-LABEL: test4:
 ; CHECK-LE-P7:       # %bb.0: # %entry
 ; CHECK-LE-P7-NEXT:    xscvdpuxws f0, f1
 ; CHECK-LE-P7-NEXT:    addi r3, r1, -4
-; CHECK-LE-P7-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
-; CHECK-LE-P7-NEXT:    addi r4, r4, .LCPI3_0@toc@l
 ; CHECK-LE-P7-NEXT:    stfiwx f0, 0, r3
-; CHECK-LE-P7-NEXT:    lxvd2x vs0, 0, r4
 ; CHECK-LE-P7-NEXT:    lwz r3, -4(r1)
 ; CHECK-LE-P7-NEXT:    stw r3, -32(r1)
+; CHECK-LE-P7-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
+; CHECK-LE-P7-NEXT:    addi r3, r3, .LCPI3_0@toc@l
+; CHECK-LE-P7-NEXT:    lxvd2x vs0, 0, r3
 ; CHECK-LE-P7-NEXT:    addi r3, r1, -32
 ; CHECK-LE-P7-NEXT:    xxswapd v3, vs0
-; CHECK-LE-P7-NEXT:    lxvd2x vs1, 0, r3
-; CHECK-LE-P7-NEXT:    xxswapd v4, vs1
+; CHECK-LE-P7-NEXT:    lxvd2x vs0, 0, r3
+; CHECK-LE-P7-NEXT:    xxswapd v4, vs0
 ; CHECK-LE-P7-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-LE-P7-NEXT:    blr
 ;
 ; CHECK-LE-P8-LABEL: test4:
 ; CHECK-LE-P8:       # %bb.0: # %entry
 ; CHECK-LE-P8-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
 ; CHECK-LE-P8-NEXT:    xscvdpuxws v3, f1
 ; CHECK-LE-P8-NEXT:    addi r3, r3, .LCPI3_0@toc@l
 ; CHECK-LE-P8-NEXT:    lxvd2x vs0, 0, r3
 ; CHECK-LE-P8-NEXT:    xxswapd v4, vs0
 ; CHECK-LE-P8-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test4:
 ; CHECK-LE-P9:       # %bb.0: # %entry
 ; CHECK-LE-P9-NEXT:    xscvdpuxws f0, f1
 ; CHECK-LE-P9-NEXT:    xxinsertw v2, vs0, 0
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P7-LABEL: test4:
 ; CHECK-BE-P7:       # %bb.0: # %entry
 ; CHECK-BE-P7-NEXT:    xscvdpuxws f0, f1
 ; CHECK-BE-P7-NEXT:    addi r3, r1, -4
-; CHECK-BE-P7-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
 ; CHECK-BE-P7-NEXT:    stfiwx f0, 0, r3
 ; CHECK-BE-P7-NEXT:    lwz r3, -4(r1)
 ; CHECK-BE-P7-NEXT:    stw r3, -32(r1)
-; CHECK-BE-P7-NEXT:    addi r3, r4, .LCPI3_0@toc@l
-; CHECK-BE-P7-NEXT:    addi r4, r1, -32
+; CHECK-BE-P7-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
+; CHECK-BE-P7-NEXT:    addi r3, r3, .LCPI3_0@toc@l
 ; CHECK-BE-P7-NEXT:    lxvw4x v3, 0, r3
-; CHECK-BE-P7-NEXT:    lxvw4x v4, 0, r4
+; CHECK-BE-P7-NEXT:    addi r3, r1, -32
+; CHECK-BE-P7-NEXT:    lxvw4x v4, 0, r3
 ; CHECK-BE-P7-NEXT:    vperm v2, v2, v4, v3
 ; CHECK-BE-P7-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test4:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    xscvdpuxws v3, f1
 ; CHECK-BE-P8-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
 ; CHECK-BE-P8-NEXT:    addi r3, r3, .LCPI3_0@toc@l

llvm/test/CodeGen/PowerPC/unal-vec-ldst.ll

 define <32 x i8> @test_l_v32i8(ptr %p) #0 {
 ; CHECK-LABEL: test_l_v32i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li 4, 31
 ; CHECK-NEXT:    lvsl 5, 0, 3
 ; CHECK-NEXT:    lvx 2, 3, 4
 ; CHECK-NEXT:    li 4, 16
 ; CHECK-NEXT:    lvx 4, 3, 4
-; CHECK-NEXT:    lvx 0, 0, 3
 ; CHECK-NEXT:    vperm 3, 4, 2, 5
-; CHECK-NEXT:    vperm 2, 0, 4, 5
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    vperm 2, 2, 4, 5
 ; CHECK-NEXT:    blr
 entry:
   %r = load <32 x i8>, ptr %p, align 1
   ret <32 x i8> %r
 
 }
 
 define <8 x i16> @test_l_v8i16(ptr %p) #0 {

 define <16 x i16> @test_l_v16i16(ptr %p) #0 {
 ; CHECK-LABEL: test_l_v16i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li 4, 31
 ; CHECK-NEXT:    lvsl 5, 0, 3
 ; CHECK-NEXT:    lvx 2, 3, 4
 ; CHECK-NEXT:    li 4, 16
 ; CHECK-NEXT:    lvx 4, 3, 4
-; CHECK-NEXT:    lvx 0, 0, 3
 ; CHECK-NEXT:    vperm 3, 4, 2, 5
-; CHECK-NEXT:    vperm 2, 0, 4, 5
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    vperm 2, 2, 4, 5
 ; CHECK-NEXT:    blr
 entry:
   %r = load <16 x i16>, ptr %p, align 2
   ret <16 x i16> %r
 
 }
 
 define <4 x i32> @test_l_v4i32(ptr %p) #0 {

 define <8 x i32> @test_l_v8i32(ptr %p) #0 {
 ; CHECK-LABEL: test_l_v8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li 4, 31
 ; CHECK-NEXT:    lvsl 5, 0, 3
 ; CHECK-NEXT:    lvx 2, 3, 4
 ; CHECK-NEXT:    li 4, 16
 ; CHECK-NEXT:    lvx 4, 3, 4
-; CHECK-NEXT:    lvx 0, 0, 3
 ; CHECK-NEXT:    vperm 3, 4, 2, 5
-; CHECK-NEXT:    vperm 2, 0, 4, 5
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    vperm 2, 2, 4, 5
 ; CHECK-NEXT:    blr
 entry:
   %r = load <8 x i32>, ptr %p, align 4
   ret <8 x i32> %r
 
 }
 
 define <2 x i64> @test_l_v2i64(ptr %p) #0 {

 define <8 x float> @test_l_v8float(ptr %p) #0 {
 ; CHECK-LABEL: test_l_v8float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li 4, 31
 ; CHECK-NEXT:    lvsl 5, 0, 3
 ; CHECK-NEXT:    lvx 2, 3, 4
 ; CHECK-NEXT:    li 4, 16
 ; CHECK-NEXT:    lvx 4, 3, 4
-; CHECK-NEXT:    lvx 0, 0, 3
 ; CHECK-NEXT:    vperm 3, 4, 2, 5
-; CHECK-NEXT:    vperm 2, 0, 4, 5
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    vperm 2, 2, 4, 5
 ; CHECK-NEXT:    blr
 entry:
   %r = load <8 x float>, ptr %p, align 4
   ret <8 x float> %r
 
 }
 
 define <2 x double> @test_l_v2double(ptr %p) #0 {

llvm/test/CodeGen/PowerPC/unal4-std.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 -mattr=-vsx| FileCheck %s
 ; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define void @copy_to_conceal(ptr %inp) #0 {
 ; CHECK-LABEL: copy_to_conceal:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vxor 2, 2, 2
 ; CHECK-NEXT:    addi 4, 1, -16
+; CHECK-NEXT:    vxor 2, 2, 2
 ; CHECK-NEXT:    stvx 2, 0, 4
 ; CHECK-NEXT:    ld 4, -8(1)
 ; CHECK-NEXT:    std 4, 8(3)
 ; CHECK-NEXT:    ld 4, -16(1)
 ; CHECK-NEXT:    std 4, 0(3)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-VSX-LABEL: copy_to_conceal:

llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll

 ; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-BE-NEXT:    mfvsrd 4, 34
 ; CHECK-BE-NEXT:    srd 3, 4, 3
 ; CHECK-BE-NEXT:    clrldi 3, 3, 32
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: geti:
 ; CHECK-P7:       # %bb.0: # %entry
-; CHECK-P7-NEXT:    addi 3, 1, -16
-; CHECK-P7-NEXT:    rlwinm 4, 5, 2, 28, 29
-; CHECK-P7-NEXT:    stxvw4x 34, 0, 3
-; CHECK-P7-NEXT:    lwzx 3, 3, 4
+; CHECK-P7-NEXT:    addi 4, 1, -16
+; CHECK-P7-NEXT:    rlwinm 3, 5, 2, 28, 29
+; CHECK-P7-NEXT:    stxvw4x 34, 0, 4
+; CHECK-P7-NEXT:    lwzx 3, 4, 3
 ; CHECK-P7-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %a, i32 %b
   ret i32 %vecext
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @getl(<2 x i64> %a, i32 zeroext %b) {

 ; CHECK-BE-NEXT:    sldi 3, 3, 3
 ; CHECK-BE-NEXT:    lvsl 3, 0, 3
 ; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-BE-NEXT:    mfvsrd 3, 34
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: getl:
 ; CHECK-P7:       # %bb.0: # %entry
-; CHECK-P7-NEXT:    addi 3, 1, -16
-; CHECK-P7-NEXT:    rlwinm 4, 5, 3, 28, 28
-; CHECK-P7-NEXT:    stxvd2x 34, 0, 3
-; CHECK-P7-NEXT:    ldx 3, 3, 4
+; CHECK-P7-NEXT:    addi 4, 1, -16
+; CHECK-P7-NEXT:    rlwinm 3, 5, 3, 28, 28
+; CHECK-P7-NEXT:    stxvd2x 34, 0, 4
+; CHECK-P7-NEXT:    ldx 3, 4, 3
 ; CHECK-P7-NEXT:    blr
 entry:
   %vecext = extractelement <2 x i64> %a, i32 %b
   ret i64 %vecext
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @getf(<4 x float> %a, i32 zeroext %b) {

 ; CHECK-BE-NEXT:    sldi 3, 5, 2
 ; CHECK-BE-NEXT:    lvsl 3, 0, 3
 ; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-BE-NEXT:    xscvspdpn 1, 34
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: getf:
 ; CHECK-P7:       # %bb.0: # %entry
-; CHECK-P7-NEXT:    addi 3, 1, -16
-; CHECK-P7-NEXT:    rlwinm 4, 5, 2, 28, 29
-; CHECK-P7-NEXT:    stxvw4x 34, 0, 3
-; CHECK-P7-NEXT:    lfsx 1, 3, 4
+; CHECK-P7-NEXT:    addi 4, 1, -16
+; CHECK-P7-NEXT:    rlwinm 3, 5, 2, 28, 29
+; CHECK-P7-NEXT:    stxvw4x 34, 0, 4
+; CHECK-P7-NEXT:    lfsx 1, 4, 3
 ; CHECK-P7-NEXT:    blr
 entry:
   %vecext = extractelement <4 x float> %a, i32 %b
   ret float %vecext
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @getd(<2 x double> %a, i32 zeroext %b) {

llvm/test/CodeGen/PowerPC/vavg.ll

 ; CHECK-P8-NEXT:    vadduhm 2, 2, 4
 ; CHECK-P8-NEXT:    vsrah 2, 2, 3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: test_v8i16_sign_negative:
 ; CHECK-P7:       # %bb.0: # %entry
 ; CHECK-P7-NEXT:    addis 3, 2, .LCPI6_0@toc@ha
 ; CHECK-P7-NEXT:    vadduhm 2, 2, 3
-; CHECK-P7-NEXT:    vspltish 3, 1
+; CHECK-P7-NEXT:    vspltish 5, 1
 ; CHECK-P7-NEXT:    addi 3, 3, .LCPI6_0@toc@l
 ; CHECK-P7-NEXT:    lxvd2x 0, 0, 3
 ; CHECK-P7-NEXT:    xxswapd 36, 0
 ; CHECK-P7-NEXT:    vadduhm 2, 2, 4
-; CHECK-P7-NEXT:    vsrah 2, 2, 3
+; CHECK-P7-NEXT:    vsrah 2, 2, 5
 ; CHECK-P7-NEXT:    blr
 entry:
   %add = add <8 x i16> %m, <i16 1, i16 1, i16 1, i16 -1, i16 1, i16 1, i16 1, i16 1>
   %add1 = add <8 x i16> %add, %n
   %shr = ashr <8 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   ret <8 x i16> %shr
 }
 

 ; CHECK-P8-NEXT:    vadduwm 2, 2, 4
 ; CHECK-P8-NEXT:    vsraw 2, 2, 3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: test_v4i32_sign_negative:
 ; CHECK-P7:       # %bb.0: # %entry
 ; CHECK-P7-NEXT:    vspltisb 4, -1
 ; CHECK-P7-NEXT:    vadduwm 2, 2, 3
-; CHECK-P7-NEXT:    vspltisw 3, 1
+; CHECK-P7-NEXT:    vspltisw 5, 1
 ; CHECK-P7-NEXT:    vadduwm 2, 2, 4
-; CHECK-P7-NEXT:    vsraw 2, 2, 3
+; CHECK-P7-NEXT:    vsraw 2, 2, 5
 ; CHECK-P7-NEXT:    blr
 entry:
   %add = add <4 x i32> %m, <i32 -1, i32 -1, i32 -1, i32 -1>
   %add1 = add <4 x i32> %add, %n
   %shr = ashr <4 x i32> %add1, <i32 1, i32 1, i32 1, i32 1>
   ret <4 x i32> %shr
 }

llvm/test/CodeGen/PowerPC/vec-icmpeq-v2i64-p7.ll

 ; CHECK-NEXT:    lwz 3, -12(1)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK_LE-LABEL: shufeq:
 ; CHECK_LE:       # %bb.0: # %entry
 ; CHECK_LE-NEXT:    xxswapd 35, 34
 ; CHECK_LE-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
 ; CHECK_LE-NEXT:    addi 3, 3, .LCPI0_0@toc@l
+; CHECK_LE-NEXT:    vcmpequw 2, 2, 3
 ; CHECK_LE-NEXT:    lxvd2x 0, 0, 3
 ; CHECK_LE-NEXT:    addi 3, 1, -16
-; CHECK_LE-NEXT:    vcmpequw 2, 2, 3
-; CHECK_LE-NEXT:    xxswapd 35, 0
-; CHECK_LE-NEXT:    vperm 3, 2, 2, 3
+; CHECK_LE-NEXT:    xxswapd 36, 0
+; CHECK_LE-NEXT:    vperm 3, 2, 2, 4
 ; CHECK_LE-NEXT:    xxland 0, 35, 34
 ; CHECK_LE-NEXT:    xxswapd 0, 0
 ; CHECK_LE-NEXT:    stxvd2x 0, 0, 3
 ; CHECK_LE-NEXT:    ld 3, -16(1)
 ; CHECK_LE-NEXT:    blr
 ;
 ; CHECK_P8LE-LABEL: shufeq:
 ; CHECK_P8LE:       # %bb.0: # %entry

 ; CHECK-NEXT:    lwz 3, -12(1)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK_LE-LABEL: shufne:
 ; CHECK_LE:       # %bb.0: # %entry
 ; CHECK_LE-NEXT:    xxswapd 35, 34
 ; CHECK_LE-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
 ; CHECK_LE-NEXT:    addi 3, 3, .LCPI1_0@toc@l
+; CHECK_LE-NEXT:    vcmpequw 2, 2, 3
 ; CHECK_LE-NEXT:    lxvd2x 0, 0, 3
 ; CHECK_LE-NEXT:    addi 3, 1, -16
-; CHECK_LE-NEXT:    vcmpequw 2, 2, 3
-; CHECK_LE-NEXT:    xxswapd 35, 0
-; CHECK_LE-NEXT:    vperm 3, 2, 2, 3
+; CHECK_LE-NEXT:    xxswapd 36, 0
+; CHECK_LE-NEXT:    vperm 3, 2, 2, 4
 ; CHECK_LE-NEXT:    xxland 0, 35, 34
 ; CHECK_LE-NEXT:    xxswapd 0, 0
 ; CHECK_LE-NEXT:    stxvd2x 0, 0, 3
 ; CHECK_LE-NEXT:    ld 3, -16(1)
 ; CHECK_LE-NEXT:    blr
 ;
 ; CHECK_P8LE-LABEL: shufne:
 ; CHECK_P8LE:       # %bb.0: # %entry

 ; CHECK-NEXT:    blr
 ;
 ; CHECK_LE-LABEL: cmpeq:
 ; CHECK_LE:       # %bb.0: # %entry
 ; CHECK_LE-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
 ; CHECK_LE-NEXT:    vcmpequw 2, 2, 3
 ; CHECK_LE-NEXT:    addi 3, 3, .LCPI2_0@toc@l
 ; CHECK_LE-NEXT:    lxvd2x 0, 0, 3
-; CHECK_LE-NEXT:    xxswapd 35, 0
-; CHECK_LE-NEXT:    vperm 3, 2, 2, 3
+; CHECK_LE-NEXT:    xxswapd 36, 0
+; CHECK_LE-NEXT:    vperm 3, 2, 2, 4
 ; CHECK_LE-NEXT:    xxland 34, 35, 34
 ; CHECK_LE-NEXT:    blr
 ;
 ; CHECK_P8LE-LABEL: cmpeq:
 ; CHECK_P8LE:       # %bb.0: # %entry
 ; CHECK_P8LE-NEXT:    vcmpequd 2, 2, 3
 ; CHECK_P8LE-NEXT:    blr
 entry:

 ; CHECK-NEXT:    xxlor 34, 35, 34
 ; CHECK-NEXT:    blr
 ;
 ; CHECK_LE-LABEL: cmpne:
 ; CHECK_LE:       # %bb.0: # %entry
 ; CHECK_LE-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
 ; CHECK_LE-NEXT:    vcmpequw 2, 2, 3
 ; CHECK_LE-NEXT:    addi 3, 3, .LCPI3_0@toc@l
-; CHECK_LE-NEXT:    lxvd2x 0, 0, 3
-; CHECK_LE-NEXT:    xxswapd 35, 0
 ; CHECK_LE-NEXT:    xxlnor 34, 34, 34
-; CHECK_LE-NEXT:    vperm 3, 2, 2, 3
+; CHECK_LE-NEXT:    lxvd2x 0, 0, 3
+; CHECK_LE-NEXT:    xxswapd 36, 0
+; CHECK_LE-NEXT:    vperm 3, 2, 2, 4
 ; CHECK_LE-NEXT:    xxlor 34, 35, 34
 ; CHECK_LE-NEXT:    blr
 ;
 ; CHECK_P8LE-LABEL: cmpne:
 ; CHECK_P8LE:       # %bb.0: # %entry
 ; CHECK_P8LE-NEXT:    vcmpequd 2, 2, 3
 ; CHECK_P8LE-NEXT:    xxlnor 34, 34, 34
 ; CHECK_P8LE-NEXT:    blr
 entry:
   %cmp = icmp ne <2 x i64> %a, %b
   %sext = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %sext
 }
 

llvm/test/CodeGen/PowerPC/vec-min-max.ll

 ; CHECK-LABEL: getsmaxi64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmaxsd 2, 2, 3
 ; CHECK-NEXT:    blr
 ;
 ; NOP8VEC-LABEL: getsmaxi64:
 ; NOP8VEC:       # %bb.0: # %entry
 ; NOP8VEC-NEXT:    xxswapd 0, 35
-; NOP8VEC-NEXT:    addi 3, 1, -32
-; NOP8VEC-NEXT:    addi 4, 1, -48
 ; NOP8VEC-NEXT:    xxswapd 1, 34
+; NOP8VEC-NEXT:    addi 3, 1, -32
 ; NOP8VEC-NEXT:    stxvd2x 0, 0, 3
-; NOP8VEC-NEXT:    stxvd2x 1, 0, 4
+; NOP8VEC-NEXT:    addi 3, 1, -48
+; NOP8VEC-NEXT:    stxvd2x 1, 0, 3
 ; NOP8VEC-NEXT:    ld 3, -24(1)
 ; NOP8VEC-NEXT:    ld 4, -40(1)
 ; NOP8VEC-NEXT:    ld 6, -48(1)
 ; NOP8VEC-NEXT:    cmpd 4, 3
 ; NOP8VEC-NEXT:    li 3, 0
 ; NOP8VEC-NEXT:    li 4, -1
 ; NOP8VEC-NEXT:    iselgt 5, 4, 3
 ; NOP8VEC-NEXT:    std 5, -8(1)

 ; CHECK-LABEL: getsmini64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vminsd 2, 2, 3
 ; CHECK-NEXT:    blr
 ;
 ; NOP8VEC-LABEL: getsmini64:
 ; NOP8VEC:       # %bb.0: # %entry
 ; NOP8VEC-NEXT:    xxswapd 0, 35
-; NOP8VEC-NEXT:    addi 3, 1, -32
-; NOP8VEC-NEXT:    addi 4, 1, -48
 ; NOP8VEC-NEXT:    xxswapd 1, 34
+; NOP8VEC-NEXT:    addi 3, 1, -32
 ; NOP8VEC-NEXT:    stxvd2x 0, 0, 3
-; NOP8VEC-NEXT:    stxvd2x 1, 0, 4
+; NOP8VEC-NEXT:    addi 3, 1, -48
+; NOP8VEC-NEXT:    stxvd2x 1, 0, 3
 ; NOP8VEC-NEXT:    ld 3, -24(1)
 ; NOP8VEC-NEXT:    ld 4, -40(1)
 ; NOP8VEC-NEXT:    ld 6, -48(1)
 ; NOP8VEC-NEXT:    cmpd 4, 3
 ; NOP8VEC-NEXT:    li 3, 0
 ; NOP8VEC-NEXT:    li 4, -1
 ; NOP8VEC-NEXT:    isellt 5, 4, 3
 ; NOP8VEC-NEXT:    std 5, -8(1)

 ; CHECK-NEXT:    mfvsrd 4, 34
 ; CHECK-NEXT:    mffprd 3, 0
 ; CHECK-NEXT:    blr
 ;
 ; NOP8VEC-LABEL: invalidv1i128:
 ; NOP8VEC:       # %bb.0:
 ; NOP8VEC-NEXT:    cmpld 4, 8
 ; NOP8VEC-NEXT:    cmpd 1, 4, 8
-; NOP8VEC-NEXT:    addi 5, 1, -32
 ; NOP8VEC-NEXT:    crandc 20, 4, 2
 ; NOP8VEC-NEXT:    cmpld 1, 3, 7
 ; NOP8VEC-NEXT:    crand 21, 2, 4
 ; NOP8VEC-NEXT:    cror 20, 21, 20
 ; NOP8VEC-NEXT:    isel 3, 3, 7, 20
 ; NOP8VEC-NEXT:    isel 4, 4, 8, 20
 ; NOP8VEC-NEXT:    std 3, -32(1)
-; NOP8VEC-NEXT:    addi 3, 1, -16
+; NOP8VEC-NEXT:    addi 3, 1, -32
 ; NOP8VEC-NEXT:    std 4, -24(1)
-; NOP8VEC-NEXT:    lxvd2x 0, 0, 5
+; NOP8VEC-NEXT:    lxvd2x 0, 0, 3
+; NOP8VEC-NEXT:    addi 3, 1, -16
 ; NOP8VEC-NEXT:    stxvd2x 0, 0, 3
 ; NOP8VEC-NEXT:    ld 3, -16(1)
 ; NOP8VEC-NEXT:    ld 4, -8(1)
 ; NOP8VEC-NEXT:    blr
 %1 = icmp slt <2 x i128> %v1, %v2
 %2 = select <2 x i1> %1, <2 x i128> %v1, <2 x i128> %v2
 %3 = extractelement <2 x i128> %2, i32 0
 ret i128 %3
 }

llvm/test/CodeGen/PowerPC/vec_cmpd_p7.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; Test the doubleword comparison expansions on Power7
 ;
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr7 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-BE
 
 define <2 x i64> @v2si64_cmp(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
 ; CHECK-LABEL: v2si64_cmp:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
 ; CHECK-NEXT:    vcmpequw 2, 2, 3
 ; CHECK-NEXT:    addi 3, 3, .LCPI0_0@toc@l
 ; CHECK-NEXT:    lxvd2x 0, 0, 3
-; CHECK-NEXT:    xxswapd 35, 0
-; CHECK-NEXT:    vperm 3, 2, 2, 3
+; CHECK-NEXT:    xxswapd 36, 0
+; CHECK-NEXT:    vperm 3, 2, 2, 4
 ; CHECK-NEXT:    xxland 34, 35, 34
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: v2si64_cmp:
 ; CHECK-BE:       # %bb.0:
 ; CHECK-BE-NEXT:    vcmpequw 2, 2, 3
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI0_0@toc@l
 ; CHECK-BE-NEXT:    lxvw4x 35, 0, 3
 ; CHECK-BE-NEXT:    vperm 3, 2, 2, 3
 ; CHECK-BE-NEXT:    xxland 34, 35, 34
 ; CHECK-BE-NEXT:    blr
   %cmp = icmp eq <2 x i64> %x, %y
   %result = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %result
 }
 
 ; Greater than signed
 define <2 x i64> @v2si64_cmp_gt(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
 ; CHECK-LABEL: v2si64_cmp_gt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xxswapd 0, 35
-; CHECK-NEXT:    addi 3, 1, -32
-; CHECK-NEXT:    addi 4, 1, -48
 ; CHECK-NEXT:    xxswapd 1, 34
+; CHECK-NEXT:    addi 3, 1, -32
 ; CHECK-NEXT:    stxvd2x 0, 0, 3
-; CHECK-NEXT:    stxvd2x 1, 0, 4
+; CHECK-NEXT:    addi 3, 1, -48
+; CHECK-NEXT:    stxvd2x 1, 0, 3
 ; CHECK-NEXT:    ld 3, -24(1)
 ; CHECK-NEXT:    ld 4, -40(1)
 ; CHECK-NEXT:    ld 6, -48(1)
 ; CHECK-NEXT:    cmpd 4, 3
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    li 4, -1
 ; CHECK-NEXT:    iselgt 5, 4, 3
 ; CHECK-NEXT:    std 5, -8(1)
 ; CHECK-NEXT:    ld 5, -32(1)
 ; CHECK-NEXT:    cmpd 6, 5
 ; CHECK-NEXT:    iselgt 3, 4, 3
 ; CHECK-NEXT:    std 3, -16(1)
 ; CHECK-NEXT:    addi 3, 1, -16
 ; CHECK-NEXT:    lxvd2x 0, 0, 3
 ; CHECK-NEXT:    xxswapd 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: v2si64_cmp_gt:
 ; CHECK-BE:       # %bb.0:
 ; CHECK-BE-NEXT:    addi 3, 1, -32
-; CHECK-BE-NEXT:    addi 4, 1, -48
 ; CHECK-BE-NEXT:    stxvd2x 35, 0, 3
-; CHECK-BE-NEXT:    stxvd2x 34, 0, 4
+; CHECK-BE-NEXT:    addi 3, 1, -48
+; CHECK-BE-NEXT:    stxvd2x 34, 0, 3
 ; CHECK-BE-NEXT:    ld 3, -24(1)
 ; CHECK-BE-NEXT:    ld 4, -40(1)
 ; CHECK-BE-NEXT:    ld 6, -48(1)
 ; CHECK-BE-NEXT:    cmpd 4, 3
 ; CHECK-BE-NEXT:    li 3, 0
 ; CHECK-BE-NEXT:    li 4, -1
 ; CHECK-BE-NEXT:    iselgt 5, 4, 3
 ; CHECK-BE-NEXT:    std 5, -8(1)
; CHECK-BE-NEXT:    blr
   ret <2 x i64> %result
 }
 
 ; Greater than unsigned
 define <2 x i64> @v2ui64_cmp_gt(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
 ; CHECK-LABEL: v2ui64_cmp_gt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xxswapd 0, 35
-; CHECK-NEXT:    addi 3, 1, -32
-; CHECK-NEXT:    addi 4, 1, -48
 ; CHECK-NEXT:    xxswapd 1, 34
+; CHECK-NEXT:    addi 3, 1, -32
 ; CHECK-NEXT:    stxvd2x 0, 0, 3
-; CHECK-NEXT:    stxvd2x 1, 0, 4
+; CHECK-NEXT:    addi 3, 1, -48
+; CHECK-NEXT:    stxvd2x 1, 0, 3
 ; CHECK-NEXT:    ld 3, -24(1)
 ; CHECK-NEXT:    ld 4, -40(1)
 ; CHECK-NEXT:    ld 6, -48(1)
 ; CHECK-NEXT:    cmpld 4, 3
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    li 4, -1
 ; CHECK-NEXT:    iselgt 5, 4, 3
 ; CHECK-NEXT:    std 5, -8(1)
 ; CHECK-NEXT:    ld 5, -32(1)
 ; CHECK-NEXT:    cmpld 6, 5
 ; CHECK-NEXT:    iselgt 3, 4, 3
 ; CHECK-NEXT:    std 3, -16(1)
 ; CHECK-NEXT:    addi 3, 1, -16
 ; CHECK-NEXT:    lxvd2x 0, 0, 3
 ; CHECK-NEXT:    xxswapd 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: v2ui64_cmp_gt:
 ; CHECK-BE:       # %bb.0:
 ; CHECK-BE-NEXT:    addi 3, 1, -32
-; CHECK-BE-NEXT:    addi 4, 1, -48
 ; CHECK-BE-NEXT:    stxvd2x 35, 0, 3
-; CHECK-BE-NEXT:    stxvd2x 34, 0, 4
+; CHECK-BE-NEXT:    addi 3, 1, -48
+; CHECK-BE-NEXT:    stxvd2x 34, 0, 3
 ; CHECK-BE-NEXT:    ld 3, -24(1)
 ; CHECK-BE-NEXT:    ld 4, -40(1)
 ; CHECK-BE-NEXT:    ld 6, -48(1)
 ; CHECK-BE-NEXT:    cmpld 4, 3
 ; CHECK-BE-NEXT:    li 3, 0
 ; CHECK-BE-NEXT:    li 4, -1
 ; CHECK-BE-NEXT:    iselgt 5, 4, 3
 ; CHECK-BE-NEXT:    std 5, -8(1)
; CHECK-BE-NEXT:    blr
   %tmp = tail call i32 @llvm.ppc.altivec.vcmpequd.p(i32 2, <2 x i64> %x, <2 x i64> %y)
   ret i32 %tmp
 }
 
 define i32 @test_vcmpgtsd_p(<2 x i64> %x, <2 x i64> %y) {
 ; CHECK-LABEL: test_vcmpgtsd_p:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vcmpgtuw 4, 2, 3
-; CHECK-NEXT:    vcmpequw 5, 2, 3
+; CHECK-NEXT:    xxsldwi 0, 36, 36, 1
+; CHECK-NEXT:    vcmpequw 4, 2, 3
 ; CHECK-NEXT:    vcmpgtsw 2, 2, 3
 ; CHECK-NEXT:    xxlxor 35, 35, 35
-; CHECK-NEXT:    xxsldwi 0, 36, 36, 1
-; CHECK-NEXT:    xxland 0, 0, 37
+; CHECK-NEXT:    xxland 0, 0, 36
 ; CHECK-NEXT:    xxlor 0, 34, 0
 ; CHECK-NEXT:    xxspltw 1, 0, 2
 ; CHECK-NEXT:    xxspltw 0, 0, 0
 ; CHECK-NEXT:    xxmrghd 34, 0, 1
 ; CHECK-NEXT:    vcmpgtub. 2, 2, 3
 ; CHECK-NEXT:    mfocrf 3, 2
 ; CHECK-NEXT:    rlwinm 3, 3, 25, 31, 31
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_vcmpgtsd_p:
 ; CHECK-BE:       # %bb.0:
 ; CHECK-BE-NEXT:    vcmpgtuw 4, 2, 3
-; CHECK-BE-NEXT:    vcmpequw 5, 2, 3
+; CHECK-BE-NEXT:    xxsldwi 0, 36, 36, 1
+; CHECK-BE-NEXT:    vcmpequw 4, 2, 3
 ; CHECK-BE-NEXT:    vcmpgtsw 2, 2, 3
 ; CHECK-BE-NEXT:    xxlxor 35, 35, 35
-; CHECK-BE-NEXT:    xxsldwi 0, 36, 36, 1
-; CHECK-BE-NEXT:    xxland 0, 0, 37
+; CHECK-BE-NEXT:    xxland 0, 0, 36
 ; CHECK-BE-NEXT:    xxlor 0, 34, 0
 ; CHECK-BE-NEXT:    xxspltw 1, 0, 2
 ; CHECK-BE-NEXT:    xxspltw 0, 0, 0
 ; CHECK-BE-NEXT:    xxmrghd 34, 0, 1
 ; CHECK-BE-NEXT:    vcmpgtub. 2, 2, 3
 ; CHECK-BE-NEXT:    mfocrf 3, 2
 ; CHECK-BE-NEXT:    rlwinm 3, 3, 25, 31, 31
 ; CHECK-BE-NEXT:    blr

llvm/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll

 ; CHECK-NEXT:    vpkudum 2, 2, 3
 ; CHECK-NEXT:    stxvw4x 34, 0, 3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-PWR7-LABEL: VPKUDUM:
 ; CHECK-PWR7:       # %bb.0: # %entry
 ; CHECK-PWR7-NEXT:    addis 5, 2, .LCPI1_0@toc@ha
 ; CHECK-PWR7-NEXT:    lxvw4x 34, 0, 4
+; CHECK-PWR7-NEXT:    addi 5, 5, .LCPI1_0@toc@l
 ; CHECK-PWR7-NEXT:    lxvw4x 35, 0, 3
-; CHECK-PWR7-NEXT:    addi 4, 5, .LCPI1_0@toc@l
-; CHECK-PWR7-NEXT:    lxvw4x 36, 0, 4
+; CHECK-PWR7-NEXT:    lxvw4x 36, 0, 5
 ; CHECK-PWR7-NEXT:    vperm 2, 3, 2, 4
 ; CHECK-PWR7-NEXT:    stxvw4x 34, 0, 3
 ; CHECK-PWR7-NEXT:    blr
 ;
 ; CHECK-PWR7-AIX-LABEL: VPKUDUM:
 ; CHECK-PWR7-AIX:       # %bb.0: # %entry
 ; CHECK-PWR7-AIX-NEXT:    ld 5, L..C1(2) # %const.0
 ; CHECK-PWR7-AIX-NEXT:    lxvw4x 34, 0, 4

llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll

 ; PWR6-NEXT:    vand 2, 2, 4
 ; PWR6-NEXT:    vcmpgtub 2, 2, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_2_v16i8:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisb 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI2_0@toc@l
 ; PWR7-NEXT:    vspltisb 4, 2
-; PWR7-NEXT:    lxvw4x 0, 0, 3
-; PWR7-NEXT:    addis 3, 2, .LCPI2_1@toc@ha
+; PWR7-NEXT:    addi 3, 3, .LCPI2_0@toc@l
 ; PWR7-NEXT:    vspltisb 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
 ; PWR7-NEXT:    vsrb 3, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
+; PWR7-NEXT:    addis 3, 2, .LCPI2_1@toc@ha
 ; PWR7-NEXT:    addi 3, 3, .LCPI2_1@toc@l
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsububm 2, 2, 3
-; PWR7-NEXT:    vsrb 3, 2, 4
+; PWR7-NEXT:    xxland 35, 34, 0
+; PWR7-NEXT:    vsrb 2, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    vaddubm 2, 2, 3
+; PWR7-NEXT:    vaddubm 2, 3, 2
 ; PWR7-NEXT:    vsrb 3, 2, 5
-; PWR7-NEXT:    vspltisb 5, 15
 ; PWR7-NEXT:    vaddubm 2, 2, 3
-; PWR7-NEXT:    xxland 34, 34, 37
+; PWR7-NEXT:    xxland 34, 34, 32
 ; PWR7-NEXT:    vcmpgtub 2, 2, 4
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_2_v16i8:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisb 3, 2
 ; PWR8-NEXT:    vpopcntb 2, 2
 ; PWR8-NEXT:    vcmpgtub 2, 2, 3

 ; PWR6-NEXT:    vand 2, 2, 4
 ; PWR6-NEXT:    vcmpgtub 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_3_v16i8:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisb 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI3_0@toc@l
 ; PWR7-NEXT:    vspltisb 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI3_0@toc@l
+; PWR7-NEXT:    vspltisb 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 3
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI3_1@toc@ha
-; PWR7-NEXT:    vsrb 3, 2, 3
 ; PWR7-NEXT:    addi 3, 3, .LCPI3_1@toc@l
+; PWR7-NEXT:    vsrb 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsububm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrb 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisb 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vaddubm 2, 2, 3
-; PWR7-NEXT:    vsrb 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 15
+; PWR7-NEXT:    vsrb 3, 2, 5
 ; PWR7-NEXT:    vaddubm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 3
-; PWR7-NEXT:    xxland 34, 34, 36
-; PWR7-NEXT:    vcmpgtub 2, 3, 2
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vcmpgtub 2, 1, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_3_v16i8:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisb 3, 3
 ; PWR8-NEXT:    vpopcntb 2, 2
 ; PWR8-NEXT:    vcmpgtub 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vand 2, 2, 4
 ; PWR6-NEXT:    vcmpgtub 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_3_v16i8:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisb 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI4_0@toc@l
 ; PWR7-NEXT:    vspltisb 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI4_0@toc@l
+; PWR7-NEXT:    vspltisb 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 3
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI4_1@toc@ha
-; PWR7-NEXT:    vsrb 3, 2, 3
 ; PWR7-NEXT:    addi 3, 3, .LCPI4_1@toc@l
+; PWR7-NEXT:    vsrb 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsububm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrb 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisb 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vaddubm 2, 2, 3
-; PWR7-NEXT:    vsrb 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 15
+; PWR7-NEXT:    vsrb 3, 2, 5
 ; PWR7-NEXT:    vaddubm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 3
-; PWR7-NEXT:    xxland 34, 34, 36
-; PWR7-NEXT:    vcmpgtub 2, 2, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vcmpgtub 2, 2, 1
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_3_v16i8:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisb 3, 3
 ; PWR8-NEXT:    vpopcntb 2, 2
 ; PWR8-NEXT:    vcmpgtub 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vand 2, 2, 5
 ; PWR6-NEXT:    vcmpgtub 2, 4, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_4_v16i8:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisb 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI5_0@toc@l
 ; PWR7-NEXT:    vspltisb 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI5_0@toc@l
+; PWR7-NEXT:    vspltisb 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vsrb 3, 2, 3
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI5_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 15
-; PWR7-NEXT:    vsrb 3, 2, 3
 ; PWR7-NEXT:    addi 3, 3, .LCPI5_1@toc@l
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsububm 2, 2, 3
 ; PWR7-NEXT:    vsrb 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisb 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vaddubm 2, 2, 3
-; PWR7-NEXT:    vsrb 3, 2, 4
+; PWR7-NEXT:    vsrb 3, 2, 5
 ; PWR7-NEXT:    vaddubm 2, 2, 3
-; PWR7-NEXT:    xxland 34, 34, 37
-; PWR7-NEXT:    vcmpgtub 2, 4, 2
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vcmpgtub 2, 5, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_4_v16i8:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisb 3, 4
 ; PWR8-NEXT:    vpopcntb 2, 2
 ; PWR8-NEXT:    vcmpgtub 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vand 2, 2, 5
 ; PWR6-NEXT:    vcmpgtub 2, 2, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_4_v16i8:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisb 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI6_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI6_0@toc@l
 ; PWR7-NEXT:    vspltisb 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI6_0@toc@l
+; PWR7-NEXT:    vspltisb 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vsrb 3, 2, 3
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI6_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 15
-; PWR7-NEXT:    vsrb 3, 2, 3
 ; PWR7-NEXT:    addi 3, 3, .LCPI6_1@toc@l
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsububm 2, 2, 3
 ; PWR7-NEXT:    vsrb 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisb 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vaddubm 2, 2, 3
-; PWR7-NEXT:    vsrb 3, 2, 4
+; PWR7-NEXT:    vsrb 3, 2, 5
 ; PWR7-NEXT:    vaddubm 2, 2, 3
-; PWR7-NEXT:    xxland 34, 34, 37
-; PWR7-NEXT:    vcmpgtub 2, 2, 4
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vcmpgtub 2, 2, 5
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_4_v16i8:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisb 3, 4
 ; PWR8-NEXT:    vpopcntb 2, 2
 ; PWR8-NEXT:    vcmpgtub 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vand 2, 2, 4
 ; PWR6-NEXT:    vcmpgtub 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_5_v16i8:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisb 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI7_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI7_0@toc@l
 ; PWR7-NEXT:    vspltisb 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI7_0@toc@l
+; PWR7-NEXT:    vspltisb 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 5
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI7_1@toc@ha
-; PWR7-NEXT:    vsrb 3, 2, 3
 ; PWR7-NEXT:    addi 3, 3, .LCPI7_1@toc@l
+; PWR7-NEXT:    vsrb 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsububm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrb 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisb 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vaddubm 2, 2, 3
-; PWR7-NEXT:    vsrb 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 15
+; PWR7-NEXT:    vsrb 3, 2, 5
 ; PWR7-NEXT:    vaddubm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 5
-; PWR7-NEXT:    xxland 34, 34, 36
-; PWR7-NEXT:    vcmpgtub 2, 3, 2
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vcmpgtub 2, 1, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_5_v16i8:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisb 3, 5
 ; PWR8-NEXT:    vpopcntb 2, 2
 ; PWR8-NEXT:    vcmpgtub 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vand 2, 2, 4
 ; PWR6-NEXT:    vcmpgtub 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_5_v16i8:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisb 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI8_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI8_0@toc@l
 ; PWR7-NEXT:    vspltisb 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI8_0@toc@l
+; PWR7-NEXT:    vspltisb 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 5
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI8_1@toc@ha
-; PWR7-NEXT:    vsrb 3, 2, 3
 ; PWR7-NEXT:    addi 3, 3, .LCPI8_1@toc@l
+; PWR7-NEXT:    vsrb 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsububm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrb 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisb 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vaddubm 2, 2, 3
-; PWR7-NEXT:    vsrb 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 15
+; PWR7-NEXT:    vsrb 3, 2, 5
 ; PWR7-NEXT:    vaddubm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 5
-; PWR7-NEXT:    xxland 34, 34, 36
-; PWR7-NEXT:    vcmpgtub 2, 2, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vcmpgtub 2, 2, 1
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_5_v16i8:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisb 3, 5
 ; PWR8-NEXT:    vpopcntb 2, 2
 ; PWR8-NEXT:    vcmpgtub 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vand 2, 2, 4
 ; PWR6-NEXT:    vcmpgtub 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_6_v16i8:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisb 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI9_0@toc@l
 ; PWR7-NEXT:    vspltisb 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI9_0@toc@l
+; PWR7-NEXT:    vspltisb 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 6
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI9_1@toc@ha
-; PWR7-NEXT:    vsrb 3, 2, 3
 ; PWR7-NEXT:    addi 3, 3, .LCPI9_1@toc@l
+; PWR7-NEXT:    vsrb 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsububm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrb 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisb 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vaddubm 2, 2, 3
-; PWR7-NEXT:    vsrb 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 15
+; PWR7-NEXT:    vsrb 3, 2, 5
 ; PWR7-NEXT:    vaddubm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 6
-; PWR7-NEXT:    xxland 34, 34, 36
-; PWR7-NEXT:    vcmpgtub 2, 3, 2
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vcmpgtub 2, 1, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_6_v16i8:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisb 3, 6
 ; PWR8-NEXT:    vpopcntb 2, 2
 ; PWR8-NEXT:    vcmpgtub 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vand 2, 2, 4
 ; PWR6-NEXT:    vcmpgtub 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_6_v16i8:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisb 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI10_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI10_0@toc@l
 ; PWR7-NEXT:    vspltisb 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI10_0@toc@l
+; PWR7-NEXT:    vspltisb 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 6
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI10_1@toc@ha
-; PWR7-NEXT:    vsrb 3, 2, 3
 ; PWR7-NEXT:    addi 3, 3, .LCPI10_1@toc@l
+; PWR7-NEXT:    vsrb 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsububm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrb 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisb 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vaddubm 2, 2, 3
-; PWR7-NEXT:    vsrb 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 15
+; PWR7-NEXT:    vsrb 3, 2, 5
 ; PWR7-NEXT:    vaddubm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 6
-; PWR7-NEXT:    xxland 34, 34, 36
-; PWR7-NEXT:    vcmpgtub 2, 2, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vcmpgtub 2, 2, 1
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_6_v16i8:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisb 3, 6
 ; PWR8-NEXT:    vpopcntb 2, 2
 ; PWR8-NEXT:    vcmpgtub 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vand 2, 2, 4
 ; PWR6-NEXT:    vcmpgtub 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_7_v16i8:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisb 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI11_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI11_0@toc@l
 ; PWR7-NEXT:    vspltisb 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI11_0@toc@l
+; PWR7-NEXT:    vspltisb 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 7
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI11_1@toc@ha
-; PWR7-NEXT:    vsrb 3, 2, 3
 ; PWR7-NEXT:    addi 3, 3, .LCPI11_1@toc@l
+; PWR7-NEXT:    vsrb 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsububm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrb 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisb 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vaddubm 2, 2, 3
-; PWR7-NEXT:    vsrb 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 15
+; PWR7-NEXT:    vsrb 3, 2, 5
 ; PWR7-NEXT:    vaddubm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 7
-; PWR7-NEXT:    xxland 34, 34, 36
-; PWR7-NEXT:    vcmpgtub 2, 3, 2
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vcmpgtub 2, 1, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_7_v16i8:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisb 3, 7
 ; PWR8-NEXT:    vpopcntb 2, 2
 ; PWR8-NEXT:    vcmpgtub 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vsrh 2, 2, 3
 ; PWR6-NEXT:    vcmpgtuh 2, 2, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_2_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI14_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI14_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI14_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI14_1@toc@ha
-; PWR7-NEXT:    vspltish 5, 4
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI14_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
+; PWR7-NEXT:    xxland 35, 34, 0
+; PWR7-NEXT:    vsrh 2, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    vadduhm 2, 2, 3
+; PWR7-NEXT:    vadduhm 2, 3, 2
 ; PWR7-NEXT:    vsrh 3, 2, 5
-; PWR7-NEXT:    vxor 5, 5, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
+; PWR7-NEXT:    vxor 3, 3, 3
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 5
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
 ; PWR7-NEXT:    vcmpgtuh 2, 2, 4
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_2_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 2
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 2, 3

 ; PWR6-NEXT:    vspltish 3, 3
 ; PWR6-NEXT:    vcmpgtuh 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_3_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI15_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI15_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI15_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI15_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 15
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI15_1@toc@l
+; PWR7-NEXT:    vspltish 7, 3
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
 ; PWR7-NEXT:    vsrh 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltish 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
-; PWR7-NEXT:    vxor 4, 4, 4
+; PWR7-NEXT:    vsrh 3, 2, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
-; PWR7-NEXT:    xxland 34, 34, 37
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 4
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
-; PWR7-NEXT:    vspltish 3, 3
-; PWR7-NEXT:    vcmpgtuh 2, 3, 2
+; PWR7-NEXT:    vxor 3, 3, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
+; PWR7-NEXT:    vcmpgtuh 2, 7, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_3_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 3
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltish 3, 3
 ; PWR6-NEXT:    vcmpgtuh 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_3_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI16_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI16_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI16_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI16_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 15
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI16_1@toc@l
+; PWR7-NEXT:    vspltish 7, 3
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
 ; PWR7-NEXT:    vsrh 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltish 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
-; PWR7-NEXT:    vxor 4, 4, 4
+; PWR7-NEXT:    vsrh 3, 2, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
-; PWR7-NEXT:    xxland 34, 34, 37
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 4
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
-; PWR7-NEXT:    vspltish 3, 3
-; PWR7-NEXT:    vcmpgtuh 2, 2, 3
+; PWR7-NEXT:    vxor 3, 3, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
+; PWR7-NEXT:    vcmpgtuh 2, 2, 7
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_3_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 3
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vsrh 2, 2, 3
 ; PWR6-NEXT:    vcmpgtuh 2, 5, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_4_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI17_0@toc@ha
-; PWR7-NEXT:    vxor 5, 5, 5
-; PWR7-NEXT:    addi 3, 3, .LCPI17_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI17_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI17_1@toc@ha
-; PWR7-NEXT:    vspltisb 0, 15
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI17_1@toc@l
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
 ; PWR7-NEXT:    vsrh 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltish 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
+; PWR7-NEXT:    vsrh 3, 2, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
+; PWR7-NEXT:    vxor 3, 3, 3
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 5
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
-; PWR7-NEXT:    vcmpgtuh 2, 4, 2
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
+; PWR7-NEXT:    vcmpgtuh 2, 5, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_4_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 4
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vsrh 2, 2, 3
 ; PWR6-NEXT:    vcmpgtuh 2, 2, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_4_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI18_0@toc@ha
-; PWR7-NEXT:    vxor 5, 5, 5
-; PWR7-NEXT:    addi 3, 3, .LCPI18_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI18_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI18_1@toc@ha
-; PWR7-NEXT:    vspltisb 0, 15
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI18_1@toc@l
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
 ; PWR7-NEXT:    vsrh 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltish 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
+; PWR7-NEXT:    vsrh 3, 2, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
+; PWR7-NEXT:    vxor 3, 3, 3
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 5
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
-; PWR7-NEXT:    vcmpgtuh 2, 2, 4
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
+; PWR7-NEXT:    vcmpgtuh 2, 2, 5
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_4_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 4
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltish 3, 5
 ; PWR6-NEXT:    vcmpgtuh 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_5_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI19_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI19_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI19_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI19_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 15
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI19_1@toc@l
+; PWR7-NEXT:    vspltish 7, 5
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
 ; PWR7-NEXT:    vsrh 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltish 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
-; PWR7-NEXT:    vxor 4, 4, 4
+; PWR7-NEXT:    vsrh 3, 2, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
-; PWR7-NEXT:    xxland 34, 34, 37
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 4
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
-; PWR7-NEXT:    vspltish 3, 5
-; PWR7-NEXT:    vcmpgtuh 2, 3, 2
+; PWR7-NEXT:    vxor 3, 3, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
+; PWR7-NEXT:    vcmpgtuh 2, 7, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_5_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 5
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltish 3, 5
 ; PWR6-NEXT:    vcmpgtuh 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_5_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI20_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI20_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI20_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI20_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 15
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI20_1@toc@l
+; PWR7-NEXT:    vspltish 7, 5
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
 ; PWR7-NEXT:    vsrh 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltish 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
-; PWR7-NEXT:    vxor 4, 4, 4
+; PWR7-NEXT:    vsrh 3, 2, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
-; PWR7-NEXT:    xxland 34, 34, 37
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 4
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
-; PWR7-NEXT:    vspltish 3, 5
-; PWR7-NEXT:    vcmpgtuh 2, 2, 3
+; PWR7-NEXT:    vxor 3, 3, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
+; PWR7-NEXT:    vcmpgtuh 2, 2, 7
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_5_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 5
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltish 3, 6
 ; PWR6-NEXT:    vcmpgtuh 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_6_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI21_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI21_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI21_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI21_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 15
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI21_1@toc@l
+; PWR7-NEXT:    vspltish 7, 6
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
 ; PWR7-NEXT:    vsrh 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltish 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
-; PWR7-NEXT:    vxor 4, 4, 4
+; PWR7-NEXT:    vsrh 3, 2, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
-; PWR7-NEXT:    xxland 34, 34, 37
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 4
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
-; PWR7-NEXT:    vspltish 3, 6
-; PWR7-NEXT:    vcmpgtuh 2, 3, 2
+; PWR7-NEXT:    vxor 3, 3, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
+; PWR7-NEXT:    vcmpgtuh 2, 7, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_6_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 6
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltish 3, 6
 ; PWR6-NEXT:    vcmpgtuh 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_6_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI22_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI22_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI22_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI22_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 15
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI22_1@toc@l
+; PWR7-NEXT:    vspltish 7, 6
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
 ; PWR7-NEXT:    vsrh 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltish 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
-; PWR7-NEXT:    vxor 4, 4, 4
+; PWR7-NEXT:    vsrh 3, 2, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
-; PWR7-NEXT:    xxland 34, 34, 37
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 4
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
-; PWR7-NEXT:    vspltish 3, 6
-; PWR7-NEXT:    vcmpgtuh 2, 2, 3
+; PWR7-NEXT:    vxor 3, 3, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
+; PWR7-NEXT:    vcmpgtuh 2, 2, 7
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_6_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 6
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltish 3, 7
 ; PWR6-NEXT:    vcmpgtuh 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_7_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI23_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI23_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI23_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI23_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 15
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI23_1@toc@l
+; PWR7-NEXT:    vspltish 7, 7
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
 ; PWR7-NEXT:    vsrh 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltish 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
-; PWR7-NEXT:    vxor 4, 4, 4
+; PWR7-NEXT:    vsrh 3, 2, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
-; PWR7-NEXT:    xxland 34, 34, 37
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 4
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
-; PWR7-NEXT:    vspltish 3, 7
-; PWR7-NEXT:    vcmpgtuh 2, 3, 2
+; PWR7-NEXT:    vxor 3, 3, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
+; PWR7-NEXT:    vcmpgtuh 2, 7, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_7_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 7
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltish 3, 7
 ; PWR6-NEXT:    vcmpgtuh 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_7_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI24_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI24_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI24_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI24_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 15
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI24_1@toc@l
+; PWR7-NEXT:    vspltish 7, 7
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
 ; PWR7-NEXT:    vsrh 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltish 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
-; PWR7-NEXT:    vxor 4, 4, 4
+; PWR7-NEXT:    vsrh 3, 2, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
-; PWR7-NEXT:    xxland 34, 34, 37
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 4
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
-; PWR7-NEXT:    vspltish 3, 7
-; PWR7-NEXT:    vcmpgtuh 2, 2, 3
+; PWR7-NEXT:    vxor 3, 3, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
+; PWR7-NEXT:    vcmpgtuh 2, 2, 7
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_7_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 7
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vsrh 2, 2, 3
 ; PWR6-NEXT:    vcmpgtuh 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_8_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI25_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI25_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI25_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI25_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 15
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI25_1@toc@l
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
 ; PWR7-NEXT:    vsrh 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltish 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
-; PWR7-NEXT:    vxor 4, 4, 4
+; PWR7-NEXT:    vsrh 3, 2, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
-; PWR7-NEXT:    xxland 34, 34, 37
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 4
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
-; PWR7-NEXT:    vcmpgtuh 2, 3, 2
+; PWR7-NEXT:    vxor 3, 3, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
+; PWR7-NEXT:    vcmpgtuh 2, 6, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_8_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 8
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vsrh 2, 2, 3
 ; PWR6-NEXT:    vcmpgtuh 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_8_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI26_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI26_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI26_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI26_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 15
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI26_1@toc@l
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
 ; PWR7-NEXT:    vsrh 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltish 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
-; PWR7-NEXT:    vxor 4, 4, 4
+; PWR7-NEXT:    vsrh 3, 2, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
-; PWR7-NEXT:    xxland 34, 34, 37
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 4
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
-; PWR7-NEXT:    vcmpgtuh 2, 2, 3
+; PWR7-NEXT:    vxor 3, 3, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
+; PWR7-NEXT:    vcmpgtuh 2, 2, 6
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_8_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 8
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltish 3, 9
 ; PWR6-NEXT:    vcmpgtuh 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_9_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI27_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI27_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI27_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI27_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 15
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI27_1@toc@l
+; PWR7-NEXT:    vspltish 7, 9
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
 ; PWR7-NEXT:    vsrh 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltish 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
-; PWR7-NEXT:    vxor 4, 4, 4
+; PWR7-NEXT:    vsrh 3, 2, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
-; PWR7-NEXT:    xxland 34, 34, 37
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 4
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
-; PWR7-NEXT:    vspltish 3, 9
-; PWR7-NEXT:    vcmpgtuh 2, 3, 2
+; PWR7-NEXT:    vxor 3, 3, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
+; PWR7-NEXT:    vcmpgtuh 2, 7, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_9_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 9
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltish 3, 9
 ; PWR6-NEXT:    vcmpgtuh 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_9_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI28_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI28_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI28_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI28_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 15
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI28_1@toc@l
+; PWR7-NEXT:    vspltish 7, 9
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
 ; PWR7-NEXT:    vsrh 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltish 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
-; PWR7-NEXT:    vxor 4, 4, 4
+; PWR7-NEXT:    vsrh 3, 2, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
-; PWR7-NEXT:    xxland 34, 34, 37
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 4
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
-; PWR7-NEXT:    vspltish 3, 9
-; PWR7-NEXT:    vcmpgtuh 2, 2, 3
+; PWR7-NEXT:    vxor 3, 3, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
+; PWR7-NEXT:    vcmpgtuh 2, 2, 7
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_9_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 9
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltish 3, 10
 ; PWR6-NEXT:    vcmpgtuh 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_10_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI29_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI29_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI29_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI29_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 15
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI29_1@toc@l
+; PWR7-NEXT:    vspltish 7, 10
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
 ; PWR7-NEXT:    vsrh 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltish 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
-; PWR7-NEXT:    vxor 4, 4, 4
+; PWR7-NEXT:    vsrh 3, 2, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
-; PWR7-NEXT:    xxland 34, 34, 37
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 4
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
-; PWR7-NEXT:    vspltish 3, 10
-; PWR7-NEXT:    vcmpgtuh 2, 3, 2
+; PWR7-NEXT:    vxor 3, 3, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
+; PWR7-NEXT:    vcmpgtuh 2, 7, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_10_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 10
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltish 3, 10
 ; PWR6-NEXT:    vcmpgtuh 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_10_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI30_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI30_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI30_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI30_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 15
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI30_1@toc@l
+; PWR7-NEXT:    vspltish 7, 10
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
 ; PWR7-NEXT:    vsrh 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltish 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
-; PWR7-NEXT:    vxor 4, 4, 4
+; PWR7-NEXT:    vsrh 3, 2, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
-; PWR7-NEXT:    xxland 34, 34, 37
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 4
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
-; PWR7-NEXT:    vspltish 3, 10
-; PWR7-NEXT:    vcmpgtuh 2, 2, 3
+; PWR7-NEXT:    vxor 3, 3, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
+; PWR7-NEXT:    vcmpgtuh 2, 2, 7
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_10_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 10
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltish 3, 11
 ; PWR6-NEXT:    vcmpgtuh 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_11_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI31_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI31_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI31_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI31_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 15
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI31_1@toc@l
+; PWR7-NEXT:    vspltish 7, 11
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
 ; PWR7-NEXT:    vsrh 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltish 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
-; PWR7-NEXT:    vxor 4, 4, 4
+; PWR7-NEXT:    vsrh 3, 2, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
-; PWR7-NEXT:    xxland 34, 34, 37
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 4
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
-; PWR7-NEXT:    vspltish 3, 11
-; PWR7-NEXT:    vcmpgtuh 2, 3, 2
+; PWR7-NEXT:    vxor 3, 3, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
+; PWR7-NEXT:    vcmpgtuh 2, 7, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_11_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 11
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltish 3, 11
 ; PWR6-NEXT:    vcmpgtuh 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_11_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI32_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI32_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI32_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI32_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 15
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI32_1@toc@l
+; PWR7-NEXT:    vspltish 7, 11
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
 ; PWR7-NEXT:    vsrh 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltish 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
-; PWR7-NEXT:    vxor 4, 4, 4
+; PWR7-NEXT:    vsrh 3, 2, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
-; PWR7-NEXT:    xxland 34, 34, 37
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 4
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
-; PWR7-NEXT:    vspltish 3, 11
-; PWR7-NEXT:    vcmpgtuh 2, 2, 3
+; PWR7-NEXT:    vxor 3, 3, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
+; PWR7-NEXT:    vcmpgtuh 2, 2, 7
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_11_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 11
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltish 3, 12
 ; PWR6-NEXT:    vcmpgtuh 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_12_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI33_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI33_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI33_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI33_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 15
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI33_1@toc@l
+; PWR7-NEXT:    vspltish 7, 12
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
 ; PWR7-NEXT:    vsrh 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltish 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
-; PWR7-NEXT:    vxor 4, 4, 4
+; PWR7-NEXT:    vsrh 3, 2, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
-; PWR7-NEXT:    xxland 34, 34, 37
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 4
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
-; PWR7-NEXT:    vspltish 3, 12
-; PWR7-NEXT:    vcmpgtuh 2, 3, 2
+; PWR7-NEXT:    vxor 3, 3, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
+; PWR7-NEXT:    vcmpgtuh 2, 7, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_12_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 12
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltish 3, 12
 ; PWR6-NEXT:    vcmpgtuh 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_12_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI34_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI34_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI34_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI34_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 15
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI34_1@toc@l
+; PWR7-NEXT:    vspltish 7, 12
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
 ; PWR7-NEXT:    vsrh 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltish 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
-; PWR7-NEXT:    vxor 4, 4, 4
+; PWR7-NEXT:    vsrh 3, 2, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
-; PWR7-NEXT:    xxland 34, 34, 37
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 4
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
-; PWR7-NEXT:    vspltish 3, 12
-; PWR7-NEXT:    vcmpgtuh 2, 2, 3
+; PWR7-NEXT:    vxor 3, 3, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
+; PWR7-NEXT:    vcmpgtuh 2, 2, 7
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_12_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 12
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltish 3, 13
 ; PWR6-NEXT:    vcmpgtuh 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_13_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI35_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI35_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI35_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI35_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 15
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI35_1@toc@l
+; PWR7-NEXT:    vspltish 7, 13
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
 ; PWR7-NEXT:    vsrh 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltish 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
-; PWR7-NEXT:    vxor 4, 4, 4
+; PWR7-NEXT:    vsrh 3, 2, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
-; PWR7-NEXT:    xxland 34, 34, 37
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 4
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
-; PWR7-NEXT:    vspltish 3, 13
-; PWR7-NEXT:    vcmpgtuh 2, 3, 2
+; PWR7-NEXT:    vxor 3, 3, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
+; PWR7-NEXT:    vcmpgtuh 2, 7, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_13_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 13
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltish 3, 13
 ; PWR6-NEXT:    vcmpgtuh 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_13_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI36_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI36_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI36_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI36_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 15
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI36_1@toc@l
+; PWR7-NEXT:    vspltish 7, 13
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
 ; PWR7-NEXT:    vsrh 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltish 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
-; PWR7-NEXT:    vxor 4, 4, 4
+; PWR7-NEXT:    vsrh 3, 2, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
-; PWR7-NEXT:    xxland 34, 34, 37
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 4
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
-; PWR7-NEXT:    vspltish 3, 13
-; PWR7-NEXT:    vcmpgtuh 2, 2, 3
+; PWR7-NEXT:    vxor 3, 3, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
+; PWR7-NEXT:    vcmpgtuh 2, 2, 7
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_13_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 13
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltish 3, 14
 ; PWR6-NEXT:    vcmpgtuh 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_14_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI37_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI37_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI37_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI37_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 15
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI37_1@toc@l
+; PWR7-NEXT:    vspltish 7, 14
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
 ; PWR7-NEXT:    vsrh 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltish 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
-; PWR7-NEXT:    vxor 4, 4, 4
+; PWR7-NEXT:    vsrh 3, 2, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
-; PWR7-NEXT:    xxland 34, 34, 37
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 4
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
-; PWR7-NEXT:    vspltish 3, 14
-; PWR7-NEXT:    vcmpgtuh 2, 3, 2
+; PWR7-NEXT:    vxor 3, 3, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
+; PWR7-NEXT:    vcmpgtuh 2, 7, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_14_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 14
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltish 3, 14
 ; PWR6-NEXT:    vcmpgtuh 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_14_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI38_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI38_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI38_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI38_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 15
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI38_1@toc@l
+; PWR7-NEXT:    vspltish 7, 14
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
 ; PWR7-NEXT:    vsrh 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltish 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
-; PWR7-NEXT:    vxor 4, 4, 4
+; PWR7-NEXT:    vsrh 3, 2, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
-; PWR7-NEXT:    xxland 34, 34, 37
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 4
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
-; PWR7-NEXT:    vspltish 3, 14
-; PWR7-NEXT:    vcmpgtuh 2, 2, 3
+; PWR7-NEXT:    vxor 3, 3, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
+; PWR7-NEXT:    vcmpgtuh 2, 2, 7
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_14_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 14
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltish 3, 15
 ; PWR6-NEXT:    vcmpgtuh 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_15_v8i16:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltish 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI39_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI39_0@toc@l
 ; PWR7-NEXT:    vspltish 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI39_0@toc@l
+; PWR7-NEXT:    vspltish 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI39_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 15
-; PWR7-NEXT:    vsrh 3, 2, 3
+; PWR7-NEXT:    vspltish 6, 8
 ; PWR7-NEXT:    addi 3, 3, .LCPI39_1@toc@l
+; PWR7-NEXT:    vspltish 7, 15
+; PWR7-NEXT:    vsrh 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuhm 2, 2, 3
 ; PWR7-NEXT:    vsrh 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltish 4, 4
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vsrh 3, 2, 4
-; PWR7-NEXT:    vxor 4, 4, 4
+; PWR7-NEXT:    vsrh 3, 2, 5
 ; PWR7-NEXT:    vadduhm 2, 2, 3
-; PWR7-NEXT:    vspltisb 3, 1
-; PWR7-NEXT:    xxland 34, 34, 37
-; PWR7-NEXT:    vmladduhm 2, 2, 3, 4
-; PWR7-NEXT:    vspltish 3, 8
-; PWR7-NEXT:    vsrh 2, 2, 3
-; PWR7-NEXT:    vspltish 3, 15
-; PWR7-NEXT:    vcmpgtuh 2, 3, 2
+; PWR7-NEXT:    vxor 3, 3, 3
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmladduhm 2, 2, 1, 3
+; PWR7-NEXT:    vsrh 2, 2, 6
+; PWR7-NEXT:    vcmpgtuh 2, 7, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_15_v8i16:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltish 3, 15
 ; PWR8-NEXT:    vpopcnth 2, 2
 ; PWR8-NEXT:    vcmpgtuh 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vsrw 2, 2, 3
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 0
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_2_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI42_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI42_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI42_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI42_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, 4
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI42_1@toc@l
-; PWR7-NEXT:    vspltisw 0, -16
-; PWR7-NEXT:    vspltisb 1, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
+; PWR7-NEXT:    xxland 35, 34, 0
+; PWR7-NEXT:    vsrw 2, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    vadduwm 2, 2, 3
+; PWR7-NEXT:    vadduwm 2, 3, 2
 ; PWR7-NEXT:    vsrw 3, 2, 5
-; PWR7-NEXT:    vspltisb 5, 1
-; PWR7-NEXT:    vrlw 6, 5, 0
+; PWR7-NEXT:    xxlxor 37, 37, 37
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
-; PWR7-NEXT:    xxland 34, 34, 33
-; PWR7-NEXT:    vmsumuhm 3, 2, 6, 3
-; PWR7-NEXT:    vmulouh 2, 2, 5
-; PWR7-NEXT:    vspltisw 5, 12
-; PWR7-NEXT:    vslw 3, 3, 0
+; PWR7-NEXT:    vrlw 3, 1, 6
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 5
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 5, 5
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
 ; PWR7-NEXT:    vcmpgtuw 2, 2, 4
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_2_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 2
 ; PWR8-NEXT:    vpopcntw 2, 2

 ; PWR6-NEXT:    vspltisw 3, 3
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_3_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI43_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI43_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI43_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI43_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI43_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 3
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 3
-; PWR7-NEXT:    vcmpgtuw 2, 3, 2
+; PWR7-NEXT:    vcmpgtuw 2, 8, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_3_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 3
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltisw 3, 3
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_3_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI44_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI44_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI44_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI44_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI44_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 3
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 3
-; PWR7-NEXT:    vcmpgtuw 2, 2, 3
+; PWR7-NEXT:    vcmpgtuw 2, 2, 8
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_3_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 3
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vsrw 2, 2, 3
 ; PWR6-NEXT:    vcmpgtuw 2, 5, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_4_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI45_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI45_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI45_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI45_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 1
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI45_1@toc@l
-; PWR7-NEXT:    vspltisw 0, -16
-; PWR7-NEXT:    vspltisb 1, 15
-; PWR7-NEXT:    vrlw 6, 5, 0
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
-; PWR7-NEXT:    xxland 34, 34, 33
-; PWR7-NEXT:    vmsumuhm 3, 2, 6, 3
-; PWR7-NEXT:    vmulouh 2, 2, 5
-; PWR7-NEXT:    vspltisw 5, 12
-; PWR7-NEXT:    vslw 3, 3, 0
+; PWR7-NEXT:    vrlw 3, 1, 6
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 5, 5
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vcmpgtuw 2, 4, 2
+; PWR7-NEXT:    vcmpgtuw 2, 5, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_4_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 4
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vsrw 2, 2, 3
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_4_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI46_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI46_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI46_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI46_1@toc@ha
-; PWR7-NEXT:    vspltisb 5, 1
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI46_1@toc@l
-; PWR7-NEXT:    vspltisw 0, -16
-; PWR7-NEXT:    vspltisb 1, 15
-; PWR7-NEXT:    vrlw 6, 5, 0
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
-; PWR7-NEXT:    xxland 34, 34, 33
-; PWR7-NEXT:    vmsumuhm 3, 2, 6, 3
-; PWR7-NEXT:    vmulouh 2, 2, 5
-; PWR7-NEXT:    vspltisw 5, 12
-; PWR7-NEXT:    vslw 3, 3, 0
+; PWR7-NEXT:    vrlw 3, 1, 6
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 5, 5
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vcmpgtuw 2, 2, 4
+; PWR7-NEXT:    vcmpgtuw 2, 2, 5
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_4_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 4
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltisw 3, 5
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_5_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI47_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI47_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI47_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI47_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI47_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 5
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 5
-; PWR7-NEXT:    vcmpgtuw 2, 3, 2
+; PWR7-NEXT:    vcmpgtuw 2, 8, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_5_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 5
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltisw 3, 5
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_5_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI48_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI48_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI48_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI48_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI48_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 5
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 5
-; PWR7-NEXT:    vcmpgtuw 2, 2, 3
+; PWR7-NEXT:    vcmpgtuw 2, 2, 8
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_5_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 5
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltisw 3, 6
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_6_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI49_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI49_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI49_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI49_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI49_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 6
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 6
-; PWR7-NEXT:    vcmpgtuw 2, 3, 2
+; PWR7-NEXT:    vcmpgtuw 2, 8, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_6_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 6
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltisw 3, 6
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_6_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI50_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI50_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI50_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI50_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI50_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 6
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 6
-; PWR7-NEXT:    vcmpgtuw 2, 2, 3
+; PWR7-NEXT:    vcmpgtuw 2, 2, 8
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_6_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 6
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltisw 3, 7
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_7_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI51_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI51_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI51_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI51_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI51_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 7
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 7
-; PWR7-NEXT:    vcmpgtuw 2, 3, 2
+; PWR7-NEXT:    vcmpgtuw 2, 8, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_7_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 7
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltisw 3, 7
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_7_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI52_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI52_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI52_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI52_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI52_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 7
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 7
-; PWR7-NEXT:    vcmpgtuw 2, 2, 3
+; PWR7-NEXT:    vcmpgtuw 2, 2, 8
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_7_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 7
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltisw 3, 8
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_8_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI53_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI53_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI53_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI53_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI53_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 8
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 8
-; PWR7-NEXT:    vcmpgtuw 2, 3, 2
+; PWR7-NEXT:    vcmpgtuw 2, 8, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_8_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 8
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltisw 3, 8
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_8_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI54_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI54_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI54_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI54_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI54_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 8
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 8
-; PWR7-NEXT:    vcmpgtuw 2, 2, 3
+; PWR7-NEXT:    vcmpgtuw 2, 2, 8
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_8_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 8
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltisw 3, 9
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_9_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI55_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI55_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI55_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI55_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI55_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 9
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 9
-; PWR7-NEXT:    vcmpgtuw 2, 3, 2
+; PWR7-NEXT:    vcmpgtuw 2, 8, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_9_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 9
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltisw 3, 9
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_9_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI56_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI56_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI56_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI56_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI56_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 9
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 9
-; PWR7-NEXT:    vcmpgtuw 2, 2, 3
+; PWR7-NEXT:    vcmpgtuw 2, 2, 8
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_9_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 9
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltisw 3, 10
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_10_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI57_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI57_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI57_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI57_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI57_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 10
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 10
-; PWR7-NEXT:    vcmpgtuw 2, 3, 2
+; PWR7-NEXT:    vcmpgtuw 2, 8, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_10_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 10
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltisw 3, 10
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_10_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI58_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI58_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI58_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI58_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI58_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 10
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 10
-; PWR7-NEXT:    vcmpgtuw 2, 2, 3
+; PWR7-NEXT:    vcmpgtuw 2, 2, 8
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_10_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 10
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltisw 3, 11
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_11_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI59_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI59_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI59_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI59_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI59_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 11
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 11
-; PWR7-NEXT:    vcmpgtuw 2, 3, 2
+; PWR7-NEXT:    vcmpgtuw 2, 8, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_11_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 11
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltisw 3, 11
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_11_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI60_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI60_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI60_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI60_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI60_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 11
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 11
-; PWR7-NEXT:    vcmpgtuw 2, 2, 3
+; PWR7-NEXT:    vcmpgtuw 2, 2, 8
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_11_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 11
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vsrw 2, 2, 5
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_12_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI61_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI61_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI61_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI61_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI61_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vcmpgtuw 2, 4, 2
+; PWR7-NEXT:    vcmpgtuw 2, 7, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_12_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 12
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vsrw 2, 2, 5
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_12_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI62_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI62_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI62_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI62_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI62_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vcmpgtuw 2, 2, 4
+; PWR7-NEXT:    vcmpgtuw 2, 2, 7
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_12_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 12
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltisw 3, 13
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_13_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI63_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI63_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI63_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI63_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI63_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 13
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 13
-; PWR7-NEXT:    vcmpgtuw 2, 3, 2
+; PWR7-NEXT:    vcmpgtuw 2, 8, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_13_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 13
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltisw 3, 13
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_13_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI64_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI64_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI64_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI64_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI64_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 13
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 13
-; PWR7-NEXT:    vcmpgtuw 2, 2, 3
+; PWR7-NEXT:    vcmpgtuw 2, 2, 8
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_13_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 13
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltisw 3, 14
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_14_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI65_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI65_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI65_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI65_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI65_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 14
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 14
-; PWR7-NEXT:    vcmpgtuw 2, 3, 2
+; PWR7-NEXT:    vcmpgtuw 2, 8, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_14_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 14
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltisw 3, 14
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_14_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI66_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI66_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI66_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI66_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI66_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 14
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 14
-; PWR7-NEXT:    vcmpgtuw 2, 2, 3
+; PWR7-NEXT:    vcmpgtuw 2, 2, 8
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_14_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 14
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltisw 3, 15
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_15_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI67_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI67_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI67_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI67_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI67_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 15
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 15
-; PWR7-NEXT:    vcmpgtuw 2, 3, 2
+; PWR7-NEXT:    vcmpgtuw 2, 8, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_15_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 15
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vspltisw 3, 15
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_15_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI68_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI68_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI68_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI68_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI68_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 15
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 15
-; PWR7-NEXT:    vcmpgtuw 2, 2, 3
+; PWR7-NEXT:    vcmpgtuw 2, 2, 8
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_15_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 15
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR8-NEXT:    blr

 ; PWR6-NEXT:    vadduwm 3, 3, 3
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_16_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI69_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI69_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI69_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI69_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI69_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 8
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 8
-; PWR7-NEXT:    vadduwm 3, 3, 3
+; PWR7-NEXT:    vadduwm 3, 8, 8
 ; PWR7-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_16_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 8
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vadduwm 3, 3, 3

 ; PWR6-NEXT:    vadduwm 3, 3, 3
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_16_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI70_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI70_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI70_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI70_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI70_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 8
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 8
-; PWR7-NEXT:    vadduwm 3, 3, 3
+; PWR7-NEXT:    vadduwm 3, 8, 8
 ; PWR7-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_16_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 8
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vadduwm 3, 3, 3

 ; PWR6-NEXT:    vsubuwm 3, 4, 0
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_17_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI71_0@toc@ha
+; PWR7-NEXT:    vspltisw 4, 2
 ; PWR7-NEXT:    addi 3, 3, .LCPI71_0@toc@l
-; PWR7-NEXT:    vspltisw 5, 2
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI71_1@toc@ha
-; PWR7-NEXT:    vspltisw 0, -16
-; PWR7-NEXT:    vsrw 4, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI71_1@toc@l
-; PWR7-NEXT:    vspltisb 1, 15
-; PWR7-NEXT:    vsubuwm 3, 3, 0
-; PWR7-NEXT:    xxland 36, 36, 0
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vsrw 8, 2, 3
+; PWR7-NEXT:    vsubuwm 3, 3, 6
+; PWR7-NEXT:    xxland 40, 40, 0
+; PWR7-NEXT:    vsubuwm 2, 2, 8
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
-; PWR7-NEXT:    vsubuwm 2, 2, 4
-; PWR7-NEXT:    vsrw 4, 2, 5
+; PWR7-NEXT:    vsrw 4, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 5, 4
 ; PWR7-NEXT:    xxland 36, 36, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 4
 ; PWR7-NEXT:    vsrw 4, 2, 5
-; PWR7-NEXT:    vspltisb 5, 1
-; PWR7-NEXT:    vrlw 6, 5, 0
+; PWR7-NEXT:    xxlxor 37, 37, 37
 ; PWR7-NEXT:    vadduwm 2, 2, 4
-; PWR7-NEXT:    xxlxor 36, 36, 36
-; PWR7-NEXT:    xxland 34, 34, 33
-; PWR7-NEXT:    vmsumuhm 4, 2, 6, 4
-; PWR7-NEXT:    vmulouh 2, 2, 5
-; PWR7-NEXT:    vspltisw 5, 12
-; PWR7-NEXT:    vslw 4, 4, 0
+; PWR7-NEXT:    vrlw 4, 1, 6
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmsumuhm 4, 2, 4, 5
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 4, 4, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 4
-; PWR7-NEXT:    vadduwm 4, 5, 5
+; PWR7-NEXT:    vadduwm 4, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 4
 ; PWR7-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_17_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, -16
 ; PWR8-NEXT:    vspltisw 4, 1

 ; PWR6-NEXT:    vsubuwm 3, 4, 0
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_17_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI72_0@toc@ha
+; PWR7-NEXT:    vspltisw 4, 2
 ; PWR7-NEXT:    addi 3, 3, .LCPI72_0@toc@l
-; PWR7-NEXT:    vspltisw 5, 2
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI72_1@toc@ha
-; PWR7-NEXT:    vspltisw 0, -16
-; PWR7-NEXT:    vsrw 4, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI72_1@toc@l
-; PWR7-NEXT:    vspltisb 1, 15
-; PWR7-NEXT:    vsubuwm 3, 3, 0
-; PWR7-NEXT:    xxland 36, 36, 0
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vsrw 8, 2, 3
+; PWR7-NEXT:    vsubuwm 3, 3, 6
+; PWR7-NEXT:    xxland 40, 40, 0
+; PWR7-NEXT:    vsubuwm 2, 2, 8
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
-; PWR7-NEXT:    vsubuwm 2, 2, 4
-; PWR7-NEXT:    vsrw 4, 2, 5
+; PWR7-NEXT:    vsrw 4, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 5, 4
 ; PWR7-NEXT:    xxland 36, 36, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 4
 ; PWR7-NEXT:    vsrw 4, 2, 5
-; PWR7-NEXT:    vspltisb 5, 1
-; PWR7-NEXT:    vrlw 6, 5, 0
+; PWR7-NEXT:    xxlxor 37, 37, 37
 ; PWR7-NEXT:    vadduwm 2, 2, 4
-; PWR7-NEXT:    xxlxor 36, 36, 36
-; PWR7-NEXT:    xxland 34, 34, 33
-; PWR7-NEXT:    vmsumuhm 4, 2, 6, 4
-; PWR7-NEXT:    vmulouh 2, 2, 5
-; PWR7-NEXT:    vspltisw 5, 12
-; PWR7-NEXT:    vslw 4, 4, 0
+; PWR7-NEXT:    vrlw 4, 1, 6
+; PWR7-NEXT:    xxland 34, 34, 32
+; PWR7-NEXT:    vmsumuhm 4, 2, 4, 5
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 4, 4, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 4
-; PWR7-NEXT:    vadduwm 4, 5, 5
+; PWR7-NEXT:    vadduwm 4, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 4
 ; PWR7-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_17_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, -16
 ; PWR8-NEXT:    vspltisw 4, 1

 ; PWR6-NEXT:    vadduwm 3, 3, 3
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_18_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI73_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI73_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI73_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI73_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI73_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 9
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 9
-; PWR7-NEXT:    vadduwm 3, 3, 3
+; PWR7-NEXT:    vadduwm 3, 8, 8
 ; PWR7-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_18_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 9
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vadduwm 3, 3, 3

 ; PWR6-NEXT:    vadduwm 3, 3, 3
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_18_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI74_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI74_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI74_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI74_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI74_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 9
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 9
-; PWR7-NEXT:    vadduwm 3, 3, 3
+; PWR7-NEXT:    vadduwm 3, 8, 8
 ; PWR7-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_18_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 9
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vadduwm 3, 3, 3

 ; PWR6-NEXT:    vsubuwm 3, 3, 5
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_19_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI75_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI75_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI75_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI75_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI75_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 3
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 3
-; PWR7-NEXT:    vsubuwm 3, 3, 5
+; PWR7-NEXT:    vsubuwm 3, 8, 6
 ; PWR7-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_19_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, -16
 ; PWR8-NEXT:    vspltisw 4, 3
 ; PWR8-NEXT:    vpopcntw 2, 2

 ; PWR6-NEXT:    vsubuwm 3, 3, 5
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_19_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI76_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI76_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI76_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI76_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI76_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 3
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 3
-; PWR7-NEXT:    vsubuwm 3, 3, 5
+; PWR7-NEXT:    vsubuwm 3, 8, 6
 ; PWR7-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_19_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, -16
 ; PWR8-NEXT:    vspltisw 4, 3
 ; PWR8-NEXT:    vpopcntw 2, 2

 ; PWR6-NEXT:    vadduwm 3, 3, 3
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_20_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI77_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI77_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI77_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI77_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI77_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 10
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 10
-; PWR7-NEXT:    vadduwm 3, 3, 3
+; PWR7-NEXT:    vadduwm 3, 8, 8
 ; PWR7-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_20_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 10
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vadduwm 3, 3, 3

 ; PWR6-NEXT:    vadduwm 3, 3, 3
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_20_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI78_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI78_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI78_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI78_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI78_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 10
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 10
-; PWR7-NEXT:    vadduwm 3, 3, 3
+; PWR7-NEXT:    vadduwm 3, 8, 8
 ; PWR7-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_20_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 10
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vadduwm 3, 3, 3

 ; PWR6-NEXT:    vsubuwm 3, 3, 5
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_21_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI79_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI79_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI79_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI79_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI79_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 5
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 5
-; PWR7-NEXT:    vsubuwm 3, 3, 5
+; PWR7-NEXT:    vsubuwm 3, 8, 6
 ; PWR7-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_21_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, -16
 ; PWR8-NEXT:    vspltisw 4, 5
 ; PWR8-NEXT:    vpopcntw 2, 2

 ; PWR6-NEXT:    vsubuwm 3, 3, 5
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_21_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI80_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI80_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI80_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI80_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI80_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 5
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 5
-; PWR7-NEXT:    vsubuwm 3, 3, 5
+; PWR7-NEXT:    vsubuwm 3, 8, 6
 ; PWR7-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_21_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, -16
 ; PWR8-NEXT:    vspltisw 4, 5
 ; PWR8-NEXT:    vpopcntw 2, 2

 ; PWR6-NEXT:    vadduwm 3, 3, 3
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_22_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI81_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI81_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI81_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI81_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI81_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 11
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 11
-; PWR7-NEXT:    vadduwm 3, 3, 3
+; PWR7-NEXT:    vadduwm 3, 8, 8
 ; PWR7-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_22_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 11
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vadduwm 3, 3, 3

 ; PWR6-NEXT:    vadduwm 3, 3, 3
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_22_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI82_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI82_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI82_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI82_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI82_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 11
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 11
-; PWR7-NEXT:    vadduwm 3, 3, 3
+; PWR7-NEXT:    vadduwm 3, 8, 8
 ; PWR7-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_22_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 11
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vadduwm 3, 3, 3

 ; PWR6-NEXT:    vsubuwm 3, 3, 5
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_23_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI83_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI83_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI83_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI83_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI83_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 7
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 7
-; PWR7-NEXT:    vsubuwm 3, 3, 5
+; PWR7-NEXT:    vsubuwm 3, 8, 6
 ; PWR7-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_23_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, -16
 ; PWR8-NEXT:    vspltisw 4, 7
 ; PWR8-NEXT:    vpopcntw 2, 2

 ; PWR6-NEXT:    vsubuwm 3, 3, 5
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_23_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI84_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI84_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI84_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI84_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI84_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 7
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 7
-; PWR7-NEXT:    vsubuwm 3, 3, 5
+; PWR7-NEXT:    vsubuwm 3, 8, 6
 ; PWR7-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_23_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, -16
 ; PWR8-NEXT:    vspltisw 4, 7
 ; PWR8-NEXT:    vpopcntw 2, 2

 ; PWR6-NEXT:    vsrw 2, 2, 3
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_24_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI85_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI85_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI85_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI85_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI85_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
 ; PWR7-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_24_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 12
 ; PWR8-NEXT:    vpopcntw 2, 2

 ; PWR6-NEXT:    vsrw 2, 2, 3
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_24_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI86_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI86_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI86_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI86_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI86_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
 ; PWR7-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_24_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 12
 ; PWR8-NEXT:    vpopcntw 2, 2

 ; PWR6-NEXT:    vsubuwm 3, 3, 5
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_25_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI87_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI87_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI87_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI87_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI87_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 9
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 9
-; PWR7-NEXT:    vsubuwm 3, 3, 5
+; PWR7-NEXT:    vsubuwm 3, 8, 6
 ; PWR7-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_25_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, -16
 ; PWR8-NEXT:    vspltisw 4, 9
 ; PWR8-NEXT:    vpopcntw 2, 2

 ; PWR6-NEXT:    vsubuwm 3, 3, 5
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_25_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI88_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI88_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI88_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI88_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI88_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 9
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 9
-; PWR7-NEXT:    vsubuwm 3, 3, 5
+; PWR7-NEXT:    vsubuwm 3, 8, 6
 ; PWR7-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_25_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, -16
 ; PWR8-NEXT:    vspltisw 4, 9
 ; PWR8-NEXT:    vpopcntw 2, 2

 ; PWR6-NEXT:    vadduwm 3, 3, 3
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_26_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI89_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI89_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI89_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI89_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI89_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 13
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 13
-; PWR7-NEXT:    vadduwm 3, 3, 3
+; PWR7-NEXT:    vadduwm 3, 8, 8
 ; PWR7-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_26_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 13
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vadduwm 3, 3, 3

 ; PWR6-NEXT:    vadduwm 3, 3, 3
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_26_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI90_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI90_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI90_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI90_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI90_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 13
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 13
-; PWR7-NEXT:    vadduwm 3, 3, 3
+; PWR7-NEXT:    vadduwm 3, 8, 8
 ; PWR7-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_26_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 13
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vadduwm 3, 3, 3

 ; PWR6-NEXT:    vsubuwm 3, 3, 5
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_27_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI91_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI91_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI91_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI91_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI91_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 11
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 11
-; PWR7-NEXT:    vsubuwm 3, 3, 5
+; PWR7-NEXT:    vsubuwm 3, 8, 6
 ; PWR7-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_27_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, -16
 ; PWR8-NEXT:    vspltisw 4, 11
 ; PWR8-NEXT:    vpopcntw 2, 2

 ; PWR6-NEXT:    vsubuwm 3, 3, 5
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_27_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI92_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI92_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI92_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI92_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI92_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 11
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 11
-; PWR7-NEXT:    vsubuwm 3, 3, 5
+; PWR7-NEXT:    vsubuwm 3, 8, 6
 ; PWR7-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_27_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, -16
 ; PWR8-NEXT:    vspltisw 4, 11
 ; PWR8-NEXT:    vpopcntw 2, 2

 ; PWR6-NEXT:    vadduwm 3, 3, 3
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_28_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI93_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI93_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI93_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI93_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI93_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 14
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 14
-; PWR7-NEXT:    vadduwm 3, 3, 3
+; PWR7-NEXT:    vadduwm 3, 8, 8
 ; PWR7-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_28_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 14
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vadduwm 3, 3, 3

 ; PWR6-NEXT:    vadduwm 3, 3, 3
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_28_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI94_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI94_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI94_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI94_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI94_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 14
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 14
-; PWR7-NEXT:    vadduwm 3, 3, 3
+; PWR7-NEXT:    vadduwm 3, 8, 8
 ; PWR7-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_28_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 14
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vadduwm 3, 3, 3

 ; PWR6-NEXT:    vsubuwm 3, 3, 5
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_29_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI95_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI95_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI95_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI95_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI95_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 13
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 13
-; PWR7-NEXT:    vsubuwm 3, 3, 5
+; PWR7-NEXT:    vsubuwm 3, 8, 6
 ; PWR7-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_29_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, -16
 ; PWR8-NEXT:    vspltisw 4, 13
 ; PWR8-NEXT:    vpopcntw 2, 2

 ; PWR6-NEXT:    vsubuwm 3, 3, 5
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_29_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI96_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI96_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI96_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI96_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI96_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 13
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 13
-; PWR7-NEXT:    vsubuwm 3, 3, 5
+; PWR7-NEXT:    vsubuwm 3, 8, 6
 ; PWR7-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_29_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, -16
 ; PWR8-NEXT:    vspltisw 4, 13
 ; PWR8-NEXT:    vpopcntw 2, 2

 ; PWR6-NEXT:    vadduwm 3, 3, 3
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_30_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI97_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI97_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI97_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI97_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI97_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 15
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 15
-; PWR7-NEXT:    vadduwm 3, 3, 3
+; PWR7-NEXT:    vadduwm 3, 8, 8
 ; PWR7-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_30_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 15
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vadduwm 3, 3, 3

 ; PWR6-NEXT:    vadduwm 3, 3, 3
 ; PWR6-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_30_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI98_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI98_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI98_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI98_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI98_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 15
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 15
-; PWR7-NEXT:    vadduwm 3, 3, 3
+; PWR7-NEXT:    vadduwm 3, 8, 8
 ; PWR7-NEXT:    vcmpgtuw 2, 2, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_30_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, 15
 ; PWR8-NEXT:    vpopcntw 2, 2
 ; PWR8-NEXT:    vadduwm 3, 3, 3

 ; PWR6-NEXT:    vsubuwm 3, 3, 5
 ; PWR6-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_31_v4i32:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    vspltisw 3, 1
 ; PWR7-NEXT:    addis 3, 2, .LCPI99_0@toc@ha
-; PWR7-NEXT:    addi 3, 3, .LCPI99_0@toc@l
 ; PWR7-NEXT:    vspltisw 4, 2
+; PWR7-NEXT:    addi 3, 3, .LCPI99_0@toc@l
+; PWR7-NEXT:    vspltisw 5, 4
+; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisb 1, 1
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI99_1@toc@ha
-; PWR7-NEXT:    vspltisw 5, -16
-; PWR7-NEXT:    vsrw 3, 2, 3
+; PWR7-NEXT:    vspltisw 6, -16
 ; PWR7-NEXT:    addi 3, 3, .LCPI99_1@toc@l
-; PWR7-NEXT:    vspltisb 0, 15
+; PWR7-NEXT:    vspltisw 7, 12
+; PWR7-NEXT:    vspltisw 8, 15
+; PWR7-NEXT:    vsrw 3, 2, 3
 ; PWR7-NEXT:    xxland 35, 35, 0
-; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsubuwm 2, 2, 3
+; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    vsrw 3, 2, 4
 ; PWR7-NEXT:    xxland 34, 34, 0
-; PWR7-NEXT:    vspltisw 4, 4
+; PWR7-NEXT:    xxlxor 36, 36, 36
 ; PWR7-NEXT:    xxland 35, 35, 0
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vsrw 3, 2, 4
-; PWR7-NEXT:    vspltisb 4, 1
-; PWR7-NEXT:    vrlw 1, 4, 5
+; PWR7-NEXT:    vsrw 3, 2, 5
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    xxlxor 35, 35, 35
+; PWR7-NEXT:    vrlw 3, 1, 6
 ; PWR7-NEXT:    xxland 34, 34, 32
-; PWR7-NEXT:    vmsumuhm 3, 2, 1, 3
-; PWR7-NEXT:    vmulouh 2, 2, 4
-; PWR7-NEXT:    vspltisw 4, 12
-; PWR7-NEXT:    vslw 3, 3, 5
+; PWR7-NEXT:    vmsumuhm 3, 2, 3, 4
+; PWR7-NEXT:    vmulouh 2, 2, 1
+; PWR7-NEXT:    vslw 3, 3, 6
 ; PWR7-NEXT:    vadduwm 2, 2, 3
-; PWR7-NEXT:    vadduwm 3, 4, 4
+; PWR7-NEXT:    vadduwm 3, 7, 7
 ; PWR7-NEXT:    vsrw 2, 2, 3
-; PWR7-NEXT:    vspltisw 3, 15
-; PWR7-NEXT:    vsubuwm 3, 3, 5
+; PWR7-NEXT:    vsubuwm 3, 8, 6
 ; PWR7-NEXT:    vcmpgtuw 2, 3, 2
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_31_v4i32:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    vspltisw 3, -16
 ; PWR8-NEXT:    vspltisw 4, 15
 ; PWR8-NEXT:    vpopcntw 2, 2

 ; PWR7-NEXT:    addi 3, 3, -1
 ; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
 ; PWR7-NEXT:    lxvw4x 0, 0, 3
 ; PWR7-NEXT:    addis 3, 2, .LCPI100_0@toc@ha
 ; PWR7-NEXT:    addi 3, 3, .LCPI100_0@toc@l
 ; PWR7-NEXT:    xxland 34, 34, 0
 ; PWR7-NEXT:    vcmpequw 2, 2, 3
-; PWR7-NEXT:    lxvw4x 35, 0, 3
 ; PWR7-NEXT:    xxlnor 34, 34, 34
+; PWR7-NEXT:    lxvw4x 35, 0, 3
 ; PWR7-NEXT:    vperm 3, 2, 2, 3
 ; PWR7-NEXT:    xxlor 34, 35, 34
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_1_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI100_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 2
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_2_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 2
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 2
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 2
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_2_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI102_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI102_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_3_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 3
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 3
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 3
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_3_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI103_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI103_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 3
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_3_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 3
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 3
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 3
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_3_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI104_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI104_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_4_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 4
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 4
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 4
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_4_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI105_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI105_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 4
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_4_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 4
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 4
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 4
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_4_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI106_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI106_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_5_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 5
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 5
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 5
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_5_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI107_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI107_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 5
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_5_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 5
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 5
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 5
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_5_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI108_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI108_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_6_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 6
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 6
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 6
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_6_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI109_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI109_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 6
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_6_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 6
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 6
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 6
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_6_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI110_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI110_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_7_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 7
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 7
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 7
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_7_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI111_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI111_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 7
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_7_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 7
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 7
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 7
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_7_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI112_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI112_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_8_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 8
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 8
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 8
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_8_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI113_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI113_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 8
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_8_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 8
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 8
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 8
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_8_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI114_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI114_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_9_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 9
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 9
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 9
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_9_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI115_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI115_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 9
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_9_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 9
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 9
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 9
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_9_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI116_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI116_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_10_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 10
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 10
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 10
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_10_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI117_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI117_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 10
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_10_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 10
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 10
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 10
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_10_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI118_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI118_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_11_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 11
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 11
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 11
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_11_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI119_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI119_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 11
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_11_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 11
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 11
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 11
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_11_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI120_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI120_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_12_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 12
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 12
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 12
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_12_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI121_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI121_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 12
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_12_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 12
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 12
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 12
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_12_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI122_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI122_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_13_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 13
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 13
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 13
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_13_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI123_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI123_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 13
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_13_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 13
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 13
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 13
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_13_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI124_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI124_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_14_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 14
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 14
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 14
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_14_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI125_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI125_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 14
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_14_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 14
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 14
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 14
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_14_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI126_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI126_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_15_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 15
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 15
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 15
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_15_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI127_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI127_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 15
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_15_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 15
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 15
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 15
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_15_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI128_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI128_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_16_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 16
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 16
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 16
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_16_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI129_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI129_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 16
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_16_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 16
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 16
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 16
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_16_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI130_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI130_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_17_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 17
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 17
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 17
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_17_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI131_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI131_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 17
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_17_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 17
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 17
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 17
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_17_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI132_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI132_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_18_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 18
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 18
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 18
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_18_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI133_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI133_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 18
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_18_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 18
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 18
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 18
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_18_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI134_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI134_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_19_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 19
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 19
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 19
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_19_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI135_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI135_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 19
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_19_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 19
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 19
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 19
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_19_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI136_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI136_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_20_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 20
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 20
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 20
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_20_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI137_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI137_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 20
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_20_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 20
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 20
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 20
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_20_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI138_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI138_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_21_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 21
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 21
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 21
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_21_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI139_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI139_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 21
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_21_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 21
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 21
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 21
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_21_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI140_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI140_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_22_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 22
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 22
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 22
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_22_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI141_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI141_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 22
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_22_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 22
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 22
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 22
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_22_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI142_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI142_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_23_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 23
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 23
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 23
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_23_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI143_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI143_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 23
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_23_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 23
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 23
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 23
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_23_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI144_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI144_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_24_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 24
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 24
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 24
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_24_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI145_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI145_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 24
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_24_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 24
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 24
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 24
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_24_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI146_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI146_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_25_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 25
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 25
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 25
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_25_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI147_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI147_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 25
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_25_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 25
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 25
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 25
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_25_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI148_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI148_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_26_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 26
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 26
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 26
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_26_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI149_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI149_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 26
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_26_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 26
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 26
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 26
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_26_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI150_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI150_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_27_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 27
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 27
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 27
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_27_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI151_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI151_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 27
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_27_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 27
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 27
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 27
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_27_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI152_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI152_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_28_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 28
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 28
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 28
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_28_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI153_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI153_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 28
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_28_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 28
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 28
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 28
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_28_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI154_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI154_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_29_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 29
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 29
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 29
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_29_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI155_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI155_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 29
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_29_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 29
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 29
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 29
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_29_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI156_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI156_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_30_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 30
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 30
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 30
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_30_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI157_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI157_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 30
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_30_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 30
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 30
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 30
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_30_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI158_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI158_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_31_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 31
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 31
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 31
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_31_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI159_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI159_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 31
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_31_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 31
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 31
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 31
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_31_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI160_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI160_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_32_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 32
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 32
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 32
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_32_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI161_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI161_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 32
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_32_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 32
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 32
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 32
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_32_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI162_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI162_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_33_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 33
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 33
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 33
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_33_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI163_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI163_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 33
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_33_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 33
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 33
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 33
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_33_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI164_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI164_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_34_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 34
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 34
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 34
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_34_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI165_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI165_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 34
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_34_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 34
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 34
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 34
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_34_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI166_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI166_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_35_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 35
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 35
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 35
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_35_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI167_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI167_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 35
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_35_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 35
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 35
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 35
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_35_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI168_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI168_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_36_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 36
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 36
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 36
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_36_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI169_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI169_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 36
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_36_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 36
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 36
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 36
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_36_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI170_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI170_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_37_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 37
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 37
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 37
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_37_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI171_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI171_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 37
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_37_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 37
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 37
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 37
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_37_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI172_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI172_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_38_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 38
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 38
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 38
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_38_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI173_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI173_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 38
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_38_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 38
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 38
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 38
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_38_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI174_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI174_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_39_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 39
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 39
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 39
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_39_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI175_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI175_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 39
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_39_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 39
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 39
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 39
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_39_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI176_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI176_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_40_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 40
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 40
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 40
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_40_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI177_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI177_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 40
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_40_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 40
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 40
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 40
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_40_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI178_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI178_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_41_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 41
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 41
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 41
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_41_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI179_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI179_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 41
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_41_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 41
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 41
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 41
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_41_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI180_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI180_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_42_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 42
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 42
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 42
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_42_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI181_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI181_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 42
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_42_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 42
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 42
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 42
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_42_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI182_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI182_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_43_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 43
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 43
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 43
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_43_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI183_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI183_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 43
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_43_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 43
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 43
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 43
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_43_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI184_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI184_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_44_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 44
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 44
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 44
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_44_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI185_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI185_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 44
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_44_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 44
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 44
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 44
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_44_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI186_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI186_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_45_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 45
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 45
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 45
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_45_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI187_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI187_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 45
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_45_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 45
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 45
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 45
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_45_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI188_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI188_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_46_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 46
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 46
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 46
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_46_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI189_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI189_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 46
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_46_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 46
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 46
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 46
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_46_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI190_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI190_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_47_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 47
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 47
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 47
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_47_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI191_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI191_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 47
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_47_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 47
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 47
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 47
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_47_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI192_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI192_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_48_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 48
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 48
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 48
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_48_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI193_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI193_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 48
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_48_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 48
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 48
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 48
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_48_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI194_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI194_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_49_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 49
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 49
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 49
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_49_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI195_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI195_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 49
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_49_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 49
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 49
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 49
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_49_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI196_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI196_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_50_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 50
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 50
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 50
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_50_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI197_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI197_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 50
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_50_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 50
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 50
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 50
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_50_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI198_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI198_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_51_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 51
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 51
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 51
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_51_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI199_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI199_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 51
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_51_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 51
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 51
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 51
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_51_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI200_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI200_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_52_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 52
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 52
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 52
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_52_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI201_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI201_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 52
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_52_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 52
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 52
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 52
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_52_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI202_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI202_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_53_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 53
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 53
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 53
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_53_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI203_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI203_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 53
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_53_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 53
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 53
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 53
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_53_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI204_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI204_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_54_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 54
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 54
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 54
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_54_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI205_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI205_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 54
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_54_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 54
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 54
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 54
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_54_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI206_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI206_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_55_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 55
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 55
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 55
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_55_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI207_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI207_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 55
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_55_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 55
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 55
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 55
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_55_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI208_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI208_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_56_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 56
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 56
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 56
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_56_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI209_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI209_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 56
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_56_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 56
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 56
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 56
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_56_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI210_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI210_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_57_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 57
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 57
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 57
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_57_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI211_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI211_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 57
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_57_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 57
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 57
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 57
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_57_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI212_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI212_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_58_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 58
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 58
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 58
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_58_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI213_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI213_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 58
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_58_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 58
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 58
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 58
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_58_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI214_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI214_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_59_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 59
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 59
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 59
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_59_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI215_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI215_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 59
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_59_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 59
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 59
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 59
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_59_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI216_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI216_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_60_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 60
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 60
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 60
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_60_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI217_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI217_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 60
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_60_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 60
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 60
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 60
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_60_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI218_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI218_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_61_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 61
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 61
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 61
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_61_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI219_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI219_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 61
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_61_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 61
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 61
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 61
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_61_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI220_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI220_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_62_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 62
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 62
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 62
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_62_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI221_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI221_0@toc@l

 ; PWR6-NEXT:    subfe 3, 5, 5
 ; PWR6-NEXT:    subfic 4, 4, 62
 ; PWR6-NEXT:    subfe 4, 5, 5
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ugt_62_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 62
-; PWR7-NEXT:    iselgt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 62
-; PWR7-NEXT:    iselgt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    iselgt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 62
+; PWR7-NEXT:    iselgt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ugt_62_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI222_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI222_0@toc@l

 ; PWR6-NEXT:    subfe 3, 3, 3
 ; PWR6-NEXT:    subc 5, 4, 5
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
 ;
 ; PWR7-LABEL: ult_63_v2i64:
 ; PWR7:       # %bb.0:
 ; PWR7-NEXT:    addi 3, 1, -32
-; PWR7-NEXT:    li 5, 0
-; PWR7-NEXT:    li 6, -1
+; PWR7-NEXT:    li 5, -1
 ; PWR7-NEXT:    stxvd2x 34, 0, 3
-; PWR7-NEXT:    ld 3, -24(1)
-; PWR7-NEXT:    ld 4, -32(1)
-; PWR7-NEXT:    popcntd 3, 3
+; PWR7-NEXT:    ld 4, -24(1)
+; PWR7-NEXT:    ld 3, -32(1)
 ; PWR7-NEXT:    popcntd 4, 4
-; PWR7-NEXT:    cmpldi 3, 63
-; PWR7-NEXT:    isellt 3, 6, 5
+; PWR7-NEXT:    popcntd 3, 3
 ; PWR7-NEXT:    cmpldi 4, 63
-; PWR7-NEXT:    isellt 4, 6, 5
-; PWR7-NEXT:    std 3, -8(1)
+; PWR7-NEXT:    li 4, 0
+; PWR7-NEXT:    isellt 6, 5, 4
+; PWR7-NEXT:    cmpldi 3, 63
+; PWR7-NEXT:    isellt 3, 5, 4
+; PWR7-NEXT:    std 6, -8(1)
+; PWR7-NEXT:    std 3, -16(1)
 ; PWR7-NEXT:    addi 3, 1, -16
-; PWR7-NEXT:    std 4, -16(1)
 ; PWR7-NEXT:    lxvd2x 34, 0, 3
 ; PWR7-NEXT:    blr
 ;
 ; PWR8-LABEL: ult_63_v2i64:
 ; PWR8:       # %bb.0:
 ; PWR8-NEXT:    addis 3, 2, .LCPI223_0@toc@ha
 ; PWR8-NEXT:    vpopcntd 2, 2
 ; PWR8-NEXT:    addi 3, 3, .LCPI223_0@toc@l

llvm/test/CodeGen/PowerPC/vsx.ll

 
 
 }
 
 define <2 x i64> @test26(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test26:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi r3, r1, -32
-; CHECK-NEXT:    addi r4, r1, -48
 ; CHECK-NEXT:    stxvd2x v3, 0, r3
-; CHECK-NEXT:    stxvd2x v2, 0, r4
+; CHECK-NEXT:    addi r3, r1, -48
+; CHECK-NEXT:    stxvd2x v2, 0, r3
 ; CHECK-NEXT:    ld r3, -24(r1)
 ; CHECK-NEXT:    ld r4, -40(r1)
 ; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    ld r4, -48(r1)
 ; CHECK-NEXT:    std r3, -8(r1)
 ; CHECK-NEXT:    ld r3, -32(r1)
 ; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    std r3, -16(r1)
 ; CHECK-NEXT:    addi r3, r1, -16
 ; CHECK-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test26:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addi r3, r1, -32
-; CHECK-REG-NEXT:    addi r4, r1, -48
 ; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
-; CHECK-REG-NEXT:    stxvd2x v2, 0, r4
+; CHECK-REG-NEXT:    addi r3, r1, -48
+; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
 ; CHECK-REG-NEXT:    ld r3, -24(r1)
 ; CHECK-REG-NEXT:    ld r4, -40(r1)
 ; CHECK-REG-NEXT:    add r3, r4, r3
 ; CHECK-REG-NEXT:    ld r4, -48(r1)
 ; CHECK-REG-NEXT:    std r3, -8(r1)
 ; CHECK-REG-NEXT:    ld r3, -32(r1)
 ; CHECK-REG-NEXT:    add r3, r4, r3
 ; CHECK-REG-NEXT:    std r3, -16(r1)

 
 
 }
 
 define <2 x float> @test44(<2 x i64> %a) {
 ; CHECK-LABEL: test44:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi r3, r1, -16
-; CHECK-NEXT:    addi r4, r1, -64
 ; CHECK-NEXT:    stxvd2x v2, 0, r3
 ; CHECK-NEXT:    ld r3, -8(r1)
 ; CHECK-NEXT:    std r3, -24(r1)
 ; CHECK-NEXT:    ld r3, -16(r1)
 ; CHECK-NEXT:    lfd f0, -24(r1)
 ; CHECK-NEXT:    std r3, -32(r1)
 ; CHECK-NEXT:    addi r3, r1, -48
 ; CHECK-NEXT:    fcfidus f0, f0
 ; CHECK-NEXT:    stfs f0, -48(r1)
 ; CHECK-NEXT:    lfd f0, -32(r1)
 ; CHECK-NEXT:    fcfidus f0, f0
 ; CHECK-NEXT:    stfs f0, -64(r1)
 ; CHECK-NEXT:    lxvw4x vs0, 0, r3
-; CHECK-NEXT:    lxvw4x vs1, 0, r4
+; CHECK-NEXT:    addi r3, r1, -64
+; CHECK-NEXT:    lxvw4x vs1, 0, r3
 ; CHECK-NEXT:    xxmrghw v2, vs1, vs0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test44:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addi r3, r1, -16
-; CHECK-REG-NEXT:    addi r4, r1, -64
 ; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
 ; CHECK-REG-NEXT:    ld r3, -8(r1)
 ; CHECK-REG-NEXT:    std r3, -24(r1)
 ; CHECK-REG-NEXT:    ld r3, -16(r1)
 ; CHECK-REG-NEXT:    lfd f0, -24(r1)
 ; CHECK-REG-NEXT:    std r3, -32(r1)
 ; CHECK-REG-NEXT:    addi r3, r1, -48
 ; CHECK-REG-NEXT:    fcfidus f0, f0
 ; CHECK-REG-NEXT:    stfs f0, -48(r1)
 ; CHECK-REG-NEXT:    lfd f0, -32(r1)
 ; CHECK-REG-NEXT:    fcfidus f0, f0
 ; CHECK-REG-NEXT:    stfs f0, -64(r1)
 ; CHECK-REG-NEXT:    lxvw4x vs0, 0, r3
-; CHECK-REG-NEXT:    lxvw4x vs1, 0, r4
+; CHECK-REG-NEXT:    addi r3, r1, -64
+; CHECK-REG-NEXT:    lxvw4x vs1, 0, r3
 ; CHECK-REG-NEXT:    xxmrghw v2, vs1, vs0
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test44:
 ; CHECK-FISL:       # %bb.0:
 ; CHECK-FISL-NEXT:    addi r3, r1, -16
 ; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
 ; CHECK-FISL-NEXT:    ld r3, -8(r1)

 
 ; FIXME: The code quality here looks pretty bad.
 }
 
 define <2 x float> @test45(<2 x i64> %a) {
 ; CHECK-LABEL: test45:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi r3, r1, -16
-; CHECK-NEXT:    addi r4, r1, -64
 ; CHECK-NEXT:    stxvd2x v2, 0, r3
 ; CHECK-NEXT:    ld r3, -8(r1)
 ; CHECK-NEXT:    std r3, -24(r1)
 ; CHECK-NEXT:    ld r3, -16(r1)
 ; CHECK-NEXT:    lfd f0, -24(r1)
 ; CHECK-NEXT:    std r3, -32(r1)
 ; CHECK-NEXT:    addi r3, r1, -48
 ; CHECK-NEXT:    fcfids f0, f0
 ; CHECK-NEXT:    stfs f0, -48(r1)
 ; CHECK-NEXT:    lfd f0, -32(r1)
 ; CHECK-NEXT:    fcfids f0, f0
 ; CHECK-NEXT:    stfs f0, -64(r1)
 ; CHECK-NEXT:    lxvw4x vs0, 0, r3
-; CHECK-NEXT:    lxvw4x vs1, 0, r4
+; CHECK-NEXT:    addi r3, r1, -64
+; CHECK-NEXT:    lxvw4x vs1, 0, r3
 ; CHECK-NEXT:    xxmrghw v2, vs1, vs0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test45:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addi r3, r1, -16
-; CHECK-REG-NEXT:    addi r4, r1, -64
 ; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
 ; CHECK-REG-NEXT:    ld r3, -8(r1)
 ; CHECK-REG-NEXT:    std r3, -24(r1)
 ; CHECK-REG-NEXT:    ld r3, -16(r1)
 ; CHECK-REG-NEXT:    lfd f0, -24(r1)
 ; CHECK-REG-NEXT:    std r3, -32(r1)
 ; CHECK-REG-NEXT:    addi r3, r1, -48
 ; CHECK-REG-NEXT:    fcfids f0, f0
 ; CHECK-REG-NEXT:    stfs f0, -48(r1)
 ; CHECK-REG-NEXT:    lfd f0, -32(r1)
 ; CHECK-REG-NEXT:    fcfids f0, f0
 ; CHECK-REG-NEXT:    stfs f0, -64(r1)
 ; CHECK-REG-NEXT:    lxvw4x vs0, 0, r3
-; CHECK-REG-NEXT:    lxvw4x vs1, 0, r4
+; CHECK-REG-NEXT:    addi r3, r1, -64
+; CHECK-REG-NEXT:    lxvw4x vs1, 0, r3
 ; CHECK-REG-NEXT:    xxmrghw v2, vs1, vs0
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test45:
 ; CHECK-FISL:       # %bb.0:
 ; CHECK-FISL-NEXT:    addi r3, r1, -16
 ; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
 ; CHECK-FISL-NEXT:    ld r3, -8(r1)

 
 
 }
 
 define <2 x i64> @test60(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test60:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi r3, r1, -32
-; CHECK-NEXT:    addi r4, r1, -48
 ; CHECK-NEXT:    stxvd2x v3, 0, r3
-; CHECK-NEXT:    stxvd2x v2, 0, r4
+; CHECK-NEXT:    addi r3, r1, -48
+; CHECK-NEXT:    stxvd2x v2, 0, r3
 ; CHECK-NEXT:    lwz r3, -20(r1)
 ; CHECK-NEXT:    ld r4, -40(r1)
 ; CHECK-NEXT:    sld r3, r4, r3
 ; CHECK-NEXT:    ld r4, -48(r1)
 ; CHECK-NEXT:    std r3, -8(r1)
 ; CHECK-NEXT:    lwz r3, -28(r1)
 ; CHECK-NEXT:    sld r3, r4, r3
 ; CHECK-NEXT:    std r3, -16(r1)
 ; CHECK-NEXT:    addi r3, r1, -16
 ; CHECK-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test60:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addi r3, r1, -32
-; CHECK-REG-NEXT:    addi r4, r1, -48
 ; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
-; CHECK-REG-NEXT:    stxvd2x v2, 0, r4
+; CHECK-REG-NEXT:    addi r3, r1, -48
+; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
 ; CHECK-REG-NEXT:    lwz r3, -20(r1)
 ; CHECK-REG-NEXT:    ld r4, -40(r1)
 ; CHECK-REG-NEXT:    sld r3, r4, r3
 ; CHECK-REG-NEXT:    ld r4, -48(r1)
 ; CHECK-REG-NEXT:    std r3, -8(r1)
 ; CHECK-REG-NEXT:    lwz r3, -28(r1)
 ; CHECK-REG-NEXT:    sld r3, r4, r3
 ; CHECK-REG-NEXT:    std r3, -16(r1)

 
 ; This should scalarize, and the current code quality is not good.
 }
 
 define <2 x i64> @test61(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test61:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi r3, r1, -32
-; CHECK-NEXT:    addi r4, r1, -48
 ; CHECK-NEXT:    stxvd2x v3, 0, r3
-; CHECK-NEXT:    stxvd2x v2, 0, r4
+; CHECK-NEXT:    addi r3, r1, -48
+; CHECK-NEXT:    stxvd2x v2, 0, r3
 ; CHECK-NEXT:    lwz r3, -20(r1)
 ; CHECK-NEXT:    ld r4, -40(r1)
 ; CHECK-NEXT:    srd r3, r4, r3
 ; CHECK-NEXT:    ld r4, -48(r1)
 ; CHECK-NEXT:    std r3, -8(r1)
 ; CHECK-NEXT:    lwz r3, -28(r1)
 ; CHECK-NEXT:    srd r3, r4, r3
 ; CHECK-NEXT:    std r3, -16(r1)
 ; CHECK-NEXT:    addi r3, r1, -16
 ; CHECK-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test61:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addi r3, r1, -32
-; CHECK-REG-NEXT:    addi r4, r1, -48
 ; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
-; CHECK-REG-NEXT:    stxvd2x v2, 0, r4
+; CHECK-REG-NEXT:    addi r3, r1, -48
+; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
 ; CHECK-REG-NEXT:    lwz r3, -20(r1)
 ; CHECK-REG-NEXT:    ld r4, -40(r1)
 ; CHECK-REG-NEXT:    srd r3, r4, r3
 ; CHECK-REG-NEXT:    ld r4, -48(r1)
 ; CHECK-REG-NEXT:    std r3, -8(r1)
 ; CHECK-REG-NEXT:    lwz r3, -28(r1)
 ; CHECK-REG-NEXT:    srd r3, r4, r3
 ; CHECK-REG-NEXT:    std r3, -16(r1)

 
 ; This should scalarize, and the current code quality is not good.
 }
 
 define <2 x i64> @test62(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test62:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi r3, r1, -32
-; CHECK-NEXT:    addi r4, r1, -48
 ; CHECK-NEXT:    stxvd2x v3, 0, r3
-; CHECK-NEXT:    stxvd2x v2, 0, r4
+; CHECK-NEXT:    addi r3, r1, -48
+; CHECK-NEXT:    stxvd2x v2, 0, r3
 ; CHECK-NEXT:    lwz r3, -20(r1)
 ; CHECK-NEXT:    ld r4, -40(r1)
 ; CHECK-NEXT:    srad r3, r4, r3
 ; CHECK-NEXT:    ld r4, -48(r1)
 ; CHECK-NEXT:    std r3, -8(r1)
 ; CHECK-NEXT:    lwz r3, -28(r1)
 ; CHECK-NEXT:    srad r3, r4, r3
 ; CHECK-NEXT:    std r3, -16(r1)
 ; CHECK-NEXT:    addi r3, r1, -16
 ; CHECK-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test62:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addi r3, r1, -32
-; CHECK-REG-NEXT:    addi r4, r1, -48
 ; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
-; CHECK-REG-NEXT:    stxvd2x v2, 0, r4
+; CHECK-REG-NEXT:    addi r3, r1, -48
+; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
 ; CHECK-REG-NEXT:    lwz r3, -20(r1)
 ; CHECK-REG-NEXT:    ld r4, -40(r1)
 ; CHECK-REG-NEXT:    srad r3, r4, r3
 ; CHECK-REG-NEXT:    ld r4, -48(r1)
 ; CHECK-REG-NEXT:    std r3, -8(r1)
 ; CHECK-REG-NEXT:    lwz r3, -28(r1)
 ; CHECK-REG-NEXT:    srad r3, r4, r3
 ; CHECK-REG-NEXT:    std r3, -16(r1)

 }
 
 define <2 x i1> @test66(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test66:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vcmpequw v2, v2, v3
 ; CHECK-NEXT:    addis r3, r2, .LCPI60_0@toc@ha
 ; CHECK-NEXT:    addi r3, r3, .LCPI60_0@toc@l
-; CHECK-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-NEXT:    xxlnor v2, v2, v2
+; CHECK-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-NEXT:    xxlor v2, v3, v2
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test66:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    vcmpequw v2, v2, v3
 ; CHECK-REG-NEXT:    addis r3, r2, .LCPI60_0@toc@ha
 ; CHECK-REG-NEXT:    addi r3, r3, .LCPI60_0@toc@l
-; CHECK-REG-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-REG-NEXT:    xxlnor v2, v2, v2
+; CHECK-REG-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-REG-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-REG-NEXT:    xxlor v2, v3, v2
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test66:
 ; CHECK-FISL:       # %bb.0:
 ; CHECK-FISL-NEXT:    vcmpequw v2, v2, v3
 ; CHECK-FISL-NEXT:    xxlnor v3, v2, v2

 
 
 }
 
 define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test67:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi r3, r1, -32
-; CHECK-NEXT:    addi r4, r1, -48
 ; CHECK-NEXT:    stxvd2x v3, 0, r3
-; CHECK-NEXT:    stxvd2x v2, 0, r4
+; CHECK-NEXT:    addi r3, r1, -48
+; CHECK-NEXT:    stxvd2x v2, 0, r3
 ; CHECK-NEXT:    ld r3, -24(r1)
 ; CHECK-NEXT:    ld r4, -40(r1)
 ; CHECK-NEXT:    ld r6, -48(r1)
 ; CHECK-NEXT:    cmpld r4, r3
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    li r4, -1
 ; CHECK-NEXT:    isellt r5, r4, r3
 ; CHECK-NEXT:    std r5, -8(r1)
 ; CHECK-NEXT:    ld r5, -32(r1)
 ; CHECK-NEXT:    cmpld r6, r5
 ; CHECK-NEXT:    isellt r3, r4, r3
 ; CHECK-NEXT:    std r3, -16(r1)
 ; CHECK-NEXT:    addi r3, r1, -16
 ; CHECK-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test67:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addi r3, r1, -32
-; CHECK-REG-NEXT:    addi r4, r1, -48
 ; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
-; CHECK-REG-NEXT:    stxvd2x v2, 0, r4
+; CHECK-REG-NEXT:    addi r3, r1, -48
+; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
 ; CHECK-REG-NEXT:    ld r3, -24(r1)
 ; CHECK-REG-NEXT:    ld r4, -40(r1)
 ; CHECK-REG-NEXT:    ld r6, -48(r1)
 ; CHECK-REG-NEXT:    cmpld r4, r3
 ; CHECK-REG-NEXT:    li r3, 0
 ; CHECK-REG-NEXT:    li r4, -1
 ; CHECK-REG-NEXT:    isellt r5, r4, r3
 ; CHECK-REG-NEXT:    std r5, -8(r1)

 
 
 }
 
 ; This gets scalarized so the code isn't great
 define <2 x i32> @test80(i32 %v) {
 ; CHECK-LABEL: test80:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi r4, r1, -16
 ; CHECK-NEXT:    stw r3, -16(r1)
+; CHECK-NEXT:    addi r3, r1, -16
+; CHECK-NEXT:    lxvw4x vs0, 0, r3
 ; CHECK-NEXT:    addis r3, r2, .LCPI65_0@toc@ha
-; CHECK-NEXT:    lxvw4x vs0, 0, r4
 ; CHECK-NEXT:    addi r3, r3, .LCPI65_0@toc@l
-; CHECK-NEXT:    lxvw4x v3, 0, r3
-; CHECK-NEXT:    xxspltw v2, vs0, 0
-; CHECK-NEXT:    vadduwm v2, v2, v3
+; CHECK-NEXT:    lxvw4x v2, 0, r3
+; CHECK-NEXT:    xxspltw v3, vs0, 0
+; CHECK-NEXT:    vadduwm v2, v3, v2
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test80:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    addi r4, r1, -16
 ; CHECK-REG-NEXT:    stw r3, -16(r1)
+; CHECK-REG-NEXT:    addi r3, r1, -16
+; CHECK-REG-NEXT:    lxvw4x vs0, 0, r3
 ; CHECK-REG-NEXT:    addis r3, r2, .LCPI65_0@toc@ha
-; CHECK-REG-NEXT:    lxvw4x vs0, 0, r4
 ; CHECK-REG-NEXT:    addi r3, r3, .LCPI65_0@toc@l
-; CHECK-REG-NEXT:    lxvw4x v3, 0, r3
-; CHECK-REG-NEXT:    xxspltw v2, vs0, 0
-; CHECK-REG-NEXT:    vadduwm v2, v2, v3
+; CHECK-REG-NEXT:    lxvw4x v2, 0, r3
+; CHECK-REG-NEXT:    xxspltw v3, vs0, 0
+; CHECK-REG-NEXT:    vadduwm v2, v3, v2
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test80:
 ; CHECK-FISL:       # %bb.0:
 ; CHECK-FISL-NEXT:    # kill: def $r3 killed $r3 killed $x3
 ; CHECK-FISL-NEXT:    stw r3, -16(r1)
 ; CHECK-FISL-NEXT:    addi r3, r1, -16
 ; CHECK-FISL-NEXT:    lxvw4x vs0, 0, r3

llvm/test/CodeGen/PowerPC/widen-vec-correctly-be.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr7 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN: FileCheck %s --check-prefix=CHECK-BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN: FileCheck %s --check-prefix=CHECK-P9-BE
 define void @test() local_unnamed_addr #0 align 2 {
 ; CHECK-BE-LABEL: test:
 ; CHECK-BE:       # %bb.0: # %bb
 ; CHECK-BE-NEXT:    vspltisw v2, -16
 ; CHECK-BE-NEXT:    lhz r3, 0(r3)
 ; CHECK-BE-NEXT:    xxlxor vs1, vs1, vs1
 ; CHECK-BE-NEXT:    addi r3, r3, 1
-; CHECK-BE-NEXT:    vsrw v2, v2, v2
 ; CHECK-BE-NEXT:    sth r3, -32(r1)
 ; CHECK-BE-NEXT:    addi r3, r1, -32
+; CHECK-BE-NEXT:    vsrw v2, v2, v2
 ; CHECK-BE-NEXT:    lxvw4x vs0, 0, r3
 ; CHECK-BE-NEXT:    addi r3, r1, -16
 ; CHECK-BE-NEXT:    xxsel vs0, vs0, vs1, v2
 ; CHECK-BE-NEXT:    stxvw4x vs0, 0, r3
 ; CHECK-BE-NEXT:    lwz r3, -16(r1)
 ; CHECK-BE-NEXT:    stw r3, 0(r3)
 ; CHECK-BE-NEXT:    .p2align 4
 ; CHECK-BE-NEXT:  .LBB0_1: # %bb9