[RISCV][GlobalISel] Select G_CONSTANT, G_ANYEXT, COPY

[nitinjohnraj]

Summary

We select G_CONSTANT generic opcodes by materializing the constant in a
register. G_ANYEXT is replaced with COPY.

[nitinjohnraj]

Refactored

[craig.topper]

llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

131

Declare Result inside the loop.

134

Declare i here instead of outside the loop

135

Declare DstReg here instead of outside the loop.

llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant32.mir

2

What about riscv64?

[nitinjohnraj]

Addressed comments: Refactoring and added rv64 test

[craig.topper]

llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

134

const RISCVMatInt::Inst &I

llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant64.mir

1 ↗

(On Diff #552467)

Need s32/i32 tests too since i32 is legal on RV64.

[nitinjohnraj]

Addressed comments

[nitinjohnraj]

Addressed comment

[nitinjohnraj]

Addressed

[craig.topper]

llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

134

Should be a reference.

[nitinjohnraj]

Addressed comment

[craig.topper]

llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant64.mir

1 ↗

(On Diff #552467)

Did you miss this comment?

[nitinjohnraj]

In order to add s32 tests for rv64 we need to select for G_ANYEXT instructions (to return the s32 constant).

llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant64.mir

1 ↗

(On Diff #552467)

Sorry, was still working on this when I submitted, I forgot to change the status of the issue.
In order to return the constant, I need to select G_ANYEXT as well.

[nitinjohnraj]

Added selection from COPY, G_ANYEXT and G_TRUNC

[nitinjohnraj]

Removed G_TRUNC, will address in another patch (with tests).

[craig.topper]

LGTM

llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

 //===-- RISCVInstructionSelector.cpp -----------------------------*- C++ -*-==//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 /// \file
 /// This file implements the targeting of the InstructionSelector class for
 /// RISC-V.
 /// \todo This should be generated by TableGen.
 //===----------------------------------------------------------------------===//
 
+#include "MCTargetDesc/RISCVMatInt.h"
 #include "RISCVRegisterBankInfo.h"
 #include "RISCVSubtarget.h"
 #include "RISCVTargetMachine.h"
 #include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
+#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 #include "llvm/IR/IntrinsicsRISCV.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "riscv-isel"
 
 using namespace llvm;
 
 #define GET_GLOBALISEL_PREDICATE_BITSET
 #include "RISCVGenGlobalISel.inc"
 #undef GET_GLOBALISEL_PREDICATE_BITSET
 
 namespace {
 
 class RISCVInstructionSelector : public InstructionSelector {
 public:
   RISCVInstructionSelector(const RISCVTargetMachine &TM,
                            const RISCVSubtarget &STI,
                            const RISCVRegisterBankInfo &RBI);
 
-  bool select(MachineInstr &I) override;
+  bool select(MachineInstr &MI) override;
+  bool selectConstant(MachineInstr &MI, MachineIRBuilder &MIB,
+                      MachineRegisterInfo &MRI);
   static const char *getName() { return DEBUG_TYPE; }
 
 private:
   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
 
   const RISCVSubtarget &STI;
   const RISCVInstrInfo &TII;
   const RISCVRegisterInfo &TRI;

 #include "RISCVGenGlobalISel.inc"
 #undef GET_GLOBALISEL_PREDICATES_INIT
 #define GET_GLOBALISEL_TEMPORARIES_INIT
 #include "RISCVGenGlobalISel.inc"
 #undef GET_GLOBALISEL_TEMPORARIES_INIT
 {
 }
 
-bool RISCVInstructionSelector::select(MachineInstr &I) {
+bool RISCVInstructionSelector::select(MachineInstr &MI) {
+  unsigned Opc = MI.getOpcode();
+  MachineBasicBlock &MBB = *MI.getParent();
+  MachineFunction &MF = *MBB.getParent();
+  MachineRegisterInfo &MRI = MF.getRegInfo();
+  MachineIRBuilder MIB(MF);
 
-  if (!isPreISelGenericOpcode(I.getOpcode())) {
+  if (!isPreISelGenericOpcode(MI.getOpcode())) {
     // Certain non-generic instructions also need some special handling.
     return true;
   }
 
-  if (selectImpl(I, *CoverageInfo))
+  if (selectImpl(MI, *CoverageInfo))
     return true;
 
+  MIB.setInstrAndDebugLoc(MI);
+
+  switch (Opc) {
+  case TargetOpcode::G_CONSTANT:
+    if (!selectConstant(MI, MIB, MRI))
+      return false;
+    break;
+  default:
     return false;
   }
 
+  MI.eraseFromParent();
+
+  return true;
+}
+
+bool RISCVInstructionSelector::selectConstant(MachineInstr &MI,
+                                              MachineIRBuilder &MIB,
+                                              MachineRegisterInfo &MRI) {
+  assert(MI.getOpcode() == TargetOpcode::G_CONSTANT);
+  Register FinalReg = MI.getOperand(0).getReg();
+  int64_t Imm = MI.getOperand(1).getCImm()->getSExtValue();
+
+  RISCVMatInt::InstSeq Seq =
+      RISCVMatInt::generateInstSeq(Imm, Subtarget->getFeatureBits());
+  unsigned NumInsts = Seq.size();
+
+  Register SrcReg = RISCV::X0;
+  Register DstReg;
+  MachineInstr *Result;
+  unsigned i;
+
+  for (i = 0; i < NumInsts; i++) {
+    DstReg = i < NumInsts - 1 ? MRI.createVirtualRegister(&RISCV::GPRRegClass)
+                              : FinalReg;
+    RISCVMatInt::Inst I = Seq[i];
+
+    switch (I.getOpndKind()) {
+    case RISCVMatInt::Imm:
+      Result = MIB.buildInstr(I.getOpcode()).addDef(DstReg).addImm(I.getImm());
+      break;
+    case RISCVMatInt::RegX0:
+      Result = MIB.buildInstr(I.getOpcode())
+                   .addDef(DstReg)
+                   .addReg(SrcReg)
+                   .addReg(RISCV::X0);
+      break;
+    case RISCVMatInt::RegReg:
+      Result = MIB.buildInstr(I.getOpcode())
+                   .addDef(DstReg)
+                   .addReg(SrcReg)
+                   .addReg(SrcReg);
+      break;
+    case RISCVMatInt::RegImm:
+      Result = MIB.buildInstr(I.getOpcode())
+                   .addDef(DstReg)
+                   .addReg(SrcReg)
+                   .addImm(I.getImm());
+      break;
+    }
+
+    if (!constrainSelectedInstRegOperands(*Result, TII, TRI, RBI))
+      return false;
+
+    SrcReg = DstReg;
+  }
+
+  return true;
+}
+
 namespace llvm {
 InstructionSelector *
 createRISCVInstructionSelector(const RISCVTargetMachine &TM,
                                RISCVSubtarget &Subtarget,
                                RISCVRegisterBankInfo &RBI) {
   return new RISCVInstructionSelector(TM, Subtarget, RBI);
 }
 } // end namespace llvm

llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant32.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \
+# RUN: | FileCheck %s
+---
+name:            const_i32_INT_MIN
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:            |
+  bb.0:
+    liveins: $x10
+
+    ; CHECK-LABEL: name: const_i32_INT_MIN
+    ; CHECK: liveins: $x10
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524288
+    ; CHECK-NEXT: $x10 = COPY [[LUI]]
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:gprb(s32) = G_CONSTANT i32 -2147483648
+    $x10 = COPY %0(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            const_i32_neg_2147483000
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:            |
+  bb.0:
+    liveins: $x10
+
+    ; CHECK-LABEL: name: const_i32_neg_2147483000
+    ; CHECK: liveins: $x10
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524288
+    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], 648
+    ; CHECK-NEXT: $x10 = COPY [[ADDI]]
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:gprb(s32) = G_CONSTANT i32 -2147483000
+    $x10 = COPY %0(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            const_i32_INT_MAX
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:            |
+  bb.0:
+    liveins: $x10
+
+    ; CHECK-LABEL: name: const_i32_INT_MAX
+    ; CHECK: liveins: $x10
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524288
+    ; CHECK-NEXT: $x10 = COPY [[LUI]]
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:gprb(s32) = G_CONSTANT i32 2147483648
+    $x10 = COPY %0(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            const_i32_2147483000
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:            |
+  bb.0:
+    liveins: $x10
+
+    ; CHECK-LABEL: name: const_i32_2147483000
+    ; CHECK: liveins: $x10
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524288
+    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], -648
+    ; CHECK-NEXT: $x10 = COPY [[ADDI]]
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:gprb(s32) = G_CONSTANT i32 2147483000
+    $x10 = COPY %0(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            const_i32_256
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:            |
+  bb.0:
+    liveins: $x10
+
+    ; CHECK-LABEL: name: const_i32_256
+    ; CHECK: liveins: $x10
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 256
+    ; CHECK-NEXT: $x10 = COPY [[ADDI]]
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:gprb(s32) = G_CONSTANT i32 256
+    $x10 = COPY %0(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            const_i32_0
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:            |
+  bb.0:
+    liveins: $x10
+
+    ; CHECK-LABEL: name: const_i32_0
+    ; CHECK: liveins: $x10
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 0
+    ; CHECK-NEXT: $x10 = COPY [[ADDI]]
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:gprb(s32) = G_CONSTANT i32 0
+    $x10 = COPY %0(s32)
+    PseudoRET implicit $x10
+
+...