[AMDGPU] Handle isUndef flag in LiveVariables::recomputeForSingleDefVirtReg

[vpykhtin]

Summary

A register's use with isUndef flags shouldn't be considered as a point where the register is live. LiveVariables::runOnInstr ignores such uses.

This was found when I tried to replace calls to

SIOptimizeVGPRLiveRange::updateLiveRangeInThenRegion
SIOptimizeVGPRLiveRange::updateLiveRangeInElseRegion

with LiveVariables::recomputeForSingleDefVirtReg.

In the testcase below %2 use is undef in the last REG_SEQUENCE.

CodeGen/AMDGPU/si-opt-vgpr-liverange-bug-deadlanes.mir failed:

# After SI Optimize VGPR LiveRange
# Machine code for function _amdgpu_ps_main: IsSSA, TracksLiveness
Function Live Ins: $vgpr0 in %0

bb.0:
  successors: %bb.1(0x40000000), %bb.2(0x40000000); %bb.1(50.00%), %bb.2(50.00%)
  liveins: $vgpr0
  %0:vgpr_32 = COPY killed $vgpr0
  %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
  %2:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN killed %0:vgpr_32, undef %5:sgpr_128, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32))
  %3:sreg_64 = V_CMP_NE_U32_e64 0, %2:vgpr_32, implicit $exec
  %7:sreg_64 = SI_IF killed %3:sreg_64, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  S_BRANCH %bb.1

bb.1:
; predecessors: %bb.0
  successors: %bb.2(0x80000000); %bb.2(100.00%)

  %8:vreg_128 = REG_SEQUENCE killed %1:vgpr_32, %subreg.sub0, %1:vgpr_32, %subreg.sub1, %1:vgpr_32, %subreg.sub2, undef %4.sub3:vreg_128, %subreg.sub3

bb.2:
; predecessors: %bb.0, %bb.1
  successors: %bb.3(0x40000000), %bb.4(0x40000000); %bb.3(50.00%), %bb.4(50.00%)

  %9:vreg_128 = PHI undef %10:vreg_128, %bb.0, %8:vreg_128, %bb.1
  %14:vgpr_32 = PHI %2:vgpr_32, %bb.0, undef %15:vgpr_32, %bb.1
  %11:sreg_64 = SI_ELSE killed %7:sreg_64, %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  S_BRANCH %bb.3

bb.3:
; predecessors: %bb.2
  successors: %bb.4(0x80000000); %bb.4(100.00%)

  %12:vreg_128 = REG_SEQUENCE killed %14:vgpr_32, %subreg.sub0, %14:vgpr_32, %subreg.sub1, %14:vgpr_32, %subreg.sub2, undef %6:vgpr_32, %subreg.sub3

bb.4:
; predecessors: %bb.2, %bb.3

  %13:vreg_128 = PHI %9:vreg_128, %bb.2, %12:vreg_128, %bb.3
  SI_END_CF killed %11:sreg_64, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  dead %4:vreg_128 = REG_SEQUENCE killed %13.sub2:vreg_128, %subreg.sub0, %13.sub2:vreg_128, %subreg.sub1, %13.sub2:vreg_128, %subreg.sub2, undef %2:vgpr_32, %subreg.sub3
  S_ENDPGM 0

# End machine code for function _amdgpu_ps_main.

*** Bad machine code: LiveVariables: Block should not be in AliveBlocks ***
- function:    _amdgpu_ps_main
- basic block: %bb.1  (0x55e17ebd7100)
Virtual register %2 is not needed live through the block.

*** Bad machine code: LiveVariables: Block should not be in AliveBlocks ***
- function:    _amdgpu_ps_main
- basic block: %bb.2  (0x55e17ebd7200)
Virtual register %2 is not needed live through the block.

*** Bad machine code: LiveVariables: Block should not be in AliveBlocks ***
- function:    _amdgpu_ps_main
- basic block: %bb.3  (0x55e17ebd7300)
Virtual register %2 is not needed live through the block.

[ruiling]

LGTM

[foad]

LGTM but can you come up with a test case?

[vpykhtin]

• Rebased.
• Added tests.

Tests have revealed another bug:

MachineInstr::readsRegister doesn't check isUndef flag, I've replaced it with readsWritesVirtualRegister(Reg).

[foad]

llvm/lib/CodeGen/LiveVariables.cpp

728

This is just readsVirtualRegister

[vpykhtin]

Replaced MI.readsWritesVirtualRegister(Reg).first with readsVirtualRegister.

[vpykhtin]

llvm/lib/CodeGen/LiveVariables.cpp

728

Thanks!

[foad]

llvm/unittests/MI/LiveIntervalTest.cpp

1 ↗

(On Diff #556150)

I don't understand this message - does clang-format want you to change something?

[vpykhtin]

llvm/unittests/MI/LiveIntervalTest.cpp

1 ↗

(On Diff #556150)

It wants me to format most of the source, I didn't include that formatting as would create a lot of unrelated changes.

Maybe it worth to format the entire source after the commit.

[foad]

llvm/unittests/MI/LiveIntervalTest.cpp

1 ↗

(On Diff #556150)

It wants me to format most of the source

Generally you should run "git clang-format @^" to reformat only the parts that your patch has modified.

[vpykhtin]

llvm/unittests/MI/LiveIntervalTest.cpp

1 ↗

(On Diff #556150)

Thank you, I didn't know that. I've relied on the formatting of arc diff.

llvm/lib/CodeGen/LiveVariables.cpp

void LiveVariables::recomputeForSingleDefVirtReg(Register Reg) {
 
   VarInfo &VI = getVarInfo(Reg);
   VI.AliveBlocks.clear();
   VI.Kills.clear();
 
   MachineInstr &DefMI = *MRI->getUniqueVRegDef(Reg);
   MachineBasicBlock &DefBB = *DefMI.getParent();
 
-  // Handle the case where all uses have been removed.
-  if (MRI->use_nodbg_empty(Reg)) {
-    VI.Kills.push_back(&DefMI);
-    DefMI.addRegisterDead(Reg, nullptr);
-    return;
-  }
-  DefMI.clearRegisterDeads(Reg);
-
   // Initialize a worklist of BBs that Reg is live-to-end of. (Here
   // "live-to-end" means Reg is live at the end of a block even if it is only
   // live because of phi uses in a successor. This is different from isLiveOut()
   // which does not consider phi uses.)
   SmallVector<MachineBasicBlock *> LiveToEndBlocks;
   SparseBitVector<> UseBlocks;
+  unsigned NumRealUses = 0;
   for (auto &UseMO : MRI->use_nodbg_operands(Reg)) {
     UseMO.setIsKill(false);
+    if (!UseMO.readsReg())
+      continue;
+    ++NumRealUses;
     MachineInstr &UseMI = *UseMO.getParent();
     MachineBasicBlock &UseBB = *UseMI.getParent();
     UseBlocks.set(UseBB.getNumber());
     if (UseMI.isPHI()) {
       // If Reg is used in a phi then it is live-to-end of the corresponding
       // predecessor.
       unsigned Idx = UseMO.getOperandNo();
       LiveToEndBlocks.push_back(UseMI.getOperand(Idx + 1).getMBB());
     } else if (&UseBB == &DefBB) {
       // A non-phi use in the same BB as the single def must come after the def.
     } else {
       // Otherwise Reg must be live-to-end of all predecessors.
       LiveToEndBlocks.append(UseBB.pred_begin(), UseBB.pred_end());
     }
   }
 
+  // Handle the case where all uses have been removed.
+  if (NumRealUses == 0) {
+    VI.Kills.push_back(&DefMI);
+    DefMI.addRegisterDead(Reg, nullptr);
+    return;
+  }
+  DefMI.clearRegisterDeads(Reg);
+
   // Iterate over the worklist adding blocks to AliveBlocks.
   bool LiveToEndOfDefBB = false;
   while (!LiveToEndBlocks.empty()) {
     MachineBasicBlock &BB = *LiveToEndBlocks.pop_back_val();
     if (&BB == &DefBB) {
       LiveToEndOfDefBB = true;
       continue;
     }
for (unsigned UseBBNum : UseBlocks) {
     MachineBasicBlock &UseBB = *MF->getBlockNumbered(UseBBNum);
     if (&UseBB == &DefBB && LiveToEndOfDefBB)
       continue;
     for (auto &MI : reverse(UseBB)) {
       if (MI.isDebugOrPseudoInstr())
         continue;
       if (MI.isPHI())
         break;
       if (MI.readsRegister(Reg)) {
         assert(!MI.killsRegister(Reg));
         MI.addRegisterKilled(Reg, nullptr);
         VI.Kills.push_back(&MI);
         break;
       }
     }
   }
 }